forked from ~ljy/RK356X_SDK_RELEASE
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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
....@@ -4,13 +4,17 @@
44  * Author: Andy Yan <andy.yan@rock-chips.com>
55  */
66 
7
-#include <drm/drmP.h>
87 #include <linux/kernel.h>
98 #include <linux/component.h>
9
+#include <linux/of.h>
10
+#include <linux/platform_device.h>
1011 #include <dt-bindings/display/rockchip_vop.h>
1112 
13
+#include <drm/drm_fourcc.h>
14
+#include <drm/drm_print.h>
1215 #include "rockchip_drm_vop.h"
1316 #include "rockchip_vop_reg.h"
17
+#include "rockchip_drm_drv.h"
1418 
1519 #define _VOP_REG(off, _mask, _shift, _write_mask) \
1620 		{ \
....@@ -27,6 +31,10 @@
2731 		_VOP_REG(off, _mask, s, true)
2832 
2933 static const uint32_t formats_for_cluster[] = {
34
+	DRM_FORMAT_XRGB2101010,
35
+	DRM_FORMAT_ARGB2101010,
36
+	DRM_FORMAT_XBGR2101010,
37
+	DRM_FORMAT_ABGR2101010,
3038 	DRM_FORMAT_XRGB8888,
3139 	DRM_FORMAT_ARGB8888,
3240 	DRM_FORMAT_XBGR8888,
....@@ -35,15 +43,69 @@
3543 	DRM_FORMAT_BGR888,
3644 	DRM_FORMAT_RGB565,
3745 	DRM_FORMAT_BGR565,
38
-	DRM_FORMAT_NV12,
39
-	DRM_FORMAT_NV16,
40
-	DRM_FORMAT_NV24,
41
-	DRM_FORMAT_NV12_10,
42
-	DRM_FORMAT_NV16_10,
43
-	DRM_FORMAT_NV24_10,
46
+	DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
47
+	DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
4448 	DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
49
+	DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
4550 };
4651 
52
+static const uint32_t formats_for_vop3_cluster[] = {
53
+	DRM_FORMAT_XRGB2101010,
54
+	DRM_FORMAT_ARGB2101010,
55
+	DRM_FORMAT_XBGR2101010,
56
+	DRM_FORMAT_ABGR2101010,
57
+	DRM_FORMAT_XRGB8888,
58
+	DRM_FORMAT_ARGB8888,
59
+	DRM_FORMAT_XBGR8888,
60
+	DRM_FORMAT_ABGR8888,
61
+	DRM_FORMAT_RGB888,
62
+	DRM_FORMAT_BGR888,
63
+	DRM_FORMAT_RGB565,
64
+	DRM_FORMAT_BGR565,
65
+	DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
66
+	DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
67
+	DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
68
+	DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
69
+	DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
70
+	DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
71
+	DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
72
+#ifdef CONFIG_NO_GKI
73
+	DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
74
+	DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
75
+#endif
76
+	DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
77
+	DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
78
+	DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
79
+	DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
80
+};
81
+
82
+static const uint32_t formats_for_esmart[] = {
83
+	DRM_FORMAT_XRGB8888,
84
+	DRM_FORMAT_ARGB8888,
85
+	DRM_FORMAT_XBGR8888,
86
+	DRM_FORMAT_ABGR8888,
87
+	DRM_FORMAT_RGB888,
88
+	DRM_FORMAT_BGR888,
89
+	DRM_FORMAT_RGB565,
90
+	DRM_FORMAT_BGR565,
91
+	DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
92
+	DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
93
+	DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
94
+	DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
95
+	DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
96
+	DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
97
+	DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
98
+#ifdef CONFIG_NO_GKI
99
+	DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
100
+	DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
101
+#endif
102
+	DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */
103
+	DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */
104
+	DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
105
+	DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
106
+};
107
+
108
+/* RK356x can't support uv swap for YUYV and UYVY */
47109 static const uint32_t formats_for_rk356x_esmart[] = {
48110 	DRM_FORMAT_XRGB8888,
49111 	DRM_FORMAT_ARGB8888,
....@@ -53,14 +115,16 @@
53115 	DRM_FORMAT_BGR888,
54116 	DRM_FORMAT_RGB565,
55117 	DRM_FORMAT_BGR565,
56
-	DRM_FORMAT_NV12,
57
-	DRM_FORMAT_NV16,
58
-	DRM_FORMAT_NV24,
59
-	DRM_FORMAT_NV12_10,
60
-	DRM_FORMAT_NV16_10,
61
-	DRM_FORMAT_NV24_10,
62
-	DRM_FORMAT_YVYU,
63
-	DRM_FORMAT_VYUY,
118
+	DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
119
+	DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
120
+	DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
121
+	DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
122
+#ifdef CONFIG_NO_GKI
123
+	DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
124
+	DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
125
+#endif
126
+	DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
127
+	DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
64128 };
65129 
66130 static const uint32_t formats_for_smart[] = {
....@@ -120,6 +184,88 @@
120184 				AFBC_FORMAT_MOD_YTR |
121185 				AFBC_FORMAT_MOD_SPARSE |
122186 				AFBC_FORMAT_MOD_SPLIT),
187
+
188
+	DRM_FORMAT_MOD_LINEAR,
189
+	DRM_FORMAT_MOD_INVALID,
190
+};
191
+
192
+static const uint64_t format_modifiers_afbc_no_linear_mode[] = {
193
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
194
+
195
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
196
+				AFBC_FORMAT_MOD_SPARSE),
197
+
198
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
199
+				AFBC_FORMAT_MOD_YTR),
200
+
201
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
202
+				AFBC_FORMAT_MOD_CBR),
203
+
204
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
205
+				AFBC_FORMAT_MOD_YTR |
206
+				AFBC_FORMAT_MOD_SPARSE),
207
+
208
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
209
+				AFBC_FORMAT_MOD_CBR |
210
+				AFBC_FORMAT_MOD_SPARSE),
211
+
212
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
213
+				AFBC_FORMAT_MOD_YTR |
214
+				AFBC_FORMAT_MOD_CBR),
215
+
216
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
217
+				AFBC_FORMAT_MOD_YTR |
218
+				AFBC_FORMAT_MOD_CBR |
219
+				AFBC_FORMAT_MOD_SPARSE),
220
+
221
+	/* SPLIT mandates SPARSE, RGB modes mandates YTR */
222
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
223
+				AFBC_FORMAT_MOD_YTR |
224
+				AFBC_FORMAT_MOD_SPARSE |
225
+				AFBC_FORMAT_MOD_SPLIT),
226
+	DRM_FORMAT_MOD_INVALID,
227
+};
228
+
229
+static const uint64_t format_modifiers_afbc_tiled[] = {
230
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
231
+
232
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
233
+				AFBC_FORMAT_MOD_SPARSE),
234
+
235
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
236
+				AFBC_FORMAT_MOD_YTR),
237
+
238
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
239
+				AFBC_FORMAT_MOD_CBR),
240
+
241
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
242
+				AFBC_FORMAT_MOD_YTR |
243
+				AFBC_FORMAT_MOD_SPARSE),
244
+
245
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
246
+				AFBC_FORMAT_MOD_CBR |
247
+				AFBC_FORMAT_MOD_SPARSE),
248
+
249
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
250
+				AFBC_FORMAT_MOD_YTR |
251
+				AFBC_FORMAT_MOD_CBR),
252
+
253
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
254
+				AFBC_FORMAT_MOD_YTR |
255
+				AFBC_FORMAT_MOD_CBR |
256
+				AFBC_FORMAT_MOD_SPARSE),
257
+
258
+	/* SPLIT mandates SPARSE, RGB modes mandates YTR */
259
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
260
+				AFBC_FORMAT_MOD_YTR |
261
+				AFBC_FORMAT_MOD_SPARSE |
262
+				AFBC_FORMAT_MOD_SPLIT),
263
+
264
+	DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_8x8),
265
+	DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0),
266
+	DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE1),
267
+
268
+	DRM_FORMAT_MOD_LINEAR,
123269 	DRM_FORMAT_MOD_INVALID,
124270 };
125271 
....@@ -364,6 +510,16 @@
364510 
365511 };
366512 
513
+static const struct vop_intr rk3528_vop_axi_intr[] = {
514
+	{
515
+	  .intrs = rk3568_vop_axi_intrs,
516
+	  .nintrs = ARRAY_SIZE(rk3568_vop_axi_intrs),
517
+	  .status = VOP_REG(RK3568_SYS0_INT_STATUS, 0xfe, 0),
518
+	  .enable = VOP_REG_MASK(RK3568_SYS0_INT_EN, 0xfe, 0),
519
+	  .clear = VOP_REG_MASK(RK3568_SYS0_INT_CLR, 0xfe, 0),
520
+	},
521
+};
522
+
367523 static const struct vop_intr rk3568_vop_axi_intr[] = {
368524 	{
369525 	  .intrs = rk3568_vop_axi_intrs,
....@@ -422,6 +578,175 @@
422578 	.clear = VOP_REG_MASK(RK3568_VP2_INT_CLR, 0xffff, 0),
423579 };
424580 
581
+static const struct vop_intr rk3588_vp3_intr = {
582
+	.intrs = rk3568_vop_intrs,
583
+	.nintrs = ARRAY_SIZE(rk3568_vop_intrs),
584
+	.line_flag_num[0] = VOP_REG(RK3588_VP3_LINE_FLAG, 0x1fff, 0),
585
+	.line_flag_num[1] = VOP_REG(RK3588_VP3_LINE_FLAG, 0x1fff, 16),
586
+	.status = VOP_REG(RK3588_VP3_INT_STATUS, 0xffff, 0),
587
+	.enable = VOP_REG_MASK(RK3588_VP3_INT_EN, 0xffff, 0),
588
+	.clear = VOP_REG_MASK(RK3588_VP3_INT_CLR, 0xffff, 0),
589
+};
590
+
591
+static const struct vop2_dsc_regs rk3588_vop_dsc_8k_regs = {
592
+	/* DSC SYS CTRL */
593
+	.dsc_port_sel = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 0),
594
+	.dsc_man_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 2),
595
+	.dsc_interface_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 4),
596
+	.dsc_pixel_num = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 6),
597
+	.dsc_pxl_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 8),
598
+	.dsc_cds_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 12),
599
+	.dsc_txp_clk_div = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x3, 14),
600
+	.dsc_init_dly_mode = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 16),
601
+	.dsc_scan_en = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 17),
602
+	.dsc_halt_en = VOP_REG(RK3588_DSC_8K_SYS_CTRL, 0x1, 18),
603
+	.rst_deassert = VOP_REG(RK3588_DSC_8K_RST, 0x1, 0),
604
+	.dsc_flush = VOP_REG(RK3588_DSC_8K_RST, 0x1, 16),
605
+	.dsc_cfg_done = VOP_REG(RK3588_DSC_8K_CFG_DONE, 0x1, 0),
606
+	.dsc_init_dly_num = VOP_REG(RK3588_DSC_8K_INIT_DLY, 0xffff, 0),
607
+	.scan_timing_para_imd_en = VOP_REG(RK3588_DSC_8K_INIT_DLY, 0x1, 16),
608
+	.dsc_htotal_pw = VOP_REG(RK3588_DSC_8K_HTOTAL_HS_END, 0xffffffff, 0),
609
+	.dsc_hact_st_end = VOP_REG(RK3588_DSC_8K_HACT_ST_END, 0xffffffff, 0),
610
+	.dsc_vtotal = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffff, 16),
611
+	.dsc_vs_end = VOP_REG(RK3588_DSC_8K_VTOTAL_VS_END, 0xffff, 0),
612
+	.dsc_vact_st_end = VOP_REG(RK3588_DSC_8K_VACT_ST_END, 0xffffffff, 0),
613
+	.dsc_error_status = VOP_REG(RK3588_DSC_8K_STATUS, 0x1, 0),
614
+
615
+	/* DSC encoder */
616
+	.dsc_pps0_3 = VOP_REG(RK3588_DSC_8K_PPS0_3, 0xffffffff, 0),
617
+	.dsc_en = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 0),
618
+	.dsc_rbit = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 2),
619
+	.dsc_rbyt = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 3),
620
+	.dsc_flal = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 4),
621
+	.dsc_mer = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 5),
622
+	.dsc_epb = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 6),
623
+	.dsc_epl = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 7),
624
+	.dsc_nslc = VOP_REG(RK3588_DSC_8K_CTRL0, 0x7, 16),
625
+	.dsc_sbo = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 28),
626
+	.dsc_ifep = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 29),
627
+	.dsc_pps_upd = VOP_REG(RK3588_DSC_8K_CTRL0, 0x1, 31),
628
+	.dsc_status = VOP_REG(RK3588_DSC_8K_STS0, 0xffffffff, 0),
629
+	.dsc_ecw = VOP_REG(RK3588_DSC_8K_ERS, 0xffffffff, 0),
630
+};
631
+
632
+static const struct vop2_dsc_regs rk3588_vop_dsc_4k_regs = {
633
+	/* DSC SYS CTRL */
634
+	.dsc_port_sel = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 0),
635
+	.dsc_man_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 2),
636
+	.dsc_interface_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 4),
637
+	.dsc_pixel_num = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 6),
638
+	.dsc_pxl_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 8),
639
+	.dsc_cds_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 12),
640
+	.dsc_txp_clk_div = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x3, 14),
641
+	.dsc_init_dly_mode = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 16),
642
+	.dsc_scan_en = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 17),
643
+	.dsc_halt_en = VOP_REG(RK3588_DSC_4K_SYS_CTRL, 0x1, 18),
644
+	.rst_deassert = VOP_REG(RK3588_DSC_4K_RST, 0x1, 0),
645
+	.dsc_flush = VOP_REG(RK3588_DSC_4K_RST, 0x1, 16),
646
+	.dsc_cfg_done = VOP_REG(RK3588_DSC_4K_CFG_DONE, 0x1, 0),
647
+	.dsc_init_dly_num = VOP_REG(RK3588_DSC_4K_INIT_DLY, 0xffff, 0),
648
+	.scan_timing_para_imd_en = VOP_REG(RK3588_DSC_4K_INIT_DLY, 0x1, 16),
649
+	.dsc_htotal_pw = VOP_REG(RK3588_DSC_4K_HTOTAL_HS_END, 0xffffffff, 0),
650
+	.dsc_hact_st_end = VOP_REG(RK3588_DSC_4K_HACT_ST_END, 0xffffffff, 0),
651
+	.dsc_vtotal = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffff, 16),
652
+	.dsc_vs_end = VOP_REG(RK3588_DSC_4K_VTOTAL_VS_END, 0xffff, 0),
653
+	.dsc_vact_st_end = VOP_REG(RK3588_DSC_4K_VACT_ST_END, 0xffffffff, 0),
654
+	.dsc_error_status = VOP_REG(RK3588_DSC_4K_STATUS, 0x1, 0),
655
+
656
+	/* DSC encoder */
657
+	.dsc_pps0_3 = VOP_REG(RK3588_DSC_4K_PPS0_3, 0xffffffff, 0),
658
+	.dsc_en = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 0),
659
+	.dsc_rbit = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 2),
660
+	.dsc_rbyt = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 3),
661
+	.dsc_flal = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 4),
662
+	.dsc_mer = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 5),
663
+	.dsc_epb = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 6),
664
+	.dsc_epl = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 7),
665
+	.dsc_nslc = VOP_REG(RK3588_DSC_4K_CTRL0, 0x7, 16),
666
+	.dsc_sbo = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 28),
667
+	.dsc_ifep = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 29),
668
+	.dsc_pps_upd = VOP_REG(RK3588_DSC_4K_CTRL0, 0x1, 31),
669
+	.dsc_status = VOP_REG(RK3588_DSC_4K_STS0, 0xffffffff, 0),
670
+	.dsc_ecw = VOP_REG(RK3588_DSC_4K_ERS, 0xffffffff, 0),
671
+};
672
+
673
+static const struct dsc_error_info dsc_ecw[] = {
674
+	{0x00000000, "no error detected by DSC encoder"},
675
+	{0x0030ffff, "bits per component error"},
676
+	{0x0040ffff, "multiple mode error"},
677
+	{0x0050ffff, "line buffer depth error"},
678
+	{0x0060ffff, "minor version error"},
679
+	{0x0070ffff, "picture height error"},
680
+	{0x0080ffff, "picture width error"},
681
+	{0x0090ffff, "number of slices error"},
682
+	{0x00c0ffff, "slice height Error "},
683
+	{0x00d0ffff, "slice width error"},
684
+	{0x00e0ffff, "second line BPG offset error"},
685
+	{0x00f0ffff, "non second line BPG offset error"},
686
+	{0x0100ffff, "PPS ID error"},
687
+	{0x0110ffff, "bits per pixel (BPP) Error"},
688
+	{0x0120ffff, "buffer flow error"},  /* dsc_buffer_flow */
689
+
690
+	{0x01510001, "slice 0 RC buffer model overflow error"},
691
+	{0x01510002, "slice 1 RC buffer model overflow error"},
692
+	{0x01510004, "slice 2 RC buffer model overflow error"},
693
+	{0x01510008, "slice 3 RC buffer model overflow error"},
694
+	{0x01510010, "slice 4 RC buffer model overflow error"},
695
+	{0x01510020, "slice 5 RC buffer model overflow error"},
696
+	{0x01510040, "slice 6 RC buffer model overflow error"},
697
+	{0x01510080, "slice 7 RC buffer model overflow error"},
698
+
699
+	{0x01610001, "slice 0 RC buffer model underflow error"},
700
+	{0x01610002, "slice 1 RC buffer model underflow error"},
701
+	{0x01610004, "slice 2 RC buffer model underflow error"},
702
+	{0x01610008, "slice 3 RC buffer model underflow error"},
703
+	{0x01610010, "slice 4 RC buffer model underflow error"},
704
+	{0x01610020, "slice 5 RC buffer model underflow error"},
705
+	{0x01610040, "slice 6 RC buffer model underflow error"},
706
+	{0x01610080, "slice 7 RC buffer model underflow error"},
707
+
708
+	{0xffffffff, "unsuccessful RESET cycle status"},
709
+	{0x00a0ffff, "ICH full error precision settings error"},
710
+	{0x0020ffff, "native mode"},
711
+};
712
+
713
+static const struct dsc_error_info dsc_buffer_flow[] = {
714
+	{0x00000000, "rate buffer status"},
715
+	{0x00000001, "line buffer status"},
716
+	{0x00000002, "decoder model status"},
717
+	{0x00000003, "pixel buffer status"},
718
+	{0x00000004, "balance fifo buffer status"},
719
+	{0x00000005, "syntax element fifo status"},
720
+};
721
+
722
+static const struct vop2_dsc_data rk3588_vop_dsc_data[] = {
723
+	{
724
+	 .id = ROCKCHIP_VOP2_DSC_8K,
725
+	 .pd_id = VOP2_PD_DSC_8K,
726
+	 .max_slice_num = 8,
727
+	 .max_linebuf_depth = 11,
728
+	 .min_bits_per_pixel = 8,
729
+	 .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src",
730
+	 .dsc_txp_clk_name = "dsc_8k_txp_clk",
731
+	 .dsc_pxl_clk_name = "dsc_8k_pxl_clk",
732
+	 .dsc_cds_clk_name = "dsc_8k_cds_clk",
733
+	 .regs = &rk3588_vop_dsc_8k_regs,
734
+	},
735
+
736
+	{
737
+	 .id = ROCKCHIP_VOP2_DSC_4K,
738
+	 .pd_id = VOP2_PD_DSC_4K,
739
+	 .max_slice_num = 2,
740
+	 .max_linebuf_depth = 11,
741
+	 .min_bits_per_pixel = 8,
742
+	 .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src",
743
+	 .dsc_txp_clk_name = "dsc_4k_txp_clk",
744
+	 .dsc_pxl_clk_name = "dsc_4k_pxl_clk",
745
+	 .dsc_cds_clk_name = "dsc_4k_cds_clk",
746
+	 .regs = &rk3588_vop_dsc_4k_regs,
747
+	},
748
+};
749
+
425750 static const struct vop2_wb_regs rk3568_vop_wb_regs = {
426751 	.enable = VOP_REG(RK3568_WB_CTRL, 0x1, 0),
427752 	.format = VOP_REG(RK3568_WB_CTRL, 0x7, 1),
....@@ -446,6 +771,288 @@
446771 	.regs = &rk3568_vop_wb_regs,
447772 };
448773 
774
+static const struct vop2_video_port_regs rk3528_vop_vp0_regs = {
775
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
776
+	.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
777
+	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
778
+	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
779
+	.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
780
+	.dclk_div2 = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 4),
781
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 5),
782
+	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
783
+	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
784
+	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
785
+	.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
786
+	.dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13),
787
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
788
+	.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
789
+	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
790
+	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
791
+	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
792
+	.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
793
+	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
794
+	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
795
+	.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xffff, 0),
796
+	.bg_dly = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xff, 24),
797
+	.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
798
+	.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
799
+	.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
800
+	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
801
+	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
802
+	.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
803
+	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
804
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
805
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
806
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
807
+	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
808
+	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
809
+	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
810
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
811
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
812
+	.layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0),
813
+	.hdr_src_color_ctrl = VOP_REG(RK3528_HDR_SRC_COLOR_CTRL, 0xffffffff, 0),
814
+	.hdr_dst_color_ctrl = VOP_REG(RK3528_HDR_DST_COLOR_CTRL, 0xffffffff, 0),
815
+	.hdr_src_alpha_ctrl = VOP_REG(RK3528_HDR_SRC_ALPHA_CTRL, 0xffffffff, 0),
816
+	.hdr_dst_alpha_ctrl = VOP_REG(RK3528_HDR_DST_ALPHA_CTRL, 0xffffffff, 0),
817
+	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
818
+	.hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
819
+	.hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
820
+	.hdr_lut_fetch_done = VOP_REG(RK3528_HDR_LUT_STATUS, 0x1, 0),
821
+	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
822
+	.sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 5),
823
+	.sdr2hdr_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 0),
824
+	.sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 1),
825
+	.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 2),
826
+	.sdr2hdr_dstmode = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
827
+	.hdr_vivid_en = VOP_REG(RK3528_HDRVIVID_CTRL, 0x1, 0),
828
+	.hdr_vivid_bypass_en = VOP_REG(RK3528_HDRVIVID_CTRL, 0x1, 2),
829
+	.hdr_vivid_path_mode = VOP_REG(RK3528_HDRVIVID_CTRL, 0x7, 3),
830
+	.hdr_vivid_dstgamut = VOP_REG(RK3528_HDRVIVID_CTRL, 0x1, 6),
831
+	.acm_bypass_en = VOP_REG(RK3528_VP0_ACM_CTRL, 0x1, 0),
832
+	.csc_en = VOP_REG(RK3528_VP0_ACM_CTRL, 0x1, 1),
833
+	.acm_r2y_en = VOP_REG(RK3528_VP0_ACM_CTRL, 0x1, 2),
834
+	.csc_mode = VOP_REG(RK3528_VP0_ACM_CTRL, 0x7, 3),
835
+	.acm_r2y_mode = VOP_REG(RK3528_VP0_ACM_CTRL, 0x7, 8),
836
+	.csc_coe00 = VOP_REG(RK3528_VP0_ACM_CTRL, 0xffff, 16),
837
+	.csc_coe01 = VOP_REG(RK3528_VP0_CSC_COE01_02, 0xffff, 0),
838
+	.csc_coe02 = VOP_REG(RK3528_VP0_CSC_COE01_02, 0xffff, 16),
839
+	.csc_coe10 = VOP_REG(RK3528_VP0_CSC_COE10_11, 0xffff, 0),
840
+	.csc_coe11 = VOP_REG(RK3528_VP0_CSC_COE10_11, 0xffff, 16),
841
+	.csc_coe12 = VOP_REG(RK3528_VP0_CSC_COE12_20, 0xffff, 0),
842
+	.csc_coe20 = VOP_REG(RK3528_VP0_CSC_COE12_20, 0xffff, 16),
843
+	.csc_coe21 = VOP_REG(RK3528_VP0_CSC_COE21_22, 0xffff, 0),
844
+	.csc_coe22 = VOP_REG(RK3528_VP0_CSC_COE21_22, 0xffff, 16),
845
+	.csc_offset0 = VOP_REG(RK3528_VP0_CSC_OFFSET0, 0xffffffff, 0),
846
+	.csc_offset1 = VOP_REG(RK3528_VP0_CSC_OFFSET1, 0xffffffff, 0),
847
+	.csc_offset2 = VOP_REG(RK3528_VP0_CSC_OFFSET2, 0xffffffff, 0),
848
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
849
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
850
+};
851
+
852
+static const struct vop2_video_port_regs rk3528_vop_vp1_regs = {
853
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
854
+	.overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0),
855
+	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
856
+	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
857
+	.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
858
+	.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
859
+	.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
860
+	.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
861
+	.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
862
+	.dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13),
863
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
864
+	.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
865
+	.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
866
+	.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
867
+	.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
868
+	.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),
869
+	.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
870
+	.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
871
+	.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xffff, 0),
872
+	.bg_dly = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xff, 24),
873
+	.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
874
+	.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
875
+	.vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
876
+	.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
877
+	.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
878
+	.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0xffffffff, 0),
879
+	.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0xffffffff, 0),
880
+	.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
881
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15),
882
+	.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
883
+	.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
884
+	.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
885
+	.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
886
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
887
+	.bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
888
+	.bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
889
+	.bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20),
890
+	.bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30),
891
+	.bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0),
892
+	.bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16),
893
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6),
894
+	.bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4),
895
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
896
+	.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
897
+	.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
898
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
899
+	.layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0),
900
+	.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
901
+	.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
902
+};
903
+
904
+static const struct vop3_ovl_mix_regs rk3528_vop_hdr_mix_regs = {
905
+	.src_color_ctrl = VOP_REG(RK3528_HDR_SRC_COLOR_CTRL, 0xffffffff, 0),
906
+	.dst_color_ctrl = VOP_REG(RK3528_HDR_DST_COLOR_CTRL, 0xffffffff, 0),
907
+	.src_alpha_ctrl = VOP_REG(RK3528_HDR_SRC_ALPHA_CTRL, 0xffffffff, 0),
908
+	.dst_alpha_ctrl = VOP_REG(RK3528_HDR_DST_ALPHA_CTRL, 0xffffffff, 0),
909
+};
910
+
911
+static const struct vop3_ovl_mix_regs rk3528_vop_vp0_layer_mix_regs = {
912
+	.src_color_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
913
+	.dst_color_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
914
+	.src_alpha_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
915
+	.dst_alpha_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
916
+};
917
+
918
+static const struct vop3_ovl_mix_regs rk3528_vop_vp1_layer_mix_regs = {
919
+	.src_color_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
920
+	.dst_color_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
921
+	.src_alpha_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
922
+	.dst_alpha_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
923
+};
924
+
925
+static const struct vop3_ovl_regs rk3528_vop_vp0_ovl_regs = {
926
+	.layer_mix_regs = &rk3528_vop_vp0_layer_mix_regs,
927
+	.hdr_mix_regs = &rk3528_vop_hdr_mix_regs,
928
+};
929
+
930
+static const struct vop3_ovl_regs rk3528_vop_vp1_ovl_regs = {
931
+	.layer_mix_regs = &rk3528_vop_vp1_layer_mix_regs,
932
+};
933
+
934
+static const struct vop2_video_port_data rk3528_vop_video_ports[] = {
935
+	{
936
+	 .id = 0,
937
+	 .soc_id = { 0x3528, 0x3528 },
938
+	 .lut_dma_rid = 14,
939
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_VIVID_HDR |
940
+		    VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC | VOP_FEATURE_OUTPUT_10BIT,
941
+	 .gamma_lut_len = 1024,
942
+	 .max_output = { 4096, 4096 },
943
+	 .hdrvivid_dly = {17, 29, 32, 44, 15, 38, 1, 29, 0, 0},
944
+	 .sdr2hdr_dly = 21,
945
+	 .layer_mix_dly = 6,
946
+	 .hdr_mix_dly = 2,
947
+	 .win_dly = 8,
948
+	 .intr = &rk3568_vp0_intr,
949
+	 .regs = &rk3528_vop_vp0_regs,
950
+	 .ovl_regs = &rk3528_vop_vp0_ovl_regs,
951
+	},
952
+	{
953
+	 .id = 1,
954
+	 .soc_id = { 0x3528, 0x3528 },
955
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
956
+	 .max_output = { 720, 576 },
957
+	 .hdrvivid_dly = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
958
+	 .sdr2hdr_dly = 0,
959
+	 .layer_mix_dly = 2,
960
+	 .hdr_mix_dly = 0,
961
+	 .win_dly = 8,
962
+	 .intr = &rk3568_vp1_intr,
963
+	 .regs = &rk3528_vop_vp1_regs,
964
+	 .ovl_regs = &rk3528_vop_vp1_ovl_regs,
965
+	},
966
+};
967
+
968
+static const struct vop2_video_port_regs rk3562_vop_vp0_regs = {
969
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
970
+	.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
971
+	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
972
+	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
973
+	.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
974
+	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
975
+	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
976
+	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
977
+	.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
978
+	.dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13),
979
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
980
+	.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
981
+	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
982
+	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
983
+	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
984
+	.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
985
+	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
986
+	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
987
+	.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xffff, 0),
988
+	.bg_dly = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xff, 24),
989
+	.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
990
+	.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
991
+	.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
992
+	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
993
+	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
994
+	.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
995
+	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
996
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
997
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
998
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
999
+	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
1000
+	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1001
+	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1002
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1003
+	.bcsh_brightness = VOP_REG(RK3568_VP0_BCSH_BCS, 0xff, 0),
1004
+	.bcsh_contrast = VOP_REG(RK3568_VP0_BCSH_BCS, 0x1ff, 8),
1005
+	.bcsh_sat_con = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3ff, 20),
1006
+	.bcsh_out_mode = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3, 30),
1007
+	.bcsh_sin_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 0),
1008
+	.bcsh_cos_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 16),
1009
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 6),
1010
+	.bcsh_r2y_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 4),
1011
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2),
1012
+	.bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0),
1013
+	.bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31),
1014
+	.edpi_te_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 28),
1015
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 30),
1016
+	.edpi_wms_fs = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 31),
1017
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1018
+	.cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
1019
+	.cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
1020
+	.cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
1021
+
1022
+	.mcu_pix_total = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 0),
1023
+	.mcu_cs_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 6),
1024
+	.mcu_cs_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 10),
1025
+	.mcu_rw_pst = VOP_REG(RK3562_VP0_MCU_CTRL, 0xf, 16),
1026
+	.mcu_rw_pend = VOP_REG(RK3562_VP0_MCU_CTRL, 0x3f, 20),
1027
+	.mcu_hold_mode = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 27),
1028
+	.mcu_frame_st = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 28),
1029
+	.mcu_rs = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 29),
1030
+	.mcu_bypass = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 30),
1031
+	.mcu_type = VOP_REG(RK3562_VP0_MCU_CTRL, 0x1, 31),
1032
+	.mcu_rw_bypass_port = VOP_REG(RK3562_VP0_MCU_RW_BYPASS_PORT, 0xffffffff, 0),
1033
+	.layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0),
1034
+
1035
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
1036
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
1037
+};
1038
+
1039
+static const struct vop2_video_port_data rk3562_vop_video_ports[] = {
1040
+	{
1041
+	 .id = 0,
1042
+	 .soc_id = { 0x3562, 0x3562 },
1043
+	 .lut_dma_rid = 14,
1044
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
1045
+	 .gamma_lut_len = 1024,
1046
+	 .cubic_lut_len = 729, /* 9x9x9 */
1047
+	 .max_output = { 2048, 4096 },
1048
+	 .win_dly = 8,
1049
+	 .layer_mix_dly = 8,
1050
+	 .intr = &rk3568_vp0_intr,
1051
+	 .regs = &rk3562_vop_vp0_regs,
1052
+	 .ovl_regs = &rk3528_vop_vp0_ovl_regs,
1053
+	},
1054
+};
1055
+
4491056 static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
4501057 	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
4511058 	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
....@@ -454,8 +1061,8 @@
4541061 	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
4551062 	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
4561063 	.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
457
-	.dclk_div2 = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 4),
458
-	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 5),
1064
+	.dclk_div2 = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 4),
1065
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 5),
4591066 	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
4601067 	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
4611068 	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
....@@ -470,7 +1077,8 @@
4701077 	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
4711078 	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
4721079 	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0x1fff1fff, 0),
473
-	.vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1080
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
1081
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
4741082 	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
4751083 	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
4761084 	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -479,8 +1087,8 @@
4791087 	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
4801088 	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
4811089 	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
482
-	.mipi_dual_en = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 20),
483
-	.mipi_dual_channel_swap = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 21),
1090
+	.dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20),
1091
+	.dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21),
4841092 	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
4851093 	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
4861094 	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
....@@ -527,6 +1135,9 @@
5271135 	.cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
5281136 	.cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
5291137 	.cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
1138
+
1139
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
1140
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
5301141 };
5311142 
5321143 static const struct vop2_video_port_regs rk3568_vop_vp1_regs = {
....@@ -537,8 +1148,8 @@
5371148 	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
5381149 	.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
5391150 	.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
540
-	.dclk_div2 = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 4),
541
-	.dclk_div2_phase_lock = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 5),
1151
+	.dclk_div2 = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 4),
1152
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 5),
5421153 	.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
5431154 	.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
5441155 	.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
....@@ -553,7 +1164,8 @@
5531164 	.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
5541165 	.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
5551166 	.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
556
-	.vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1167
+	.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
1168
+	.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
5571169 	.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
5581170 	.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
5591171 	.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -562,8 +1174,8 @@
5621174 	.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
5631175 	.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
5641176 	.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
565
-	.mipi_dual_en = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 20),
566
-	.mipi_dual_channel_swap = VOP_REG(RK3568_VP1_MIPI_CTRL, 0x1, 21),
1177
+	.dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20),
1178
+	.dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21),
5671179 
5681180 	.bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
5691181 	.bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
....@@ -577,6 +1189,9 @@
5771189 	.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
5781190 	.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
5791191 	.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
1192
+
1193
+	.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
1194
+	.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
5801195 };
5811196 
5821197 static const struct vop2_video_port_regs rk3568_vop_vp2_regs = {
....@@ -587,8 +1202,8 @@
5871202 	.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
5881203 	.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
5891204 	.core_dclk_div = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 4),
590
-	.dclk_div2 = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 4),
591
-	.dclk_div2_phase_lock = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 5),
1205
+	.dclk_div2 = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 4),
1206
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 5),
5921207 	.p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
5931208 	.dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
5941209 	.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
....@@ -603,7 +1218,8 @@
6031218 	.post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
6041219 	.htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
6051220 	.hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
606
-	.vtotal_pw = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
1221
+	.dsp_vtotal = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 16),
1222
+	.dsp_vs_end = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 0),
6071223 	.vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
6081224 	.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
6091225 	.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
....@@ -612,8 +1228,8 @@
6121228 	.dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
6131229 	.dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
6141230 	.dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
615
-	.mipi_dual_en = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 20),
616
-	.mipi_dual_channel_swap = VOP_REG(RK3568_VP2_MIPI_CTRL, 0x1, 21),
1231
+	.dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20),
1232
+	.dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21),
6171233 
6181234 	.bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0),
6191235 	.bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8),
....@@ -627,13 +1243,17 @@
6271243 	.bcsh_y2r_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 0),
6281244 	.bcsh_en = VOP_REG(RK3568_VP2_BCSH_COLOR_BAR, 0x1, 31),
6291245 	.dsp_lut_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 28),
1246
+
1247
+	.color_bar_mode = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 1),
1248
+	.color_bar_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 0),
6301249 };
6311250 
6321251 static const struct vop2_video_port_data rk3568_vop_video_ports[] = {
6331252 	{
6341253 	 .id = 0,
6351254 	 .soc_id = { 0x3568, 0x3566 },
636
-	 .feature = VOP_FEATURE_OUTPUT_10BIT,
1255
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE |
1256
+			VOP_FEATURE_HDR10 | VOP_FEATURE_OVERSCAN,
6371257 	 .gamma_lut_len = 1024,
6381258 	 .cubic_lut_len = 729, /* 9x9x9 */
6391259 	 .max_output = { 4096, 2304 },
....@@ -645,6 +1265,7 @@
6451265 	{
6461266 	 .id = 1,
6471267 	 .soc_id = { 0x3568, 0x3566 },
1268
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
6481269 	 .gamma_lut_len = 1024,
6491270 	 .max_output = { 2048, 1536 },
6501271 	 .pre_scan_max_dly = { 40, 40, 40, 40 },
....@@ -653,6 +1274,7 @@
6531274 	},
6541275 	{
6551276 	 .id = 2,
1277
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
6561278 	 .soc_id = { 0x3568, 0x3566 },
6571279 	 .gamma_lut_len = 1024,
6581280 	 .max_output = { 1920, 1080 },
....@@ -661,6 +1283,514 @@
6611283 	 .regs = &rk3568_vop_vp2_regs,
6621284 	},
6631285 };
1286
+
1287
+static const struct vop2_video_port_regs rk3588_vop_vp0_regs = {
1288
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
1289
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 0),
1290
+	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
1291
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 0),
1292
+	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
1293
+	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
1294
+	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
1295
+	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
1296
+	.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
1297
+	.dsp_x_mir_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 13),
1298
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
1299
+	.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
1300
+	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
1301
+	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
1302
+	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
1303
+	.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
1304
+	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
1305
+	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
1306
+	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
1307
+	.splice_en = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 16),
1308
+	.dclk_core_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 0),
1309
+	.dclk_out_div = VOP_REG(RK3568_VP0_CLK_CTRL, 0x3, 2),
1310
+	.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1311
+	.bg_dly = VOP_REG(RK3568_VP0_BG_MIX_CTRL, 0xff, 24),
1312
+	.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1313
+	.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1314
+	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1315
+	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
1316
+	.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
1317
+	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
1318
+	.dsp_vtotal = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 16),
1319
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1, 15),
1320
+	.dsp_vs_end = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff, 0),
1321
+	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
1322
+	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1323
+	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1324
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1325
+	.dual_channel_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 20),
1326
+	.dual_channel_swap = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 21),
1327
+	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
1328
+	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
1329
+	.hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
1330
+	.hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
1331
+	.sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 0),
1332
+	.sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 1),
1333
+	.sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 2),
1334
+	.sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
1335
+	.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 8),
1336
+	.sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 9),
1337
+	.sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 5),
1338
+	.hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 0),
1339
+	.hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 8),
1340
+	.hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL, 0x1, 9),
1341
+	.hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
1342
+	.hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
1343
+	.hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
1344
+	.hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
1345
+	.hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
1346
+	.hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
1347
+	.hdr2sdr_eetf_oetf_y0_offset = RK3568_HDR_EETF_OETF_Y0,
1348
+	.hdr2sdr_sat_y0_offset = RK3568_HDR_SAT_Y0,
1349
+	.sdr2hdr_eotf_oetf_y0_offset = RK3568_HDR_EOTF_OETF_Y0,
1350
+	.sdr2hdr_oetf_dx_pow1_offset = RK3568_HDR_OETF_DX_POW1,
1351
+	.sdr2hdr_oetf_xn1_offset = RK3568_HDR_OETF_XN1,
1352
+	.hdr_src_color_ctrl = VOP_REG(RK3568_HDR0_SRC_COLOR_CTRL, 0xffffffff, 0),
1353
+	.hdr_dst_color_ctrl = VOP_REG(RK3568_HDR0_DST_COLOR_CTRL, 0xffffffff, 0),
1354
+	.hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR0_SRC_ALPHA_CTRL, 0xffffffff, 0),
1355
+	.hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR0_DST_ALPHA_CTRL, 0xffffffff, 0),
1356
+
1357
+	.bcsh_brightness = VOP_REG(RK3568_VP0_BCSH_BCS, 0xff, 0),
1358
+	.bcsh_contrast = VOP_REG(RK3568_VP0_BCSH_BCS, 0x1ff, 8),
1359
+	.bcsh_sat_con = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3ff, 20),
1360
+	.bcsh_out_mode = VOP_REG(RK3568_VP0_BCSH_BCS, 0x3, 30),
1361
+	.bcsh_sin_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 0),
1362
+	.bcsh_cos_hue = VOP_REG(RK3568_VP0_BCSH_H, 0x1ff, 16),
1363
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 6),
1364
+	.bcsh_r2y_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 4),
1365
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x3, 2),
1366
+	.bcsh_y2r_en = VOP_REG(RK3568_VP0_BCSH_CTRL, 0x1, 0),
1367
+	.bcsh_en = VOP_REG(RK3568_VP0_BCSH_COLOR_BAR, 0x1, 31),
1368
+	.edpi_te_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 28),
1369
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 30),
1370
+	.edpi_wms_fs = VOP_REG(RK3568_VP0_DUAL_CHANNEL_CTRL, 0x1, 31),
1371
+
1372
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1373
+	.cubic_lut_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 0),
1374
+	.cubic_lut_update_en = VOP_REG(RK3568_VP0_3D_LUT_CTRL, 0x1, 2),
1375
+	.cubic_lut_mst = VOP_REG(RK3568_VP0_3D_LUT_MST, 0xffffffff, 0),
1376
+
1377
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 20),
1378
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 24),
1379
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 28),
1380
+
1381
+	.color_bar_mode = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 1),
1382
+	.color_bar_en = VOP_REG(RK3568_VP0_COLOR_BAR_CTRL, 0x1, 0),
1383
+};
1384
+
1385
+/*
1386
+ * VP1 can splice with VP0 to output hdisplay > 4096,
1387
+ * VP1 has a another HDR10 controller, but share the
1388
+ * same eotf curve with VP1.
1389
+ */
1390
+static const struct vop2_video_port_regs rk3588_vop_vp1_regs = {
1391
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
1392
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 1),
1393
+	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
1394
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 4),
1395
+	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
1396
+	.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
1397
+	.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
1398
+	.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
1399
+	.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
1400
+	.dsp_x_mir_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 13),
1401
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
1402
+	.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
1403
+	.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
1404
+	.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
1405
+	.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
1406
+	.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),
1407
+	.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
1408
+	.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
1409
+	.dclk_core_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 0),
1410
+	.dclk_out_div = VOP_REG(RK3568_VP1_CLK_CTRL, 0x3, 2),
1411
+	.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1412
+	.bg_dly = VOP_REG(RK3568_VP1_BG_MIX_CTRL, 0xff, 24),
1413
+	.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1414
+	.vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1415
+	.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1416
+	.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
1417
+	.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1418
+	.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0x1fff1fff, 0),
1419
+	.dsp_vtotal = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 16),
1420
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1, 15),
1421
+	.dsp_vs_end = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff, 0),
1422
+	.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
1423
+	.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1424
+	.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1425
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1426
+	.dual_channel_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 20),
1427
+	.dual_channel_swap = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 21),
1428
+	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 24),
1429
+	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
1430
+	.hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
1431
+	.hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
1432
+	.sdr2hdr_eotf_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 0),
1433
+	.sdr2hdr_r2r_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 1),
1434
+	.sdr2hdr_r2r_mode = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 2),
1435
+	.sdr2hdr_oetf_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 3),
1436
+	.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 8),
1437
+	.sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL1, 0x1, 9),
1438
+	.sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 25),
1439
+	.hdr2sdr_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 0),
1440
+	.hdr2sdr_bypass_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 8),
1441
+	.hdr2sdr_auto_gating_en = VOP_REG(RK3568_HDR2SDR_CTRL1, 0x1, 9),
1442
+	.hdr2sdr_src_min = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 0),
1443
+	.hdr2sdr_src_max = VOP_REG(RK3568_HDR2SDR_SRC_RANGE, 0x3fff, 16),
1444
+	.hdr2sdr_normfaceetf = VOP_REG(RK3568_HDR2SDR_NORMFACEETF, 0x7ff, 0),
1445
+	.hdr2sdr_dst_min = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 0),
1446
+	.hdr2sdr_dst_max = VOP_REG(RK3568_HDR2SDR_DST_RANGE, 0xffff, 16),
1447
+	.hdr2sdr_normfacgamma = VOP_REG(RK3568_HDR2SDR_NORMFACCGAMMA, 0xffff, 0),
1448
+	.hdr2sdr_eetf_oetf_y0_offset = RK3568_HDR_EETF_OETF_Y0,
1449
+	.hdr2sdr_sat_y0_offset = RK3568_HDR_SAT_Y0,
1450
+	.sdr2hdr_eotf_oetf_y0_offset = RK3568_HDR_EOTF_OETF_Y0,
1451
+	.sdr2hdr_oetf_dx_pow1_offset = RK3568_HDR_OETF_DX_POW1,
1452
+	.sdr2hdr_oetf_xn1_offset = RK3568_HDR_OETF_XN1,
1453
+	.hdr_src_color_ctrl = VOP_REG(RK3568_HDR1_SRC_COLOR_CTRL, 0xffffffff, 0),
1454
+	.hdr_dst_color_ctrl = VOP_REG(RK3568_HDR1_DST_COLOR_CTRL, 0xffffffff, 0),
1455
+	.hdr_src_alpha_ctrl = VOP_REG(RK3568_HDR1_SRC_ALPHA_CTRL, 0xffffffff, 0),
1456
+	.hdr_dst_alpha_ctrl = VOP_REG(RK3568_HDR1_DST_ALPHA_CTRL, 0xffffffff, 0),
1457
+
1458
+	.bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
1459
+	.bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
1460
+	.bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20),
1461
+	.bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30),
1462
+	.bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0),
1463
+	.bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16),
1464
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6),
1465
+	.bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4),
1466
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
1467
+	.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
1468
+	.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
1469
+	.edpi_te_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 28),
1470
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 30),
1471
+	.edpi_wms_fs = VOP_REG(RK3568_VP1_DUAL_CHANNEL_CTRL, 0x1, 31),
1472
+
1473
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1474
+	.cubic_lut_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 0),
1475
+	.cubic_lut_update_en = VOP_REG(RK3588_VP1_3D_LUT_CTRL, 0x1, 2),
1476
+	.cubic_lut_mst = VOP_REG(RK3588_VP1_3D_LUT_MST, 0xffffffff, 0),
1477
+
1478
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 21),
1479
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 25),
1480
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 29),
1481
+
1482
+	.color_bar_mode = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 1),
1483
+	.color_bar_en = VOP_REG(RK3568_VP1_COLOR_BAR_CTRL, 0x1, 0),
1484
+};
1485
+
1486
+static const struct vop2_video_port_regs rk3588_vop_vp2_regs = {
1487
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 2),
1488
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 2),
1489
+	.dsp_background = VOP_REG(RK3568_VP2_DSP_BG, 0xffffffff, 0),
1490
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 8),
1491
+	.out_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0xf, 0),
1492
+	.p2i_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 5),
1493
+	.dsp_filed_pol = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 6),
1494
+	.dsp_interlace = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 7),
1495
+	.dsp_data_swap = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1f, 8),
1496
+	.dsp_x_mir_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 13),
1497
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 15),
1498
+	.pre_dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 16),
1499
+	.dither_down_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 17),
1500
+	.dither_down_sel = VOP_REG(RK3568_VP2_DSP_CTRL, 0x3, 18),
1501
+	.dither_down_mode = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 20),
1502
+	.gamma_update_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 22),
1503
+	.dsp_lut_en = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 28),
1504
+	.standby = VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31),
1505
+	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 31),
1506
+	.dclk_core_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 0),
1507
+	.dclk_out_div = VOP_REG(RK3568_VP2_CLK_CTRL, 0x3, 2),
1508
+	.pre_scan_htiming = VOP_REG(RK3568_VP2_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1509
+	.bg_dly = VOP_REG(RK3568_VP2_BG_MIX_CTRL, 0xff, 24),
1510
+	.hpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1511
+	.vpost_st_end = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1512
+	.post_scl_factor = VOP_REG(RK3568_VP2_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1513
+	.post_scl_ctrl = VOP_REG(RK3568_VP2_POST_SCL_CTRL, 0x3, 0),
1514
+	.htotal_pw = VOP_REG(RK3568_VP2_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1515
+	.hact_st_end = VOP_REG(RK3568_VP2_DSP_HACT_ST_END, 0x1fff1fff, 0),
1516
+	.dsp_vtotal = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 16),
1517
+	.sw_dsp_vtotal_imd = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1, 15),
1518
+	.dsp_vs_end = VOP_REG(RK3568_VP2_DSP_VTOTAL_VS_END, 0x1fff, 0),
1519
+	.vact_st_end = VOP_REG(RK3568_VP2_DSP_VACT_ST_END, 0x1fff1fff, 0),
1520
+	.vact_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1521
+	.vs_st_end_f1 = VOP_REG(RK3568_VP2_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1522
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP2_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1523
+	.dual_channel_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 20),
1524
+	.dual_channel_swap = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 21),
1525
+	.bcsh_brightness = VOP_REG(RK3568_VP2_BCSH_BCS, 0xff, 0),
1526
+	.bcsh_contrast = VOP_REG(RK3568_VP2_BCSH_BCS, 0x1ff, 8),
1527
+	.bcsh_sat_con = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3ff, 20),
1528
+	.bcsh_out_mode = VOP_REG(RK3568_VP2_BCSH_BCS, 0x3, 30),
1529
+	.bcsh_sin_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 0),
1530
+	.bcsh_cos_hue = VOP_REG(RK3568_VP2_BCSH_H, 0x1ff, 16),
1531
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 6),
1532
+	.bcsh_r2y_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 4),
1533
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x3, 2),
1534
+	.bcsh_y2r_en = VOP_REG(RK3568_VP2_BCSH_CTRL, 0x1, 0),
1535
+	.bcsh_en = VOP_REG(RK3568_VP2_BCSH_COLOR_BAR, 0x1, 31),
1536
+	.edpi_te_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 28),
1537
+	.edpi_wms_hold_en = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 30),
1538
+	.edpi_wms_fs = VOP_REG(RK3568_VP2_DUAL_CHANNEL_CTRL, 0x1, 31),
1539
+
1540
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
1541
+	.cubic_lut_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 0),
1542
+	.cubic_lut_update_en = VOP_REG(RK3588_VP2_3D_LUT_CTRL, 0x1, 2),
1543
+	.cubic_lut_mst = VOP_REG(RK3588_VP2_3D_LUT_MST, 0xffffffff, 0),
1544
+
1545
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 22),
1546
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 26),
1547
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 30),
1548
+
1549
+	.color_bar_mode = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 1),
1550
+	.color_bar_en = VOP_REG(RK3568_VP2_COLOR_BAR_CTRL, 0x1, 0),
1551
+};
1552
+
1553
+static const struct vop2_video_port_regs rk3588_vop_vp3_regs = {
1554
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 3),
1555
+	.overlay_mode = VOP_REG(RK3568_OVL_CTRL, 0x1, 3),
1556
+	.port_mux = VOP_REG(RK3568_OVL_PORT_SEL, 0xf, 12),
1557
+	.dsp_background = VOP_REG(RK3588_VP3_DSP_BG, 0xffffffff, 0),
1558
+	.out_mode = VOP_REG(RK3588_VP3_DSP_CTRL, 0xf, 0),
1559
+	.p2i_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 5),
1560
+	.dsp_filed_pol = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 6),
1561
+	.dsp_interlace = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 7),
1562
+	.dsp_data_swap = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1f, 8),
1563
+	.dsp_x_mir_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 13),
1564
+	.post_dsp_out_r2y = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 15),
1565
+	.pre_dither_down_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 16),
1566
+	.dither_down_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 17),
1567
+	.dither_down_sel = VOP_REG(RK3588_VP3_DSP_CTRL, 0x3, 18),
1568
+	.dither_down_mode = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 20),
1569
+	.gamma_update_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 22),
1570
+	.dsp_lut_en = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 28),
1571
+	.standby = VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 31),
1572
+	.dclk_src_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x1, 30),
1573
+	.dclk_core_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 0),
1574
+	.dclk_out_div = VOP_REG(RK3568_VP3_CLK_CTRL, 0x3, 2),
1575
+	.pre_scan_htiming = VOP_REG(RK3588_VP3_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
1576
+	.bg_dly = VOP_REG(RK3588_VP3_BG_MIX_CTRL, 0xff, 24),
1577
+	.hpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
1578
+	.vpost_st_end = VOP_REG(RK3588_VP3_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
1579
+	.post_scl_factor = VOP_REG(RK3588_VP3_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
1580
+	.post_scl_ctrl = VOP_REG(RK3588_VP3_POST_SCL_CTRL, 0x3, 0),
1581
+	.htotal_pw = VOP_REG(RK3588_VP3_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
1582
+	.hact_st_end = VOP_REG(RK3588_VP3_DSP_HACT_ST_END, 0x1fff1fff, 0),
1583
+	.dsp_vtotal = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff, 16),
1584
+	.sw_dsp_vtotal_imd = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1, 15),
1585
+	.dsp_vs_end = VOP_REG(RK3588_VP3_DSP_VTOTAL_VS_END, 0x1fff, 0),
1586
+	.vact_st_end = VOP_REG(RK3588_VP3_DSP_VACT_ST_END, 0x1fff1fff, 0),
1587
+	.vact_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
1588
+	.vs_st_end_f1 = VOP_REG(RK3588_VP3_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
1589
+	.vpost_st_end_f1 = VOP_REG(RK3588_VP3_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
1590
+	.dual_channel_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 20),
1591
+	.dual_channel_swap = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 21),
1592
+	.bcsh_brightness = VOP_REG(RK3588_VP3_BCSH_BCS, 0xff, 0),
1593
+	.bcsh_contrast = VOP_REG(RK3588_VP3_BCSH_BCS, 0x1ff, 8),
1594
+	.bcsh_sat_con = VOP_REG(RK3588_VP3_BCSH_BCS, 0x3ff, 20),
1595
+	.bcsh_out_mode = VOP_REG(RK3588_VP3_BCSH_BCS, 0x3, 30),
1596
+	.bcsh_sin_hue = VOP_REG(RK3588_VP3_BCSH_H, 0x1ff, 0),
1597
+	.bcsh_cos_hue = VOP_REG(RK3588_VP3_BCSH_H, 0x1ff, 16),
1598
+	.bcsh_r2y_csc_mode = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x3, 6),
1599
+	.bcsh_r2y_en = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x1, 4),
1600
+	.bcsh_y2r_csc_mode = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x3, 2),
1601
+	.bcsh_y2r_en = VOP_REG(RK3588_VP3_BCSH_CTRL, 0x1, 0),
1602
+	.bcsh_en = VOP_REG(RK3588_VP3_BCSH_COLOR_BAR, 0x1, 31),
1603
+	.edpi_te_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 28),
1604
+	.edpi_wms_hold_en = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 30),
1605
+	.edpi_wms_fs = VOP_REG(RK3588_VP3_DUAL_CHANNEL_CTRL, 0x1, 31),
1606
+
1607
+	.line_flag_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 23),
1608
+	.dsp_hold_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 27),
1609
+	.almost_full_or_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 31),
1610
+
1611
+	.color_bar_mode = VOP_REG(RK3588_VP3_COLOR_BAR_CTRL, 0x1, 1),
1612
+	.color_bar_en = VOP_REG(RK3588_VP3_COLOR_BAR_CTRL, 0x1, 0),
1613
+};
1614
+
1615
+static const struct vop2_video_port_data rk3588_vop_video_ports[] = {
1616
+	{
1617
+	 .id = 0,
1618
+	 .splice_vp_id = 1,
1619
+	 .lut_dma_rid = 0xd,
1620
+	 .soc_id = { 0x3588, 0x3588 },
1621
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE |
1622
+			VOP_FEATURE_HDR10 | VOP_FEATURE_NEXT_HDR,
1623
+	 .gamma_lut_len = 1024,
1624
+	 .cubic_lut_len = 729, /* 9x9x9 */
1625
+	 .dclk_max = 600000000,
1626
+	 .max_output = { 7680, 4320 },
1627
+	 /* hdr2sdr sdr2hdr hdr2hdr sdr2sdr */
1628
+	 .pre_scan_max_dly = { 76, 65, 65, 54 },
1629
+	 .intr = &rk3568_vp0_intr,
1630
+	 .hdr_table = &rk3568_vop_hdr_table,
1631
+	 .regs = &rk3588_vop_vp0_regs,
1632
+	},
1633
+	{
1634
+	 .id = 1,
1635
+	 .lut_dma_rid = 0xe,
1636
+	 .soc_id = { 0x3588, 0x3588 },
1637
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE,
1638
+	 .gamma_lut_len = 1024,
1639
+	 .cubic_lut_len = 729, /* 9x9x9 */
1640
+	 .dclk_max = 600000000,
1641
+	 .max_output = { 4096, 2304 },
1642
+	 .pre_scan_max_dly = { 76, 65, 65, 54 },
1643
+	 .intr = &rk3568_vp1_intr,
1644
+	 /* vp1 share the same hdr curve with vp0 */
1645
+	 .hdr_table = &rk3568_vop_hdr_table,
1646
+	 .regs = &rk3588_vop_vp1_regs,
1647
+	},
1648
+	{
1649
+	 .id = 2,
1650
+	 .lut_dma_rid = 0xe,
1651
+	 .soc_id = { 0x3588, 0x3588 },
1652
+	 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_ALPHA_SCALE,
1653
+	 .gamma_lut_len = 1024,
1654
+	 .cubic_lut_len = 4913, /* 17x17x17 */
1655
+	 .dclk_max = 600000000,
1656
+	 .max_output = { 4096, 2304 },
1657
+	 .pre_scan_max_dly = { 52, 52, 52, 52 },
1658
+	 .intr = &rk3568_vp2_intr,
1659
+	 .regs = &rk3588_vop_vp2_regs,
1660
+	},
1661
+	{
1662
+	 .id = 3,
1663
+	 .soc_id = { 0x3588, 0x3588 },
1664
+	 .feature = VOP_FEATURE_ALPHA_SCALE,
1665
+	 .gamma_lut_len = 1024,
1666
+	 .dclk_max = 200000000,
1667
+	 .max_output = { 2048, 1536 },
1668
+	 .pre_scan_max_dly = { 52, 52, 52, 52 },
1669
+	 .intr = &rk3588_vp3_intr,
1670
+	 .regs = &rk3588_vop_vp3_regs,
1671
+	},
1672
+};
1673
+
1674
+/*
1675
+ * HDMI/eDP infterface pixclk and dclk are independent of each other.
1676
+ * MIPI and DP interface pixclk and dclk are the same in itself.
1677
+ */
1678
+static const struct vop2_connector_if_data rk3588_conn_if_data[] = {
1679
+	{
1680
+	 .id = VOP_OUTPUT_IF_HDMI0,
1681
+	 .clk_src_name = "hdmi_edp0_clk_src",
1682
+	 .clk_parent_name = "dclk",
1683
+	 .pixclk_name = "hdmi_edp0_pixclk",
1684
+	 .dclk_name = "hdmi_edp0_dclk",
1685
+	 .post_proc_div_shift = 2,
1686
+	 .if_div_shift = 4,
1687
+	 .if_div_yuv420_shift = 1,
1688
+	 .bus_div_shift = 2,
1689
+	 .pixel_clk_div_shift = 2,
1690
+	},
1691
+
1692
+	{
1693
+	 .id = VOP_OUTPUT_IF_HDMI1,
1694
+	 .clk_src_name = "hdmi_edp1_clk_src",
1695
+	 .clk_parent_name = "dclk",
1696
+	 .pixclk_name = "hdmi_edp1_pixclk",
1697
+	 .dclk_name = "hdmi_edp1_dclk",
1698
+	 .post_proc_div_shift = 2,
1699
+	 .if_div_shift = 4,
1700
+	 .if_div_yuv420_shift = 1,
1701
+	 .bus_div_shift = 2,
1702
+	 .pixel_clk_div_shift = 2,
1703
+	},
1704
+
1705
+	{
1706
+	 .id = VOP_OUTPUT_IF_eDP0,
1707
+	 .clk_src_name = "hdmi_edp0_clk_src",
1708
+	 .clk_parent_name = "dclk",
1709
+	 .pixclk_name = "hdmi_edp0_pixclk",
1710
+	 .dclk_name = "hdmi_edp0_dclk",
1711
+	 .post_proc_div_shift = 2,
1712
+	 .if_div_shift = 4,
1713
+	 .if_div_yuv420_shift = 1,
1714
+	 .bus_div_shift = 1,
1715
+	 .pixel_clk_div_shift = 1,
1716
+	},
1717
+
1718
+	{
1719
+	 .id = VOP_OUTPUT_IF_eDP1,
1720
+	 .clk_src_name = "hdmi_edp1_clk_src",
1721
+	 .clk_parent_name = "dclk",
1722
+	 .pixclk_name = "hdmi_edp1_pixclk",
1723
+	 .dclk_name = "hdmi_edp1_dclk",
1724
+	 .post_proc_div_shift = 2,
1725
+	 .if_div_shift = 4,
1726
+	 .if_div_yuv420_shift = 1,
1727
+	 .bus_div_shift = 1,
1728
+	 .pixel_clk_div_shift = 1,
1729
+	},
1730
+
1731
+	{
1732
+	 .id = VOP_OUTPUT_IF_DP0,
1733
+	 .clk_src_name = "dp0_pixclk",
1734
+	 .clk_parent_name = "dclk_out",
1735
+	 .pixclk_name = "dp0_pixclk",
1736
+	 .post_proc_div_shift = 2,
1737
+	 .if_div_shift = 1,
1738
+	 .if_div_yuv420_shift = 2,
1739
+	 .bus_div_shift = 1,
1740
+	 .pixel_clk_div_shift = 1,
1741
+
1742
+	},
1743
+
1744
+	{
1745
+	 .id = VOP_OUTPUT_IF_DP1,
1746
+	 .clk_src_name = "dp1_pixclk",
1747
+	 .clk_parent_name = "dclk_out",
1748
+	 .pixclk_name = "dp1_pixclk",
1749
+	 .post_proc_div_shift = 2,
1750
+	 .if_div_shift = 1,
1751
+	 .if_div_yuv420_shift = 2,
1752
+	 .bus_div_shift = 1,
1753
+	 .pixel_clk_div_shift = 1,
1754
+
1755
+	},
1756
+
1757
+	{
1758
+	 .id = VOP_OUTPUT_IF_MIPI0,
1759
+	 .clk_src_name = "mipi0_clk_src",
1760
+	 .clk_parent_name = "dclk_out",
1761
+	 .pixclk_name = "mipi0_pixclk",
1762
+	 .post_proc_div_shift = 2,
1763
+	 .if_div_shift = 1,
1764
+	 .if_div_yuv420_shift = 1,
1765
+	 .bus_div_shift = 1,
1766
+	 .pixel_clk_div_shift = 1,
1767
+	},
1768
+
1769
+	{
1770
+	 .id = VOP_OUTPUT_IF_MIPI1,
1771
+	 .clk_src_name = "mipi1_clk_src",
1772
+	 .clk_parent_name = "dclk_out",
1773
+	 .pixclk_name = "mipi1_pixclk",
1774
+	 .post_proc_div_shift = 2,
1775
+	 .if_div_shift = 1,
1776
+	 .if_div_yuv420_shift = 1,
1777
+	 .bus_div_shift = 1,
1778
+	 .pixel_clk_div_shift = 1,
1779
+	},
1780
+
1781
+	{
1782
+	 .id = VOP_OUTPUT_IF_RGB,
1783
+	 .clk_src_name = "port3_dclk_src",
1784
+	 .clk_parent_name = "dclk",
1785
+	 .pixclk_name = "rgb_pixclk",
1786
+	 .post_proc_div_shift = 2,
1787
+	 .if_div_shift = 0,
1788
+	 .if_div_yuv420_shift = 0,
1789
+	 .bus_div_shift = 0,
1790
+	 .pixel_clk_div_shift = 0,
1791
+	},
1792
+};
1793
+
6641794 
6651795 const struct vop2_layer_regs rk3568_vop_layer0_regs = {
6661796 	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 0)
....@@ -684,6 +1814,14 @@
6841814 
6851815 const struct vop2_layer_regs rk3568_vop_layer5_regs = {
6861816 	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 20)
1817
+};
1818
+
1819
+const struct vop2_layer_regs rk3568_vop_layer6_regs = {
1820
+	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 24)
1821
+};
1822
+
1823
+const struct vop2_layer_regs rk3568_vop_layer7_regs = {
1824
+	.layer_sel = VOP_REG(RK3568_OVL_LAYER_SEL, 0x7, 28)
6871825 };
6881826 
6891827 static const struct vop2_layer_data rk3568_vop_layers[] = {
....@@ -716,6 +1854,29 @@
7161854 	 .id = 5,
7171855 	 .regs = &rk3568_vop_layer5_regs,
7181856 	},
1857
+
1858
+	{
1859
+	 .id = 6,
1860
+	 .regs = &rk3568_vop_layer6_regs,
1861
+	},
1862
+
1863
+	{
1864
+	 .id = 7,
1865
+	 .regs = &rk3568_vop_layer7_regs,
1866
+	},
1867
+
1868
+};
1869
+
1870
+static const struct vop2_cluster_regs rk3528_vop_cluster0 = {
1871
+	.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
1872
+	.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
1873
+	.lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
1874
+	.scl_lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0x3, 9),
1875
+	.frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31),
1876
+	.src_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1877
+	.dst_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1878
+	.src_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1879
+	.dst_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
7191880 };
7201881 
7211882 static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
....@@ -738,6 +1899,26 @@
7381899 	.dst_alpha_ctrl = VOP_REG(RK3568_CLUSTER1_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
7391900 };
7401901 
1902
+static const struct vop2_cluster_regs rk3588_vop_cluster2 = {
1903
+	.afbc_enable = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 1),
1904
+	.enable = VOP_REG(RK3588_CLUSTER2_CTRL, 1, 0),
1905
+	.lb_mode = VOP_REG(RK3588_CLUSTER2_CTRL, 0xf, 4),
1906
+	.src_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1907
+	.dst_color_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1908
+	.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1909
+	.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER2_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
1910
+};
1911
+
1912
+static const struct vop2_cluster_regs rk3588_vop_cluster3 =  {
1913
+	.afbc_enable = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 1),
1914
+	.enable = VOP_REG(RK3588_CLUSTER3_CTRL, 1, 0),
1915
+	.lb_mode = VOP_REG(RK3588_CLUSTER3_CTRL, 0xf, 4),
1916
+	.src_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
1917
+	.dst_color_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
1918
+	.src_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
1919
+	.dst_alpha_ctrl = VOP_REG(RK3588_CLUSTER3_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
1920
+};
1921
+
7411922 static const struct vop_afbc rk3568_cluster0_afbc = {
7421923 	.format = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1f, 2),
7431924 	.rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_CTRL, 0x1, 9),
....@@ -756,6 +1937,27 @@
7561937 	.rotate_270 = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
7571938 	.xmirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
7581939 	.ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
1940
+};
1941
+
1942
+static const struct vop2_scl_regs rk3528_cluster0_win_scl = {
1943
+	.scale_yrgb_x = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1944
+	.scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1945
+	.yrgb_ver_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 14),
1946
+	.yrgb_hor_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 22),
1947
+
1948
+	.yrgb_vscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 12),/* supported from vop3 */
1949
+	.yrgb_hscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 20),/* supported from vop3 */
1950
+
1951
+	.vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 28),
1952
+	.vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 29),
1953
+	.vsd_cbcr_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 30),
1954
+	.vsd_cbcr_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 31),
1955
+
1956
+	.vsd_avg2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 18),/* supported from vop3 */
1957
+	.vsd_avg4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 19),
1958
+	.xavg_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 27),
1959
+	.xgt_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 24),
1960
+	.xgt_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 25),
7591961 };
7601962 
7611963 static const struct vop2_scl_regs rk3568_cluster0_win_scl = {
....@@ -798,6 +2000,65 @@
7982000 	.vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL1, 0x1, 29),
7992001 };
8002002 
2003
+static const struct vop_afbc rk3588_cluster2_afbc = {
2004
+	.format = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1f, 2),
2005
+	.rb_swap = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 9),
2006
+	.uv_swap = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 10),
2007
+	.auto_gating_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
2008
+	.half_block_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 7),
2009
+	.block_split_en = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_CTRL, 0x1, 8),
2010
+	.hdr_ptr = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
2011
+	.pic_size = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
2012
+	.pic_vir_width = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
2013
+	.tile_num = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
2014
+	.pic_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
2015
+	.dsp_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
2016
+	.transform_offset = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
2017
+	.rotate_90 = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
2018
+	.rotate_270 = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
2019
+	.xmirror = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
2020
+	.ymirror = VOP_REG(RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
2021
+};
2022
+
2023
+static const struct vop2_scl_regs rk3588_cluster2_win_scl = {
2024
+	.scale_yrgb_x = VOP_REG(RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
2025
+	.scale_yrgb_y = VOP_REG(RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
2026
+	.yrgb_ver_scl_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 14),
2027
+	.yrgb_hor_scl_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 12),
2028
+	.bic_coe_sel = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x3, 2),
2029
+	.vsd_yrgb_gt2 = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x1, 28),
2030
+	.vsd_yrgb_gt4 = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL1, 0x1, 29),
2031
+};
2032
+
2033
+static const struct vop_afbc rk3588_cluster3_afbc = {
2034
+	.format = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1f, 2),
2035
+	.rb_swap = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 9),
2036
+	.uv_swap = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 10),
2037
+	.auto_gating_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL, 0x1, 4),
2038
+	.half_block_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 7),
2039
+	.block_split_en = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_CTRL, 0x1, 8),
2040
+	.hdr_ptr = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR, 0xffffffff, 0),
2041
+	.pic_size = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE, 0xffffffff, 0),
2042
+	.pic_vir_width = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH, 0xffff, 0),
2043
+	.tile_num = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH, 0xffff, 16),
2044
+	.pic_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET, 0xffffffff, 0),
2045
+	.dsp_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET, 0xffffffff, 0),
2046
+	.transform_offset = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET, 0xffffffff, 0),
2047
+	.rotate_90 = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 0),
2048
+	.rotate_270 = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 1),
2049
+	.xmirror = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 2),
2050
+	.ymirror = VOP_REG(RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
2051
+};
2052
+
2053
+static const struct vop2_scl_regs rk3588_cluster3_win_scl = {
2054
+	.scale_yrgb_x = VOP_REG(RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
2055
+	.scale_yrgb_y = VOP_REG(RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
2056
+	.yrgb_ver_scl_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 14),
2057
+	.yrgb_hor_scl_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 12),
2058
+	.bic_coe_sel = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x3, 2),
2059
+	.vsd_yrgb_gt2 = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x1, 28),
2060
+	.vsd_yrgb_gt4 = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL1, 0x1, 29),
2061
+};
8012062 
8022063 static const struct vop2_scl_regs rk3568_esmart_win_scl = {
8032064 	.scale_yrgb_x = VOP_REG(RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB, 0xffff, 0x0),
....@@ -817,6 +2078,9 @@
8172078 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 9),
8182079 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 10),
8192080 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 11),
2081
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 20),/* supported from vop3 */
2082
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 21),
2083
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x3, 22),
8202084 };
8212085 
8222086 static const struct vop2_scl_regs rk3568_area1_scl = {
....@@ -837,6 +2101,9 @@
8372101 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 9),
8382102 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 10),
8392103 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 11),
2104
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 20),/* supported from vop3 */
2105
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 21),
2106
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x3, 22),
8402107 };
8412108 
8422109 static const struct vop2_scl_regs rk3568_area2_scl = {
....@@ -857,6 +2124,9 @@
8572124 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 9),
8582125 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 10),
8592126 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 11),
2127
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 20),/* supported from vop3 */
2128
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 21),
2129
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x3, 22),
8602130 };
8612131 
8622132 static const struct vop2_scl_regs rk3568_area3_scl = {
....@@ -877,6 +2147,9 @@
8772147 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 9),
8782148 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 10),
8792149 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 11),
2150
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 20),/* supported from vop3 */
2151
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 21),
2152
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x3, 22),
8802153 };
8812154 
8822155 static const struct vop2_win_regs rk3568_area1_data = {
....@@ -890,7 +2163,6 @@
8902163 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION1_DSP_ST, 0x1fff1fff, 0),
8912164 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION1_YRGB_MST, 0xffffffff, 0),
8922165 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION1_CBR_MST, 0xffffffff, 0),
893
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 17),
8942166 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 0),
8952167 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION1_VIR, 0xffff, 16),
8962168 };
....@@ -906,7 +2178,6 @@
9062178 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION2_DSP_ST, 0x1fff1fff, 0),
9072179 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION2_YRGB_MST, 0xffffffff, 0),
9082180 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION2_CBR_MST, 0xffffffff, 0),
909
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 17),
9102181 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 0),
9112182 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION2_VIR, 0xffff, 16),
9122183 };
....@@ -922,7 +2193,6 @@
9222193 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION3_DSP_ST, 0x1fff1fff, 0),
9232194 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION3_YRGB_MST, 0xffffffff, 0),
9242195 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION3_CBR_MST, 0xffffffff, 0),
925
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 17),
9262196 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 0),
9272197 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION3_VIR, 0xffff, 16),
9282198 };
....@@ -933,13 +2203,15 @@
9332203 	&rk3568_area3_data
9342204 };
9352205 
936
-static const struct vop2_win_regs rk3568_cluster0_win_data = {
937
-	.scl = &rk3568_cluster0_win_scl,
2206
+static const struct vop2_win_regs rk3528_cluster0_win_data = {
2207
+	.scl = &rk3528_cluster0_win_scl,
9382208 	.afbc = &rk3568_cluster0_afbc,
939
-	.cluster = &rk3568_vop_cluster0,
2209
+	.cluster = &rk3528_vop_cluster0,
9402210 	.enable = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0),
941
-	.format = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1f, 1),
2211
+	.format = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3f, 1),
2212
+	.tile_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 7),
9422213 	.rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 14),
2214
+	.uv_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 17),
9432215 	.dither_up = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 18),
9442216 	.act_info = VOP_REG(RK3568_CLUSTER0_WIN0_ACT_INFO, 0x1fff1fff, 0),
9452217 	.dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x0fff0fff, 0),
....@@ -951,7 +2223,32 @@
9512223 	.uv_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 16),
9522224 	.y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
9532225 	.r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
2226
+	.csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x7, 10),
2227
+	.axi_yrgb_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 0),
2228
+	.axi_uv_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 5),
2229
+};
2230
+
2231
+static const struct vop2_win_regs rk3568_cluster0_win_data = {
2232
+	.scl = &rk3568_cluster0_win_scl,
2233
+	.afbc = &rk3568_cluster0_afbc,
2234
+	.cluster = &rk3568_vop_cluster0,
2235
+	.enable = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0),
2236
+	.format = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1f, 1),
2237
+	.rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 14),
2238
+	.dither_up = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 18),
2239
+	.act_info = VOP_REG(RK3568_CLUSTER0_WIN0_ACT_INFO, 0x1fff1fff, 0),
2240
+	.dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x1fff1fff, 0),
2241
+	.dsp_st = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_ST, 0x1fff1fff, 0),
2242
+	.yrgb_mst = VOP_REG(RK3568_CLUSTER0_WIN0_YRGB_MST, 0xffffffff, 0),
2243
+	.uv_mst = VOP_REG(RK3568_CLUSTER0_WIN0_CBR_MST, 0xffffffff, 0),
2244
+	.yrgb_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 0),
2245
+	.uv_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 16),
2246
+	.y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
2247
+	.r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
9542248 	.csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3, 10),
2249
+	.axi_yrgb_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 0),
2250
+	.axi_uv_id = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL2, 0x1f, 5),
2251
+	.axi_id = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 13),
9552252 };
9562253 
9572254 static const struct vop2_win_regs rk3568_cluster1_win_data = {
....@@ -963,39 +2260,402 @@
9632260 	.rb_swap = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 14),
9642261 	.dither_up = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 18),
9652262 	.act_info = VOP_REG(RK3568_CLUSTER1_WIN0_ACT_INFO, 0x1fff1fff, 0),
966
-	.dsp_info = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_INFO, 0x0fff0fff, 0),
2263
+	.dsp_info = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_INFO, 0x1fff1fff, 0),
9672264 	.dsp_st = VOP_REG(RK3568_CLUSTER1_WIN0_DSP_ST, 0x1fff1fff, 0),
9682265 	.yrgb_mst = VOP_REG(RK3568_CLUSTER1_WIN0_YRGB_MST, 0xffffffff, 0),
9692266 	.uv_mst = VOP_REG(RK3568_CLUSTER1_WIN0_CBR_MST, 0xffffffff, 0),
970
-	.yuv_clip = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 19),
9712267 	.yrgb_vir = VOP_REG(RK3568_CLUSTER1_WIN0_VIR, 0xffff, 0),
9722268 	.uv_vir = VOP_REG(RK3568_CLUSTER1_WIN0_VIR, 0xffff, 16),
9732269 	.y2r_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 8),
9742270 	.r2y_en = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 9),
9752271 	.csc_mode = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x3, 10),
2272
+	.axi_yrgb_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 0),
2273
+	.axi_uv_id = VOP_REG(RK3568_CLUSTER1_WIN0_CTRL2, 0x1f, 5),
2274
+	.axi_id = VOP_REG(RK3568_CLUSTER1_CTRL, 0x1, 13),
2275
+};
2276
+
2277
+static const struct vop2_win_regs rk3588_cluster2_win_data = {
2278
+	.scl = &rk3588_cluster2_win_scl,
2279
+	.afbc = &rk3588_cluster2_afbc,
2280
+	.cluster = &rk3588_vop_cluster2,
2281
+	.enable = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0),
2282
+	.format = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1f, 1),
2283
+	.rb_swap = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 14),
2284
+	.act_info = VOP_REG(RK3588_CLUSTER2_WIN0_ACT_INFO, 0x1fff1fff, 0),
2285
+	.dsp_info = VOP_REG(RK3588_CLUSTER2_WIN0_DSP_INFO, 0x1fff1fff, 0),
2286
+	.dsp_st = VOP_REG(RK3588_CLUSTER2_WIN0_DSP_ST, 0x1fff1fff, 0),
2287
+	.yrgb_mst = VOP_REG(RK3588_CLUSTER2_WIN0_YRGB_MST, 0xffffffff, 0),
2288
+	.uv_mst = VOP_REG(RK3588_CLUSTER2_WIN0_CBR_MST, 0xffffffff, 0),
2289
+	.yrgb_vir = VOP_REG(RK3588_CLUSTER2_WIN0_VIR, 0xffff, 0),
2290
+	.uv_vir = VOP_REG(RK3588_CLUSTER2_WIN0_VIR, 0xffff, 16),
2291
+	.y2r_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 8),
2292
+	.r2y_en = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 9),
2293
+	.csc_mode = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x3, 10),
2294
+	.axi_yrgb_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 0),
2295
+	.axi_uv_id = VOP_REG(RK3588_CLUSTER2_WIN0_CTRL2, 0x1f, 5),
2296
+	.axi_id = VOP_REG(RK3588_CLUSTER2_CTRL, 0x1, 13),
2297
+};
2298
+
2299
+static const struct vop2_win_regs rk3588_cluster3_win_data = {
2300
+	.scl = &rk3588_cluster3_win_scl,
2301
+	.afbc = &rk3588_cluster3_afbc,
2302
+	.cluster = &rk3588_vop_cluster3,
2303
+	.enable = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0),
2304
+	.format = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1f, 1),
2305
+	.rb_swap = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 14),
2306
+	.act_info = VOP_REG(RK3588_CLUSTER3_WIN0_ACT_INFO, 0x1fff1fff, 0),
2307
+	.dsp_info = VOP_REG(RK3588_CLUSTER3_WIN0_DSP_INFO, 0x1fff1fff, 0),
2308
+	.dsp_st = VOP_REG(RK3588_CLUSTER3_WIN0_DSP_ST, 0x1fff1fff, 0),
2309
+	.yrgb_mst = VOP_REG(RK3588_CLUSTER3_WIN0_YRGB_MST, 0xffffffff, 0),
2310
+	.uv_mst = VOP_REG(RK3588_CLUSTER3_WIN0_CBR_MST, 0xffffffff, 0),
2311
+	.yrgb_vir = VOP_REG(RK3588_CLUSTER3_WIN0_VIR, 0xffff, 0),
2312
+	.uv_vir = VOP_REG(RK3588_CLUSTER3_WIN0_VIR, 0xffff, 16),
2313
+	.y2r_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 8),
2314
+	.r2y_en = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 9),
2315
+	.csc_mode = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x3, 10),
2316
+	.axi_yrgb_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 0),
2317
+	.axi_uv_id = VOP_REG(RK3588_CLUSTER3_WIN0_CTRL2, 0x1f, 5),
2318
+	.axi_id = VOP_REG(RK3588_CLUSTER3_CTRL, 0x1, 13),
9762319 };
9772320 
9782321 static const struct vop2_win_regs rk3568_esmart_win_data = {
9792322 	.scl = &rk3568_esmart_win_scl,
2323
+	.axi_yrgb_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 4),
2324
+	.axi_uv_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 12),
2325
+	.axi_id = VOP_REG(RK3568_ESMART0_AXI_CTRL, 0x1, 1),
9802326 	.enable = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0),
9812327 	.format = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1f, 1),
9822328 	.dither_up = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 12),
9832329 	.rb_swap = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 14),
9842330 	.uv_swap = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 16),
9852331 	.act_info = VOP_REG(RK3568_ESMART0_REGION0_ACT_INFO, 0x1fff1fff, 0),
986
-	.dsp_info = VOP_REG(RK3568_ESMART0_REGION0_DSP_INFO, 0x0fff0fff, 0),
2332
+	.dsp_info = VOP_REG(RK3568_ESMART0_REGION0_DSP_INFO, 0x1fff1fff, 0),
9872333 	.dsp_st = VOP_REG(RK3568_ESMART0_REGION0_DSP_ST, 0x1fff1fff, 0),
9882334 	.yrgb_mst = VOP_REG(RK3568_ESMART0_REGION0_YRGB_MST, 0xffffffff, 0),
9892335 	.uv_mst = VOP_REG(RK3568_ESMART0_REGION0_CBR_MST, 0xffffffff, 0),
990
-	.yuv_clip = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 17),
9912336 	.yrgb_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 0),
9922337 	.uv_vir = VOP_REG(RK3568_ESMART0_REGION0_VIR, 0xffff, 16),
9932338 	.y2r_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 0),
9942339 	.r2y_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 1),
9952340 	.csc_mode = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 2),
2341
+	.csc_13bit_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 16),
9962342 	.ymirror = VOP_REG(RK3568_ESMART0_CTRL1, 0x1, 31),
9972343 	.color_key = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x3fffffff, 0),
9982344 	.color_key_en = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x1, 31),
2345
+	.scale_engine_num = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 12),/* supported from vop3 */
2346
+};
2347
+
2348
+/*
2349
+ * RK3528 VOP with 1 Cluster win and 4 Esmart win.
2350
+ * Every Esmart win support 4 multi-region.
2351
+ * VP0 can use Cluster win and Esmart0/1/2
2352
+ * VP1 can use Esmart 2/3
2353
+ *
2354
+ * Scale filter mode:
2355
+ *
2356
+ * * Cluster:
2357
+ * * Support prescale down:
2358
+ * * H/V: gt2/avg2 or gt4/avg4
2359
+ * * After prescale down:
2360
+ *    * nearest-neighbor/bilinear/bicubic for scale up
2361
+ *    * nearest-neighbor/bilinear for scale down
2362
+ *
2363
+ * * Esmart:
2364
+ * * Support prescale down:
2365
+ * * H: gt2/avg2 or gt4/avg4
2366
+ * * V: gt2 or gt4
2367
+ * * After prescale down:
2368
+ *    * nearest-neighbor/bilinear/bicubic for scale up
2369
+ *    * nearest-neighbor/bilinear/average for scale down
2370
+ */
2371
+static const struct vop2_win_data rk3528_vop_win_data[] = {
2372
+	{
2373
+	  .name = "Esmart0-win0",
2374
+	  .phys_id = ROCKCHIP_VOP2_ESMART0,
2375
+	  .formats = formats_for_esmart,
2376
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2377
+	  .format_modifiers = format_modifiers,
2378
+	  .base = 0x0,
2379
+	  .layer_sel_id = { 1, 0xff, 0xff, 0xff },
2380
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2381
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2382
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2383
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2384
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2385
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2386
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
2387
+	  .regs = &rk3568_esmart_win_data,
2388
+	  .area = rk3568_area_data,
2389
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2390
+	  .type = DRM_PLANE_TYPE_PRIMARY,
2391
+	  .axi_id = 0,
2392
+	  .axi_yrgb_id = 0x06,
2393
+	  .axi_uv_id = 0x07,
2394
+	  .possible_crtcs = 0x1,/* vp0 only */
2395
+	  .max_upscale_factor = 8,
2396
+	  .max_downscale_factor = 8,
2397
+	  .dly = { 27, 45, 48 },
2398
+	  .feature = WIN_FEATURE_MULTI_AREA | WIN_FEATURE_Y2R_13BIT_DEPTH,
2399
+	},
2400
+
2401
+	{
2402
+	  .name = "Esmart1-win0",
2403
+	  .phys_id = ROCKCHIP_VOP2_ESMART1,
2404
+	  .formats = formats_for_esmart,
2405
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2406
+	  .format_modifiers = format_modifiers,
2407
+	  .base = 0x200,
2408
+	  .layer_sel_id = { 2, 0xff, 0xff, 0xff },
2409
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2410
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2411
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2412
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2413
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2414
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2415
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
2416
+	  .regs = &rk3568_esmart_win_data,
2417
+	  .area = rk3568_area_data,
2418
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2419
+	  .type = DRM_PLANE_TYPE_OVERLAY,
2420
+	  .axi_id = 0,
2421
+	  .axi_yrgb_id = 0x08,
2422
+	  .axi_uv_id = 0x09,
2423
+	  .possible_crtcs = 0x1,/* vp0 only */
2424
+	  .max_upscale_factor = 8,
2425
+	  .max_downscale_factor = 8,
2426
+	  .dly = { 27, 45, 48 },
2427
+	  .feature = WIN_FEATURE_MULTI_AREA,
2428
+	},
2429
+
2430
+	{
2431
+	  .name = "Esmart2-win0",
2432
+	  .phys_id = ROCKCHIP_VOP2_ESMART2,
2433
+	  .base = 0x400,
2434
+	  .formats = formats_for_esmart,
2435
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2436
+	  .format_modifiers = format_modifiers,
2437
+	  .layer_sel_id = { 3, 0, 0xff, 0xff },
2438
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2439
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2440
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2441
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2442
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2443
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2444
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
2445
+	  .regs = &rk3568_esmart_win_data,
2446
+	  .area = rk3568_area_data,
2447
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2448
+	  .type = DRM_PLANE_TYPE_CURSOR,
2449
+	  .axi_id = 0,
2450
+	  .axi_yrgb_id = 0x0a,
2451
+	  .axi_uv_id = 0x0b,
2452
+	  .possible_crtcs = 0x3,/* vp0 or vp1 */
2453
+	  .max_upscale_factor = 8,
2454
+	  .max_downscale_factor = 8,
2455
+	  .dly = { 27, 45, 48 },
2456
+	  .feature = WIN_FEATURE_MULTI_AREA,
2457
+	},
2458
+
2459
+	{
2460
+	  .name = "Esmart3-win0",
2461
+	  .phys_id = ROCKCHIP_VOP2_ESMART3,
2462
+	  .formats = formats_for_esmart,
2463
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2464
+	  .format_modifiers = format_modifiers,
2465
+	  .base = 0x600,
2466
+	  .layer_sel_id = { 0xff, 1, 0xff, 0xff },
2467
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2468
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2469
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2470
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2471
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2472
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2473
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
2474
+	  .regs = &rk3568_esmart_win_data,
2475
+	  .area = rk3568_area_data,
2476
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2477
+	  .type = DRM_PLANE_TYPE_PRIMARY,
2478
+	  .axi_id = 0,
2479
+	  .axi_yrgb_id = 0x0c,
2480
+	  .axi_uv_id = 0x0d,
2481
+	  .possible_crtcs = 0x2,/* vp1 only */
2482
+	  .max_upscale_factor = 8,
2483
+	  .max_downscale_factor = 8,
2484
+	  .dly = { 27, 45, 48 },
2485
+	  .feature = WIN_FEATURE_MULTI_AREA,
2486
+	},
2487
+
2488
+	{
2489
+	  .name = "Cluster0-win0",
2490
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
2491
+	  .base = 0x00,
2492
+	  .formats = formats_for_vop3_cluster,
2493
+	  .nformats = ARRAY_SIZE(formats_for_vop3_cluster),
2494
+	  .format_modifiers = format_modifiers_afbc_tiled,
2495
+	  .layer_sel_id = { 0, 0xff, 0xff, 0xff },
2496
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
2497
+			   DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2498
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2499
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2500
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2501
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2502
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2503
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2504
+	  .regs = &rk3528_cluster0_win_data,
2505
+	  .axi_yrgb_id = 0x02,
2506
+	  .axi_uv_id = 0x03,
2507
+	  .possible_crtcs = 0x1,/* vp0 only */
2508
+	  .max_upscale_factor = 8,
2509
+	  .max_downscale_factor = 8,
2510
+	  .dly = { 27, 27, 21 },
2511
+	  .type = DRM_PLANE_TYPE_OVERLAY,
2512
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_Y2R_13BIT_DEPTH,
2513
+	},
2514
+
2515
+	{
2516
+	  .name = "Cluster0-win1",
2517
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
2518
+	  .base = 0x80,
2519
+	  .layer_sel_id = { 0, 0xff, 0xff, 0xff },
2520
+	  .formats = formats_for_cluster,
2521
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
2522
+	  .format_modifiers = format_modifiers_afbc_tiled,
2523
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
2524
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2525
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2526
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2527
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2528
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2529
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
2530
+	  .regs = &rk3528_cluster0_win_data,
2531
+	  .axi_yrgb_id = 0x04,
2532
+	  .axi_uv_id = 0x05,
2533
+	  .possible_crtcs = 0x1,/* vp0 only */
2534
+	  .max_upscale_factor = 8,
2535
+	  .max_downscale_factor = 8,
2536
+	  .type = DRM_PLANE_TYPE_OVERLAY,
2537
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
2538
+	},
2539
+};
2540
+
2541
+/*
2542
+ * RK3562 VOP with 4 Esmart win.
2543
+ * Every Esmart win support 4 multi-region and each Esmart win can by used by VP0 or VP1
2544
+ *
2545
+ * Scale filter mode:
2546
+ *
2547
+ * * Esmart:
2548
+ * * Support prescale down:
2549
+ * * H: gt2/avg2 or gt4/avg4
2550
+ * * V: gt2 or gt4
2551
+ * * After prescale down:
2552
+ *	* nearest-neighbor/bilinear/bicubic for scale up
2553
+ *	* nearest-neighbor/bilinear/average for scale down
2554
+ */
2555
+static const struct vop2_win_data rk3562_vop_win_data[] = {
2556
+	{
2557
+	  .name = "Esmart0-win0",
2558
+	  .phys_id = ROCKCHIP_VOP2_ESMART0,
2559
+	  .formats = formats_for_esmart,
2560
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2561
+	  .format_modifiers = format_modifiers,
2562
+	  .base = 0x0,
2563
+	  .layer_sel_id = { 0, 0, 0xff, 0xff },
2564
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2565
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2566
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2567
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2568
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2569
+	  .regs = &rk3568_esmart_win_data,
2570
+	  .area = rk3568_area_data,
2571
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2572
+	  .type = DRM_PLANE_TYPE_PRIMARY,
2573
+	  .axi_id = 0,
2574
+	  .axi_yrgb_id = 0x02,
2575
+	  .axi_uv_id = 0x03,
2576
+	  .max_upscale_factor = 8,
2577
+	  .max_downscale_factor = 8,
2578
+	  .dly = { 27, 45, 48 },
2579
+	  .feature = WIN_FEATURE_MULTI_AREA,
2580
+	},
2581
+
2582
+	{
2583
+	  .name = "Esmart1-win0",
2584
+	  .phys_id = ROCKCHIP_VOP2_ESMART1,
2585
+	  .formats = formats_for_esmart,
2586
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2587
+	  .format_modifiers = format_modifiers,
2588
+	  .base = 0x200,
2589
+	  .layer_sel_id = { 1, 1, 0xff, 0xff },
2590
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2591
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2592
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2593
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2594
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2595
+	  .regs = &rk3568_esmart_win_data,
2596
+	  .area = rk3568_area_data,
2597
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2598
+	  .type = DRM_PLANE_TYPE_OVERLAY,
2599
+	  .axi_id = 0,
2600
+	  .axi_yrgb_id = 0x04,
2601
+	  .axi_uv_id = 0x05,
2602
+	  .max_upscale_factor = 8,
2603
+	  .max_downscale_factor = 8,
2604
+	  .dly = { 27, 45, 48 },
2605
+	  .feature = WIN_FEATURE_MULTI_AREA,
2606
+	},
2607
+
2608
+	{
2609
+	  .name = "Esmart2-win0",
2610
+	  .phys_id = ROCKCHIP_VOP2_ESMART2,
2611
+	  .base = 0x400,
2612
+	  .formats = formats_for_esmart,
2613
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2614
+	  .format_modifiers = format_modifiers,
2615
+	  .layer_sel_id = { 2, 2, 0xff, 0xff },
2616
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2617
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2618
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2619
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2620
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2621
+	  .regs = &rk3568_esmart_win_data,
2622
+	  .area = rk3568_area_data,
2623
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2624
+	  .type = DRM_PLANE_TYPE_PRIMARY,
2625
+	  .axi_id = 0,
2626
+	  .axi_yrgb_id = 0x06,
2627
+	  .axi_uv_id = 0x07,
2628
+	  .max_upscale_factor = 8,
2629
+	  .max_downscale_factor = 8,
2630
+	  .dly = { 27, 45, 48 },
2631
+	  .feature = WIN_FEATURE_MULTI_AREA,
2632
+	},
2633
+
2634
+	{
2635
+	  .name = "Esmart3-win0",
2636
+	  .phys_id = ROCKCHIP_VOP2_ESMART3,
2637
+	  .formats = formats_for_esmart,
2638
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
2639
+	  .format_modifiers = format_modifiers,
2640
+	  .base = 0x600,
2641
+	  .layer_sel_id = { 3, 3, 0xff, 0xff },
2642
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
2643
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
2644
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2645
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
2646
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
2647
+	  .regs = &rk3568_esmart_win_data,
2648
+	  .area = rk3568_area_data,
2649
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
2650
+	  .type = DRM_PLANE_TYPE_OVERLAY,
2651
+	  .axi_id = 0,
2652
+	  .axi_yrgb_id = 0x08,
2653
+	  .axi_uv_id = 0x0d,
2654
+	  .max_upscale_factor = 8,
2655
+	  .max_downscale_factor = 8,
2656
+	  .dly = { 27, 45, 48 },
2657
+	  .feature = WIN_FEATURE_MULTI_AREA,
2658
+	},
9992659 };
10002660 
10012661 /*
....@@ -1114,7 +2774,7 @@
11142774 	  .base = 0x00,
11152775 	  .formats = formats_for_cluster,
11162776 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1117
-	  .format_modifiers = format_modifiers_afbc,
2777
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
11182778 	  .layer_sel_id = { 0, 0, 0, 0xff },
11192779 	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
11202780 				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
....@@ -1137,7 +2797,7 @@
11372797 	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
11382798 	  .formats = formats_for_cluster,
11392799 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1140
-	  .format_modifiers = format_modifiers_afbc,
2800
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
11412801 	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
11422802 	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
11432803 	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
....@@ -1156,7 +2816,7 @@
11562816 	  .base = 0x00,
11572817 	  .formats = formats_for_cluster,
11582818 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1159
-	  .format_modifiers = format_modifiers_afbc,
2819
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
11602820 	  .layer_sel_id = { 1, 1, 1, 0xff },
11612821 	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
11622822 				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
....@@ -1178,7 +2838,7 @@
11782838 	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
11792839 	  .formats = formats_for_cluster,
11802840 	  .nformats = ARRAY_SIZE(formats_for_cluster),
1181
-	  .format_modifiers = format_modifiers_afbc,
2841
+	  .format_modifiers = format_modifiers_afbc_no_linear_mode,
11822842 	  .base = 0x80,
11832843 	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
11842844 	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
....@@ -1193,7 +2853,619 @@
11932853 	},
11942854 };
11952855 
1196
-static const struct vop_grf_ctrl rk3568_grf_ctrl = {
2856
+const struct vop2_power_domain_regs rk3588_cluster0_pd_regs = {
2857
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 0),
2858
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 8),
2859
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 9),
2860
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 9),
2861
+};
2862
+
2863
+const struct vop2_power_domain_regs rk3588_cluster1_pd_regs = {
2864
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 1),
2865
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 9),
2866
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 10),
2867
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 10),
2868
+};
2869
+
2870
+const struct vop2_power_domain_regs rk3588_cluster2_pd_regs = {
2871
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 2),
2872
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 10),
2873
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 11),
2874
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 11),
2875
+};
2876
+
2877
+const struct vop2_power_domain_regs rk3588_cluster3_pd_regs = {
2878
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 3),
2879
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 11),
2880
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 12),
2881
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 12),
2882
+};
2883
+
2884
+const struct vop2_power_domain_regs rk3588_esmart_pd_regs = {
2885
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 7),
2886
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 15),
2887
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 15),
2888
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 15),
2889
+};
2890
+
2891
+const struct vop2_power_domain_regs rk3588_dsc_8k_pd_regs = {
2892
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 5),
2893
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 13),
2894
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 13),
2895
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 13),
2896
+};
2897
+
2898
+const struct vop2_power_domain_regs rk3588_dsc_4k_pd_regs = {
2899
+	.pd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 6),
2900
+	.status = VOP_REG(RK3568_SYS_STATUS0, 0x1, 14),
2901
+	.pmu_status = VOP_REG(RK3588_PMU_BISR_STATUS5, 0x1, 14),
2902
+	.bisr_en_status = VOP_REG(RK3588_PMU_BISR_CON3, 0x1, 14),
2903
+};
2904
+
2905
+/*
2906
+ * There are 7 internal power domains on rk3588 vop,
2907
+ * Cluster0/1/2/3 each have on pd, and PD_CLUSTER0 as parent,
2908
+ * that means PD_CLUSTER0 should turn on first before
2909
+ * PD_CLUSTER1/2/3 turn on.
2910
+ *
2911
+ * Esmart1/2/3 share one pd PD_ESMART, and Esmart0 has no PD
2912
+ * DSC_8K/DSC_4K each have on pd.
2913
+ */
2914
+static const struct vop2_power_domain_data rk3588_vop_pd_data[] = {
2915
+	{
2916
+	  .id = VOP2_PD_CLUSTER0,
2917
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER0),
2918
+	  .regs = &rk3588_cluster0_pd_regs,
2919
+	},
2920
+
2921
+	{
2922
+	  .id = VOP2_PD_CLUSTER1,
2923
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER1),
2924
+	  .parent_id = VOP2_PD_CLUSTER0,
2925
+	  .regs = &rk3588_cluster1_pd_regs,
2926
+	},
2927
+
2928
+	{
2929
+	  .id = VOP2_PD_CLUSTER2,
2930
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER2),
2931
+	  .parent_id = VOP2_PD_CLUSTER0,
2932
+	  .regs = &rk3588_cluster2_pd_regs,
2933
+	},
2934
+
2935
+	{
2936
+	  .id = VOP2_PD_CLUSTER3,
2937
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER3),
2938
+	  .parent_id = VOP2_PD_CLUSTER0,
2939
+	  .regs = &rk3588_cluster3_pd_regs,
2940
+	},
2941
+
2942
+	{
2943
+	  .id = VOP2_PD_ESMART,
2944
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_ESMART1) |
2945
+			    BIT(ROCKCHIP_VOP2_ESMART2) |
2946
+			    BIT(ROCKCHIP_VOP2_ESMART3),
2947
+	  .regs = &rk3588_esmart_pd_regs,
2948
+	},
2949
+
2950
+	{
2951
+	  .id = VOP2_PD_DSC_8K,
2952
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_8K),
2953
+	  .regs = &rk3588_dsc_8k_pd_regs,
2954
+	},
2955
+
2956
+	{
2957
+	  .id = VOP2_PD_DSC_4K,
2958
+	  .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_4K),
2959
+	  .regs = &rk3588_dsc_4k_pd_regs,
2960
+	},
2961
+};
2962
+
2963
+const struct vop2_power_domain_regs rk3588_mem_pg_vp0_regs = {
2964
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON1, 0x1, 15),
2965
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 19),
2966
+};
2967
+
2968
+const struct vop2_power_domain_regs rk3588_mem_pg_vp1_regs = {
2969
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 0),
2970
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 20),
2971
+};
2972
+
2973
+const struct vop2_power_domain_regs rk3588_mem_pg_vp2_regs = {
2974
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 1),
2975
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 21),
2976
+};
2977
+
2978
+const struct vop2_power_domain_regs rk3588_mem_pg_vp3_regs = {
2979
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 2),
2980
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 22),
2981
+};
2982
+
2983
+const struct vop2_power_domain_regs rk3588_mem_pg_db0_regs = {
2984
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 3),
2985
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 23),
2986
+};
2987
+
2988
+const struct vop2_power_domain_regs rk3588_mem_pg_db1_regs = {
2989
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 4),
2990
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 24),
2991
+};
2992
+
2993
+const struct vop2_power_domain_regs rk3588_mem_pg_db2_regs = {
2994
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 5),
2995
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 25),
2996
+};
2997
+
2998
+const struct vop2_power_domain_regs rk3588_mem_pg_wb_regs = {
2999
+	.pd = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_CON2, 0x1, 6),
3000
+	.status = VOP_REG(RK3588_PMU_SUBMEM_PWR_GATE_STATUS, 0x1, 26),
3001
+};
3002
+
3003
+/*
3004
+ * All power gates will power on when PD_VOP is turn on.
3005
+ * Corresponding mem_pwr_ack_bypass bit should be enabled
3006
+ * if power gate powe down before PD_VOP.
3007
+ * power gates take effect immediately, this means there
3008
+ * is no synchronization between vop frame scanout, so
3009
+ * we can only enable a power gate before we enable
3010
+ * a module, and turn off power gate after the module
3011
+ * is actually disabled.
3012
+ */
3013
+static const struct vop2_power_domain_data rk3588_vop_mem_pg_data[] = {
3014
+	{
3015
+	  .id = VOP2_MEM_PG_VP0,
3016
+	  .regs = &rk3588_mem_pg_vp0_regs,
3017
+	},
3018
+
3019
+	{
3020
+	  .id = VOP2_MEM_PG_VP1,
3021
+	  .regs = &rk3588_mem_pg_vp1_regs,
3022
+	},
3023
+
3024
+	{
3025
+	  .id = VOP2_MEM_PG_VP2,
3026
+	  .regs = &rk3588_mem_pg_vp2_regs,
3027
+	},
3028
+
3029
+	{
3030
+	  .id = VOP2_MEM_PG_VP3,
3031
+	  .regs = &rk3588_mem_pg_vp3_regs,
3032
+	},
3033
+
3034
+	{
3035
+	  .id = VOP2_MEM_PG_DB0,
3036
+	  .regs = &rk3588_mem_pg_db0_regs,
3037
+	},
3038
+
3039
+	{
3040
+	  .id = VOP2_MEM_PG_DB1,
3041
+	  .regs = &rk3588_mem_pg_db1_regs,
3042
+	},
3043
+
3044
+	{
3045
+	  .id = VOP2_MEM_PG_DB2,
3046
+	  .regs = &rk3588_mem_pg_db2_regs,
3047
+	},
3048
+
3049
+	{
3050
+	  .id = VOP2_MEM_PG_WB,
3051
+	  .regs = &rk3588_mem_pg_wb_regs,
3052
+	},
3053
+};
3054
+
3055
+/*
3056
+ * rk3588 vop with 4 cluster, 4 esmart win.
3057
+ * Every cluster can work as 4K win or split into two win.
3058
+ * All win in cluster support AFBCD.
3059
+ *
3060
+ * Every esmart win and smart win support 4 Multi-region.
3061
+ *
3062
+ * Scale filter mode:
3063
+ *
3064
+ * * Cluster:  bicubic for horizontal scale up, others use bilinear
3065
+ * * ESmart:
3066
+ *    * nearest-neighbor/bilinear/bicubic for scale up
3067
+ *    * nearest-neighbor/bilinear/average for scale down
3068
+ *
3069
+ * AXI Read ID assignment:
3070
+ * Two AXI bus:
3071
+ * AXI0 is a read/write bus with a higher performance.
3072
+ * AXI1 is a read only bus.
3073
+ *
3074
+ * Every window on a AXI bus must assigned two unique
3075
+ * read id(yrgb_id/uv_id, valid id are 0x1~0xe).
3076
+ *
3077
+ * AXI0:
3078
+ * Cluster0/1, Esmart0/1, WriteBack
3079
+ *
3080
+ * AXI 1:
3081
+ * Cluster2/3, Esmart2/3
3082
+ *
3083
+ * @TODO describe the wind like cpu-map dt nodes;
3084
+ */
3085
+static const struct vop2_win_data rk3588_vop_win_data[] = {
3086
+	{
3087
+	  .name = "Cluster0-win0",
3088
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
3089
+	  .splice_win_id = ROCKCHIP_VOP2_CLUSTER1,
3090
+	  .base = 0x00,
3091
+	  .formats = formats_for_cluster,
3092
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3093
+	  .format_modifiers = format_modifiers_afbc,
3094
+	  .layer_sel_id = { 0, 0, 0, 0 },
3095
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3096
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3097
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3098
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3099
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3100
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3101
+	  .regs = &rk3568_cluster0_win_data,
3102
+	  .pd_id = VOP2_PD_CLUSTER0,
3103
+	  .axi_id = 0,
3104
+	  .axi_yrgb_id = 2,
3105
+	  .axi_uv_id = 3,
3106
+	  .max_upscale_factor = 4,
3107
+	  .max_downscale_factor = 4,
3108
+	  .dly = { 4, 26, 29 },
3109
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3110
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_SPLICE_LEFT,
3111
+	},
3112
+
3113
+	{
3114
+	  .name = "Cluster0-win1",
3115
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
3116
+	  .base = 0x80,
3117
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3118
+	  .formats = formats_for_cluster,
3119
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3120
+	  .format_modifiers = format_modifiers_afbc,
3121
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3122
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3123
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3124
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3125
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3126
+	  .regs = &rk3568_cluster0_win_data,
3127
+	  .axi_id = 0,
3128
+	  .axi_yrgb_id = 4,
3129
+	  .axi_uv_id = 5,
3130
+	  .max_upscale_factor = 4,
3131
+	  .max_downscale_factor = 4,
3132
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3133
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3134
+	},
3135
+
3136
+	{
3137
+	  .name = "Cluster1-win0",
3138
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER1,
3139
+	  .base = 0x00,
3140
+	  .formats = formats_for_cluster,
3141
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3142
+	  .format_modifiers = format_modifiers_afbc,
3143
+	  .layer_sel_id = { 1, 1, 1, 1 },
3144
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3145
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3146
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3147
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3148
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3149
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3150
+	  .regs = &rk3568_cluster1_win_data,
3151
+	  .pd_id = VOP2_PD_CLUSTER1,
3152
+	  .axi_id = 0,
3153
+	  .axi_yrgb_id = 6,
3154
+	  .axi_uv_id = 7,
3155
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3156
+	  .max_upscale_factor = 4,
3157
+	  .max_downscale_factor = 4,
3158
+	  .dly = { 4, 26, 29 },
3159
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
3160
+	},
3161
+
3162
+	{
3163
+	  .name = "Cluster1-win1",
3164
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER1,
3165
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3166
+	  .formats = formats_for_cluster,
3167
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3168
+	  .format_modifiers = format_modifiers_afbc,
3169
+	  .base = 0x80,
3170
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3171
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3172
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3173
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3174
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3175
+	  .regs = &rk3568_cluster1_win_data,
3176
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3177
+	  .axi_id = 0,
3178
+	  .axi_yrgb_id = 8,
3179
+	  .axi_uv_id = 9,
3180
+	  .max_upscale_factor = 4,
3181
+	  .max_downscale_factor = 4,
3182
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3183
+	},
3184
+
3185
+	{
3186
+	  .name = "Cluster2-win0",
3187
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER2,
3188
+	  .pd_id = VOP2_PD_CLUSTER2,
3189
+	  .splice_win_id = ROCKCHIP_VOP2_CLUSTER3,
3190
+	  .base = 0x00,
3191
+	  .formats = formats_for_cluster,
3192
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3193
+	  .format_modifiers = format_modifiers_afbc,
3194
+	  .layer_sel_id = { 4, 4, 4, 4 },
3195
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3196
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3197
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3198
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3199
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3200
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3201
+	  .regs = &rk3588_cluster2_win_data,
3202
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3203
+	  .axi_id = 1,
3204
+	  .axi_yrgb_id = 2,
3205
+	  .axi_uv_id = 3,
3206
+	  .max_upscale_factor = 4,
3207
+	  .max_downscale_factor = 4,
3208
+	  .dly = { 4, 26, 29 },
3209
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_SPLICE_LEFT,
3210
+	},
3211
+
3212
+	{
3213
+	  .name = "Cluster2-win1",
3214
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER2,
3215
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3216
+	  .formats = formats_for_cluster,
3217
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3218
+	  .format_modifiers = format_modifiers_afbc,
3219
+	  .base = 0x80,
3220
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3221
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3222
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3223
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3224
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3225
+	  .regs = &rk3588_cluster2_win_data,
3226
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3227
+	  .axi_id = 1,
3228
+	  .axi_yrgb_id = 4,
3229
+	  .axi_uv_id = 5,
3230
+	  .max_upscale_factor = 4,
3231
+	  .max_downscale_factor = 4,
3232
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3233
+	},
3234
+
3235
+	{
3236
+	  .name = "Cluster3-win0",
3237
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER3,
3238
+	  .pd_id = VOP2_PD_CLUSTER3,
3239
+	  .base = 0x00,
3240
+	  .formats = formats_for_cluster,
3241
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3242
+	  .format_modifiers = format_modifiers_afbc,
3243
+	  .layer_sel_id = { 5, 5, 5, 5 },
3244
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
3245
+				 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3246
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3247
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3248
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3249
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3250
+	  .regs = &rk3588_cluster3_win_data,
3251
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3252
+	  .axi_id = 1,
3253
+	  .axi_yrgb_id = 6,
3254
+	  .axi_uv_id = 7,
3255
+	  .max_upscale_factor = 4,
3256
+	  .max_downscale_factor = 4,
3257
+	  .dly = { 4, 26, 29 },
3258
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN,
3259
+	},
3260
+
3261
+	{
3262
+	  .name = "Cluster3-win1",
3263
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER3,
3264
+	  .layer_sel_id = { 0xff, 0xff, 0xff, 0xff },
3265
+	  .formats = formats_for_cluster,
3266
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
3267
+	  .format_modifiers = format_modifiers_afbc,
3268
+	  .base = 0x80,
3269
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
3270
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3271
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3272
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3273
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3274
+	  .regs = &rk3588_cluster3_win_data,
3275
+	  .type = DRM_PLANE_TYPE_OVERLAY,
3276
+	  .axi_id = 1,
3277
+	  .axi_yrgb_id = 8,
3278
+	  .axi_uv_id = 9,
3279
+	  .max_upscale_factor = 4,
3280
+	  .max_downscale_factor = 4,
3281
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
3282
+	},
3283
+
3284
+	{
3285
+	  .name = "Esmart0-win0",
3286
+	  .phys_id = ROCKCHIP_VOP2_ESMART0,
3287
+	  .splice_win_id = ROCKCHIP_VOP2_ESMART1,
3288
+	  .formats = formats_for_esmart,
3289
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3290
+	  .format_modifiers = format_modifiers,
3291
+	  .base = 0x0,
3292
+	  .layer_sel_id = { 2, 2, 2, 2 },
3293
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3294
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3295
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3296
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3297
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3298
+	  .regs = &rk3568_esmart_win_data,
3299
+	  .area = rk3568_area_data,
3300
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3301
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3302
+	  .axi_id = 0,
3303
+	  .axi_yrgb_id = 0x0a,
3304
+	  .axi_uv_id = 0x0b,
3305
+	  .max_upscale_factor = 8,
3306
+	  .max_downscale_factor = 8,
3307
+	  .dly = { 23, 45, 48 },
3308
+	  .feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
3309
+	},
3310
+
3311
+	{
3312
+	  .name = "Esmart2-win0",
3313
+	  .phys_id = ROCKCHIP_VOP2_ESMART2,
3314
+	  .pd_id = VOP2_PD_ESMART,
3315
+	  .splice_win_id = ROCKCHIP_VOP2_ESMART3,
3316
+	  .base = 0x400,
3317
+	  .formats = formats_for_esmart,
3318
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3319
+	  .format_modifiers = format_modifiers,
3320
+	  .layer_sel_id = { 6, 6, 6, 6 },
3321
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3322
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3323
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3324
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3325
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3326
+	  .regs = &rk3568_esmart_win_data,
3327
+	  .area = rk3568_area_data,
3328
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3329
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3330
+	  .axi_id = 1,
3331
+	  .axi_yrgb_id = 0x0a,
3332
+	  .axi_uv_id = 0x0b,
3333
+	  .max_upscale_factor = 8,
3334
+	  .max_downscale_factor = 8,
3335
+	  .dly = { 23, 45, 48 },
3336
+	  .feature = WIN_FEATURE_SPLICE_LEFT | WIN_FEATURE_MULTI_AREA,
3337
+	},
3338
+
3339
+	{
3340
+	  .name = "Esmart1-win0",
3341
+	  .phys_id = ROCKCHIP_VOP2_ESMART1,
3342
+	  .pd_id = VOP2_PD_ESMART,
3343
+	  .formats = formats_for_esmart,
3344
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3345
+	  .format_modifiers = format_modifiers,
3346
+	  .base = 0x200,
3347
+	  .layer_sel_id = { 3, 3, 3, 3 },
3348
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3349
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3350
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3351
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3352
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3353
+	  .regs = &rk3568_esmart_win_data,
3354
+	  .area = rk3568_area_data,
3355
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3356
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3357
+	  .axi_id = 0,
3358
+	  .axi_yrgb_id = 0x0c,
3359
+	  .axi_uv_id = 0x01,
3360
+	  .max_upscale_factor = 8,
3361
+	  .max_downscale_factor = 8,
3362
+	  .dly = { 23, 45, 48 },
3363
+	  .feature = WIN_FEATURE_MULTI_AREA,
3364
+	},
3365
+
3366
+	{
3367
+	  .name = "Esmart3-win0",
3368
+	  .phys_id = ROCKCHIP_VOP2_ESMART3,
3369
+	  .pd_id = VOP2_PD_ESMART,
3370
+	  .formats = formats_for_esmart,
3371
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
3372
+	  .format_modifiers = format_modifiers,
3373
+	  .base = 0x600,
3374
+	  .layer_sel_id = { 7, 7, 7, 7 },
3375
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
3376
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
3377
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3378
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
3379
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
3380
+	  .regs = &rk3568_esmart_win_data,
3381
+	  .area = rk3568_area_data,
3382
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
3383
+	  .type = DRM_PLANE_TYPE_PRIMARY,
3384
+	  .axi_id = 1,
3385
+	  .axi_yrgb_id = 0x0c,
3386
+	  .axi_uv_id = 0x0d,
3387
+	  .max_upscale_factor = 8,
3388
+	  .max_downscale_factor = 8,
3389
+	  .dly = { 23, 45, 48 },
3390
+	  .feature = WIN_FEATURE_MULTI_AREA,
3391
+	},
3392
+};
3393
+
3394
+static const struct vop2_ctrl rk3528_vop_ctrl = {
3395
+	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
3396
+	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
3397
+	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
3398
+	.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
3399
+	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
3400
+	.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
3401
+	.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
3402
+	.dsp_vs_t_sel = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 16),
3403
+	.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
3404
+	.hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
3405
+	.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
3406
+	.rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
3407
+	.hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 10),
3408
+	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
3409
+	.bt656_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 6),
3410
+	.hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
3411
+	.hdmi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 7),
3412
+	.esmart_lb_mode = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 26),
3413
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 0),
3414
+	.win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 16),
3415
+	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 20),
3416
+	.win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 24),
3417
+	.win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 28),
3418
+	.win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3528_OVL_SYS_CLUSTER0_CTRL, 0xffff, 0),
3419
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_ESMART0_CTRL, 0xff, 0),
3420
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_ESMART1_CTRL, 0xff, 0),
3421
+	.win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_ESMART2_CTRL, 0xff, 0),
3422
+	.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0),
3423
+};
3424
+
3425
+static const struct vop_grf_ctrl rk3562_sys_grf_ctrl = {
3426
+	.grf_bt656_clk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3),
3427
+	.grf_bt1120_clk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3),
3428
+	.grf_dclk_inv = VOP_REG(RK3562_GRF_IOC_VO_IO_CON, 0x1, 3),
3429
+};
3430
+
3431
+static const struct vop2_ctrl rk3562_vop_ctrl = {
3432
+	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
3433
+	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
3434
+	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
3435
+	.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
3436
+	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
3437
+	.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
3438
+	.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
3439
+	.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
3440
+	.mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4),
3441
+	.lvds0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5),
3442
+	.bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6),
3443
+	.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
3444
+	.rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
3445
+	.mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
3446
+	.lvds0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
3447
+	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
3448
+	.bt656_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 6),
3449
+	.bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
3450
+	.bt1120_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 10),
3451
+	.rgb_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
3452
+	.lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
3453
+	.lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
3454
+	.mipi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 12),
3455
+	.mipi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 15),
3456
+	.gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 12),
3457
+	.esmart_lb_mode = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 26),
3458
+	.win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 16),
3459
+	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 20),
3460
+	.win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 24),
3461
+	.win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 28),
3462
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_ESMART0_CTRL, 0xff, 0),
3463
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_ESMART1_CTRL, 0xff, 0),
3464
+	.win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_ESMART2_CTRL, 0xff, 0),
3465
+	.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0),
3466
+};
3467
+
3468
+static const struct vop_grf_ctrl rk3568_sys_grf_ctrl = {
11973469 	.grf_bt656_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 1),
11983470 	.grf_bt1120_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 2),
11993471 	.grf_dclk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 3),
....@@ -1235,6 +3507,7 @@
12353507 	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
12363508 	.bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
12373509 	.gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 0),
3510
+	.rgb_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
12383511 	.lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
12393512 	.lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
12403513 	.hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
....@@ -1249,13 +3522,144 @@
12493522 	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
12503523 	.win_vp_id[ROCKCHIP_VOP2_SMART0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
12513524 	.win_vp_id[ROCKCHIP_VOP2_SMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
1252
-	.win_dly[0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
1253
-	.win_dly[1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
1254
-	.win_dly[2] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
1255
-	.win_dly[3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
1256
-	.win_dly[4] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
1257
-	.win_dly[5] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
3525
+	.win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
3526
+	.win_dly[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
3527
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
3528
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
3529
+	.win_dly[ROCKCHIP_VOP2_SMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
3530
+	.win_dly[ROCKCHIP_VOP2_SMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
12583531 	.otp_en = VOP_REG(RK3568_OTP_WIN_EN, 0x1, 0),
3532
+};
3533
+
3534
+static const struct vop_grf_ctrl rk3588_sys_grf_ctrl = {
3535
+	.grf_bt656_clk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
3536
+	.grf_bt1120_clk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
3537
+	.grf_dclk_inv = VOP_REG(RK3588_GRF_SOC_CON1, 0x1, 14),
3538
+};
3539
+
3540
+static const struct vop_grf_ctrl rk3588_vop_grf_ctrl = {
3541
+	.grf_edp0_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 0),
3542
+	.grf_hdmi0_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 1),
3543
+	.grf_hdmi0_dsc_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 2),
3544
+	.grf_edp1_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 3),
3545
+	.grf_hdmi1_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 4),
3546
+	.grf_hdmi1_dsc_en = VOP_REG(RK3588_GRF_VOP_CON2, 0x1, 4),
3547
+};
3548
+
3549
+static const struct vop_grf_ctrl rk3588_vo1_grf_ctrl = {
3550
+	.grf_hdmi0_pin_pol = VOP_REG(RK3588_GRF_VO1_CON0, 0x3, 5),
3551
+	.grf_hdmi1_pin_pol = VOP_REG(RK3588_GRF_VO1_CON0, 0x3, 7),
3552
+};
3553
+
3554
+static const struct vop2_ctrl rk3588_vop_ctrl = {
3555
+	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
3556
+	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
3557
+	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
3558
+	.dma_finish_mode = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x3, 0),
3559
+	.axi_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 2),
3560
+	.wb_dma_finish_and_en = VOP_REG(RK3588_SYS_VAR_FREQ_CTRL, 0x1, 3),
3561
+	.ovl_cfg_done_port = VOP_REG(RK3568_OVL_CTRL, 0x3, 30),
3562
+	.ovl_port_mux_cfg_done_imd = VOP_REG(RK3568_OVL_CTRL, 0x1, 28),
3563
+	.ovl_port_mux_cfg = VOP_REG(RK3568_OVL_PORT_SEL, 0xffff, 0),
3564
+	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
3565
+	.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
3566
+	.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
3567
+	.src_color_ctrl = VOP_REG(RK3568_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
3568
+	.dst_color_ctrl = VOP_REG(RK3568_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
3569
+	.src_alpha_ctrl = VOP_REG(RK3568_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
3570
+	.dst_alpha_ctrl = VOP_REG(RK3568_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
3571
+	.dp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
3572
+	.dp1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
3573
+	.edp0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 2),
3574
+	.hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 3),
3575
+	.edp1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 4),
3576
+	.hdmi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 5),
3577
+	.mipi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 6),
3578
+	.mipi1_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
3579
+	.bt1120_en = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
3580
+	.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 9),
3581
+	.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 10),
3582
+	.dp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 12),
3583
+	.dp1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 14),
3584
+	.hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
3585
+	.edp0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 16),
3586
+	.hdmi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
3587
+	.edp1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 18),
3588
+	.mipi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x1, 20),
3589
+	.mipi1_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 21),
3590
+	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 1),
3591
+	.bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
3592
+	.hdmi_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8),
3593
+	.edp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 8),
3594
+	.dp_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
3595
+	.mipi_dual_en = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 10),
3596
+	.mipi0_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 11),
3597
+	.mipi1_ds_mode = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 12),
3598
+	.hdmi0_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 16),
3599
+	.hdmi0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 18),
3600
+	.hdmi1_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 20),
3601
+	.hdmi1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 22),
3602
+	.edp0_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 16),
3603
+	.edp0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 18),
3604
+	.edp1_dclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 20),
3605
+	.edp1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 22),
3606
+
3607
+	.mipi0_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 24),
3608
+	.mipi1_pixclk_div = VOP_REG(RK3568_DSP_IF_CTRL, 0x3, 26),
3609
+	/* HDMI pol control by GRF_VO1_CON0
3610
+	 * DP0/1 clk pol is fixed
3611
+	 * MIPI/eDP pol is fixed
3612
+	 */
3613
+	.rgb_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
3614
+	.rgb_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
3615
+	.dp0_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 8),
3616
+	.dp1_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 12),
3617
+	.gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 12),
3618
+	.pd_off_imd = VOP_REG(RK3568_SYS_PD_CTRL, 0x1, 31),
3619
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 16),
3620
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 18),
3621
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 20),
3622
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 22),
3623
+	.win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 24),
3624
+	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 26),
3625
+	.win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 28),
3626
+	.win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_OVL_PORT_SEL, 0x3, 30),
3627
+	.win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 0),
3628
+	.win_dly[ROCKCHIP_VOP2_CLUSTER1] = VOP_REG(RK3568_CLUSTER_DLY_NUM, 0xffff, 16),
3629
+	.win_dly[ROCKCHIP_VOP2_CLUSTER2] = VOP_REG(RK3568_CLUSTER_DLY_NUM1, 0xffff, 0),
3630
+	.win_dly[ROCKCHIP_VOP2_CLUSTER3] = VOP_REG(RK3568_CLUSTER_DLY_NUM1, 0xffff, 16),
3631
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 0),
3632
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 8),
3633
+	.win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 16),
3634
+	.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3568_SMART_DLY_NUM, 0xff, 24),
3635
+};
3636
+
3637
+static const struct vop_dump_regs rk3528_dump_regs[] = {
3638
+	{ RK3568_REG_CFG_DONE, "SYS", {0}, 0 },
3639
+	{ RK3528_OVL_SYS, "OVL_SYS", {0}, 0 },
3640
+	{ RK3528_OVL_PORT0_CTRL, "OVL_VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3641
+	{ RK3528_OVL_PORT1_CTRL, "OVL_VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3642
+	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3643
+	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3644
+	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0), 1 },
3645
+	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
3646
+	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
3647
+	{ RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_CTRL0, 0x1, 0), 1 },
3648
+	{ RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_CTRL0, 0x1, 0), 1 },
3649
+	{ RK3528_HDR_LUT_CTRL, "HDR", {0}, 0 },
3650
+};
3651
+
3652
+static const struct vop_dump_regs rk3562_dump_regs[] = {
3653
+	{ RK3568_REG_CFG_DONE, "SYS", {0}, 0 },
3654
+	{ RK3528_OVL_SYS, "OVL_SYS", {0}, 0 },
3655
+	{ RK3528_OVL_PORT0_CTRL, "OVL_VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3656
+	{ RK3528_OVL_PORT1_CTRL, "OVL_VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3657
+	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3658
+	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3659
+	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
3660
+	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
3661
+	{ RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_CTRL0, 0x1, 0), 1 },
3662
+	{ RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_CTRL0, 0x1, 0), 1 },
12593663 };
12603664 
12613665 static const struct vop_dump_regs rk3568_dump_regs[] = {
....@@ -1264,39 +3668,312 @@
12643668 	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
12653669 	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
12663670 	{ RK3568_VP2_DSP_CTRL, "VP2", VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31), 0 },
1267
-	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0), 1 },
1268
-	{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", VOP_REG(RK3568_CLUSTER1_CTRL, 1, 0), 1 },
3671
+	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0), 1 },
3672
+	{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0), 1 },
12693673 	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
12703674 	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
12713675 	{ RK3568_SMART0_CTRL0, "Smart0", VOP_REG(RK3568_SMART0_REGION0_CTRL, 0x1, 0), 1 },
12723676 	{ RK3568_SMART1_CTRL0, "Smart1", VOP_REG(RK3568_SMART1_REGION0_CTRL, 0x1, 0), 1 },
1273
-	{ RK3568_HDR_LUT_CTRL, "HDR", VOP_REG(RK3568_OVL_CTRL, 0x1, 4), 1 },
3677
+	{ RK3568_HDR_LUT_CTRL, "HDR", {0}, 0 },
3678
+};
3679
+
3680
+static const struct vop_dump_regs rk3588_dump_regs[] = {
3681
+	{ RK3568_REG_CFG_DONE, "SYS", {0}, 0 },
3682
+	{ RK3568_OVL_CTRL, "OVL", {0}, 0 },
3683
+	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
3684
+	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
3685
+	{ RK3568_VP2_DSP_CTRL, "VP2", VOP_REG(RK3568_VP2_DSP_CTRL, 0x1, 31), 0 },
3686
+	{ RK3588_VP3_DSP_CTRL, "VP3", VOP_REG(RK3588_VP3_DSP_CTRL, 0x1, 31), 0 },
3687
+	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0), 1 },
3688
+	{ RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", VOP_REG(RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0), 1 },
3689
+	{ RK3588_CLUSTER2_WIN0_CTRL0, "Cluster2", VOP_REG(RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0), 1 },
3690
+	{ RK3588_CLUSTER3_WIN0_CTRL0, "Cluster3", VOP_REG(RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0), 1 },
3691
+	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
3692
+	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
3693
+	{ RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_REGION0_CTRL, 0x1, 0), 1 },
3694
+	{ RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_REGION0_CTRL, 0x1, 0), 1 },
3695
+	{ RK3568_HDR_LUT_CTRL, "HDR", {0}, 0 },
3696
+};
3697
+
3698
+#define RK3568_PLANE_MASK_BASE \
3699
+	(BIT(ROCKCHIP_VOP2_CLUSTER0) | BIT(ROCKCHIP_VOP2_CLUSTER1) | \
3700
+	 BIT(ROCKCHIP_VOP2_ESMART0)  | BIT(ROCKCHIP_VOP2_ESMART1)  | \
3701
+	 BIT(ROCKCHIP_VOP2_SMART0)   | BIT(ROCKCHIP_VOP2_SMART1))
3702
+
3703
+#define RK3588_PLANE_MASK_BASE \
3704
+	(BIT(ROCKCHIP_VOP2_CLUSTER0) | BIT(ROCKCHIP_VOP2_CLUSTER1) | \
3705
+	 BIT(ROCKCHIP_VOP2_CLUSTER2) | BIT(ROCKCHIP_VOP2_CLUSTER3) | \
3706
+	 BIT(ROCKCHIP_VOP2_ESMART0)  | BIT(ROCKCHIP_VOP2_ESMART1)  | \
3707
+	 BIT(ROCKCHIP_VOP2_ESMART2)  | BIT(ROCKCHIP_VOP2_ESMART3))
3708
+
3709
+static struct vop2_vp_plane_mask rk3568_vp_plane_mask[ROCKCHIP_MAX_CRTC][ROCKCHIP_MAX_CRTC] = {
3710
+	{ /* one display policy */
3711
+		{/* main display */
3712
+			.primary_plane_id = ROCKCHIP_VOP2_SMART0,
3713
+			.attached_layers_nr = 6,
3714
+			.attached_layers = {
3715
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0,
3716
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1
3717
+				},
3718
+		},
3719
+		{/* second display */},
3720
+		{/* third  display */},
3721
+		{/* fourth display */},
3722
+	},
3723
+
3724
+	{ /* two display policy */
3725
+		{/* main display */
3726
+			.primary_plane_id = ROCKCHIP_VOP2_SMART0,
3727
+			.attached_layers_nr = 3,
3728
+			.attached_layers = {
3729
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0
3730
+				},
3731
+		},
3732
+
3733
+		{/* second display */
3734
+			.primary_plane_id = ROCKCHIP_VOP2_SMART1,
3735
+			.attached_layers_nr = 3,
3736
+			.attached_layers = {
3737
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1
3738
+				},
3739
+		},
3740
+		{/* third  display */},
3741
+		{/* fourth display */},
3742
+	},
3743
+
3744
+	{ /* three display policy */
3745
+		{/* main display */
3746
+			.primary_plane_id = ROCKCHIP_VOP2_SMART0,
3747
+			.attached_layers_nr = 3,
3748
+			.attached_layers = {
3749
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0
3750
+				},
3751
+		},
3752
+
3753
+		{/* second display */
3754
+			.primary_plane_id = ROCKCHIP_VOP2_SMART1,
3755
+			.attached_layers_nr = 2,
3756
+			.attached_layers = {
3757
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1
3758
+				},
3759
+		},
3760
+
3761
+		{/* third  display */
3762
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3763
+			.attached_layers_nr = 1,
3764
+			.attached_layers = { ROCKCHIP_VOP2_ESMART1 },
3765
+		},
3766
+
3767
+		{/* fourth display */},
3768
+	},
3769
+
3770
+	{/* reserved for four display policy */},
3771
+};
3772
+
3773
+static struct vop2_vp_plane_mask rk3588_vp_plane_mask[ROCKCHIP_MAX_CRTC][ROCKCHIP_MAX_CRTC] = {
3774
+	{ /* one display policy */
3775
+		{/* main display */
3776
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3777
+			.attached_layers_nr = 8,
3778
+			.attached_layers = {
3779
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2,
3780
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART3,
3781
+				  ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3
3782
+			},
3783
+		},
3784
+		{/* second display */},
3785
+		{/* third  display */},
3786
+		{/* fourth display */},
3787
+	},
3788
+
3789
+	{ /* two display policy */
3790
+		{/* main display */
3791
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3792
+			.attached_layers_nr = 4,
3793
+			.attached_layers = {
3794
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0,
3795
+				  ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1
3796
+			},
3797
+		},
3798
+
3799
+		{/* second display */
3800
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3801
+			.attached_layers_nr = 4,
3802
+			.attached_layers = {
3803
+				  ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2,
3804
+				  ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3
3805
+			},
3806
+		},
3807
+		{/* third  display */},
3808
+		{/* fourth display */},
3809
+	},
3810
+
3811
+	{ /* three display policy */
3812
+		{/* main display */
3813
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3814
+			.attached_layers_nr = 3,
3815
+			.attached_layers = {
3816
+				  ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0
3817
+			},
3818
+		},
3819
+
3820
+		{/* second display */
3821
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3822
+			.attached_layers_nr = 3,
3823
+			.attached_layers = {
3824
+				  ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1
3825
+			},
3826
+		},
3827
+
3828
+		{/* third  display */
3829
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3830
+			.attached_layers_nr = 2,
3831
+			.attached_layers = { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 },
3832
+		},
3833
+
3834
+		{/* fourth display */},
3835
+	},
3836
+
3837
+	{ /* four display policy */
3838
+		{/* main display */
3839
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART0,
3840
+			.attached_layers_nr = 2,
3841
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 },
3842
+		},
3843
+
3844
+		{/* second display */
3845
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART1,
3846
+			.attached_layers_nr = 2,
3847
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 },
3848
+		},
3849
+
3850
+		{/* third  display */
3851
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART2,
3852
+			.attached_layers_nr = 2,
3853
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 },
3854
+		},
3855
+
3856
+		{/* fourth display */
3857
+			.primary_plane_id = ROCKCHIP_VOP2_ESMART3,
3858
+			.attached_layers_nr = 2,
3859
+			.attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 },
3860
+		},
3861
+	},
3862
+
3863
+};
3864
+
3865
+static const struct vop2_data rk3528_vop = {
3866
+	.version = VOP_VERSION_RK3528,
3867
+	.nr_vps = 2,
3868
+	.nr_mixers = 4,
3869
+	.nr_layers = 4,
3870
+	.nr_gammas = 2,
3871
+	.esmart_lb_mode = VOP3_ESMART_4K_2K_2K_MODE,
3872
+	.max_input = { 4096, 4096 },
3873
+	.max_output = { 4096, 4096 },
3874
+	.ctrl = &rk3528_vop_ctrl,
3875
+	.axi_intr = rk3528_vop_axi_intr,
3876
+	.nr_axi_intr = ARRAY_SIZE(rk3528_vop_axi_intr),
3877
+	.vp = rk3528_vop_video_ports,
3878
+	.wb = &rk3568_vop_wb_data,
3879
+	.win = rk3528_vop_win_data,
3880
+	.win_size = ARRAY_SIZE(rk3528_vop_win_data),
3881
+	.dump_regs = rk3528_dump_regs,
3882
+	.dump_regs_size = ARRAY_SIZE(rk3528_dump_regs),
3883
+};
3884
+
3885
+static const struct vop2_data rk3562_vop = {
3886
+	.version = VOP_VERSION_RK3562,
3887
+	.nr_vps = ARRAY_SIZE(rk3562_vop_video_ports),
3888
+	.nr_mixers = 3,
3889
+	.nr_layers = 4,
3890
+	.nr_gammas = 2,
3891
+	.esmart_lb_mode = VOP3_ESMART_2K_2K_2K_2K_MODE,
3892
+	.max_input = { 4096, 4096 },
3893
+	.max_output = { 4096, 4096 },
3894
+	.ctrl = &rk3562_vop_ctrl,
3895
+	.sys_grf = &rk3562_sys_grf_ctrl,
3896
+	.axi_intr = rk3528_vop_axi_intr,
3897
+	.nr_axi_intr = ARRAY_SIZE(rk3528_vop_axi_intr),
3898
+	.vp = rk3562_vop_video_ports,
3899
+	.wb = &rk3568_vop_wb_data,
3900
+	.win = rk3562_vop_win_data,
3901
+	.win_size = ARRAY_SIZE(rk3562_vop_win_data),
3902
+	.dump_regs = rk3562_dump_regs,
3903
+	.dump_regs_size = ARRAY_SIZE(rk3562_dump_regs),
12743904 };
12753905 
12763906 static const struct vop2_data rk3568_vop = {
1277
-	.version = VOP_VERSION(0x40, 0x15),
3907
+	.version = VOP_VERSION_RK3568,
12783908 	.nr_vps = 3,
12793909 	.nr_mixers = 5,
3910
+	.nr_layers = 6,
12803911 	.nr_gammas = 1,
12813912 	.max_input = { 4096, 2304 },
12823913 	.max_output = { 4096, 2304 },
12833914 	.ctrl = &rk3568_vop_ctrl,
1284
-	.grf_ctrl = &rk3568_grf_ctrl,
3915
+	.sys_grf = &rk3568_sys_grf_ctrl,
12853916 	.axi_intr = rk3568_vop_axi_intr,
12863917 	.nr_axi_intr = ARRAY_SIZE(rk3568_vop_axi_intr),
12873918 	.vp = rk3568_vop_video_ports,
12883919 	.wb = &rk3568_vop_wb_data,
12893920 	.layer = rk3568_vop_layers,
1290
-	.nr_layers = ARRAY_SIZE(rk3568_vop_layers),
12913921 	.win = rk3568_vop_win_data,
12923922 	.win_size = ARRAY_SIZE(rk3568_vop_win_data),
12933923 	.dump_regs = rk3568_dump_regs,
12943924 	.dump_regs_size = ARRAY_SIZE(rk3568_dump_regs),
3925
+	.plane_mask = rk3568_vp_plane_mask[0],
3926
+	.plane_mask_base = RK3568_PLANE_MASK_BASE,
3927
+};
3928
+
3929
+static const struct vop2_data rk3588_vop = {
3930
+	.version = VOP_VERSION_RK3588,
3931
+	.feature = VOP_FEATURE_SPLICE,
3932
+	.nr_dscs = 2,
3933
+	.nr_dsc_ecw = ARRAY_SIZE(dsc_ecw),
3934
+	.nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow),
3935
+	.nr_vps = 4,
3936
+	.nr_mixers = 7,
3937
+	.nr_layers = 8,
3938
+	.nr_gammas = 4,
3939
+	.max_input = { 4096, 4320 },
3940
+	.max_output = { 4096, 4320 },
3941
+	.ctrl = &rk3588_vop_ctrl,
3942
+	.grf = &rk3588_vop_grf_ctrl,
3943
+	.sys_grf = &rk3588_sys_grf_ctrl,
3944
+	.vo1_grf = &rk3588_vo1_grf_ctrl,
3945
+	.axi_intr = rk3568_vop_axi_intr,
3946
+	.nr_axi_intr = ARRAY_SIZE(rk3568_vop_axi_intr),
3947
+	.dsc = rk3588_vop_dsc_data,
3948
+	.dsc_error_ecw = dsc_ecw,
3949
+	.dsc_error_buffer_flow = dsc_buffer_flow,
3950
+	.vp = rk3588_vop_video_ports,
3951
+	.conn = rk3588_conn_if_data,
3952
+	.nr_conns = ARRAY_SIZE(rk3588_conn_if_data),
3953
+	.wb = &rk3568_vop_wb_data,
3954
+	.layer = rk3568_vop_layers,
3955
+	.win = rk3588_vop_win_data,
3956
+	.win_size = ARRAY_SIZE(rk3588_vop_win_data),
3957
+	.pd = rk3588_vop_pd_data,
3958
+	.nr_pds = ARRAY_SIZE(rk3588_vop_pd_data),
3959
+	.mem_pg = rk3588_vop_mem_pg_data,
3960
+	.nr_mem_pgs = ARRAY_SIZE(rk3588_vop_mem_pg_data),
3961
+	.dump_regs = rk3588_dump_regs,
3962
+	.dump_regs_size = ARRAY_SIZE(rk3588_dump_regs),
3963
+	.plane_mask = rk3588_vp_plane_mask[0],
3964
+	.plane_mask_base = RK3588_PLANE_MASK_BASE,
12953965 };
12963966 
12973967 static const struct of_device_id vop2_dt_match[] = {
3968
+	{ .compatible = "rockchip,rk3528-vop",
3969
+	  .data = &rk3528_vop },
3970
+	{ .compatible = "rockchip,rk3562-vop",
3971
+	  .data = &rk3562_vop },
12983972 	{ .compatible = "rockchip,rk3568-vop",
12993973 	  .data = &rk3568_vop },
3974
+	{ .compatible = "rockchip,rk3588-vop",
3975
+	  .data = &rk3588_vop },
3976
+
13003977 	{},
13013978 };
13023979 MODULE_DEVICE_TABLE(of, vop2_dt_match);