~hc/RK356X_SDK_RELEASE.git

..	..	@@ -4,12 +4,18 @@
4	4	* Author: Andy Yan <andy.yan@rock-chips.com>
5	5	*/
6	6	#include <drm/drm.h>
7		-#include <drm/drmP.h>
8	7	#include <drm/drm_atomic.h>
	8	+#include <drm/drm_atomic_uapi.h>
9	9	#include <drm/drm_crtc.h>
10	10	#include <drm/drm_crtc_helper.h>
	11	+#include <drm/drm_debugfs.h>
11	12	#include <drm/drm_flip_work.h>
	13	+#include <drm/drm_fourcc.h>
	14	+#include <drm/drm_gem_framebuffer_helper.h>
12	15	#include <drm/drm_plane_helper.h>
	16	+#include <drm/drm_probe_helper.h>
	17	+#include <drm/drm_self_refresh_helper.h>
	18	+
13	19	#include <drm/drm_writeback.h>
14	20	#ifdef CONFIG_DRM_ANALOGIX_DP
15	21	#include <drm/bridge/analogix_dp.h>
..	..	@@ -23,6 +29,8 @@
23	29	#include <linux/module.h>
24	30	#include <linux/platform_device.h>
25	31	#include <linux/clk.h>
	32	+#include <linux/clk-provider.h>
	33	+#include <linux/clk/clk-conf.h>
26	34	#include <linux/iopoll.h>
27	35	#include <linux/of.h>
28	36	#include <linux/of_device.h>
..	..	@@ -30,23 +38,27 @@
30	38	#include <linux/pm_runtime.h>
31	39	#include <linux/component.h>
32	40	#include <linux/regmap.h>
	41	+#include <linux/reset.h>
33	42	#include <linux/mfd/syscon.h>
34	43	#include <linux/delay.h>
35	44	#include <linux/swab.h>
36	45	#include <linux/sort.h>
37	46	#include <linux/rockchip/cpu.h>
	47	+#include <linux/workqueue.h>
	48	+#include <linux/types.h>
38	49	#include <soc/rockchip/rockchip_dmc.h>
39	50	#include <soc/rockchip/rockchip-system-status.h>
40	51	#include <uapi/linux/videodev2.h>
41	52
	53	+#include "../drm_crtc_internal.h"
42	54	#include "../drm_internal.h"
43	55
44	56	#include "rockchip_drm_drv.h"
45	57	#include "rockchip_drm_gem.h"
46	58	#include "rockchip_drm_fb.h"
47		-#include "rockchip_drm_psr.h"
48	59	#include "rockchip_drm_vop.h"
49	60	#include "rockchip_vop_reg.h"
	61	+#include "rockchip_post_csc.h"
50	62
51	63	#define _REG_SET(vop2, name, off, reg, mask, v, relaxed) \
52	64	vop2_mask_write(vop2, off + reg.offset, mask, reg.shift, v, reg.write_mask, relaxed)
..	..	@@ -78,6 +90,8 @@
78	90
79	91	#define VOP_CTRL_SET(x, name, v) \
80	92	REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
	93	+
	94	+#define VOP_CTRL_GET(x, name) vop2_read_reg(x, 0, &(x)->data->ctrl->name)
81	95
82	96	#define VOP_INTR_GET(vop2, name) \
83	97	vop2_read_reg(vop2, 0, &vop2->data->ctrl->name)
..	..	@@ -112,27 +126,32 @@
112	126	#define VOP_WIN_GET(vop2, win, name) \
113	127	vop2_read_reg(vop2, win->offset, &VOP_WIN_NAME(win, name))
114	128
	129	+#define VOP_WIN_GET_REG_BAK(vop2, win, name) \
	130	+ vop2_read_reg_bak(vop2, win->offset, &VOP_WIN_NAME(win, name))
	131	+
115	132	#define VOP_WIN_NAME(win, name) \
116	133	(vop2_get_win_regs(win, &win->regs->name)->name)
117	134
118	135	#define VOP_WIN_TO_INDEX(vop2_win) \
119	136	((vop2_win) - (vop2_win)->vop2->win)
120	137
121		-#define VOP_GRF_SET(vop2, reg, v) \
	138	+#define VOP_GRF_SET(vop2, grf, reg, v) \
122	139	do { \
123		- if (vop2->data->grf_ctrl) { \
124		- vop2_grf_writel(vop2, vop2->data->grf_ctrl->reg, v); \
	140	+ if (vop2->data->grf) { \
	141	+ vop2_grf_writel(vop2->grf, vop2->data->grf->reg, v); \
125	142	} \
126	143	} while (0)
127	144
128		-#define to_vop2_video_port(c) container_of(c, struct vop2_video_port, crtc)
129	145	#define to_vop2_win(x) container_of(x, struct vop2_win, base)
130	146	#define to_vop2_plane_state(x) container_of(x, struct vop2_plane_state, base)
131	147	#define to_wb_state(x) container_of(x, struct vop2_wb_connector_state, base)
132		-
133		-#ifndef drm_is_afbc
134		-#define drm_is_afbc(modifier) (((modifier) >> 56) == DRM_FORMAT_MOD_VENDOR_ARM)
135		-#endif
	148	+#define output_if_is_hdmi(x) (x & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1))
	149	+#define output_if_is_dp(x) (x & (VOP_OUTPUT_IF_DP0 \| VOP_OUTPUT_IF_DP1))
	150	+#define output_if_is_edp(x) (x & (VOP_OUTPUT_IF_eDP0 \| VOP_OUTPUT_IF_eDP1))
	151	+#define output_if_is_mipi(x) (x & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_MIPI1))
	152	+#define output_if_is_lvds(x) (x & (VOP_OUTPUT_IF_LVDS0 \| VOP_OUTPUT_IF_LVDS1))
	153	+#define output_if_is_dpi(x) (x & (VOP_OUTPUT_IF_BT656 \| VOP_OUTPUT_IF_BT1120 \| \
	154	+ VOP_OUTPUT_IF_RGB))
136	155
137	156	/*
138	157	* max two jobs a time, one is running(writing back),
..	..	@@ -141,7 +160,11 @@
141	160	#define VOP2_WB_JOB_MAX 2
142	161	#define VOP2_SYS_AXI_BUS_NUM 2
143	162
144		-#define VOP2_CLUSTER_YUV444_10 0x12
	163	+#define VOP2_MAX_VP_OUTPUT_WIDTH 4096
	164	+/* KHZ */
	165	+#define VOP2_MAX_DCLK_RATE 600000
	166	+/* KHZ */
	167	+#define VOP2_COMMON_ACLK_RATE 500000
145	168
146	169	enum vop2_data_format {
147	170	VOP2_FMT_ARGB8888 = 0,
..	..	@@ -233,6 +256,36 @@
233	256	ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
234	257	};
235	258
	259	+struct vop2_power_domain {
	260	+ struct vop2_power_domain *parent;
	261	+ struct vop2 *vop2;
	262	+ /*
	263	+ * @lock: protect power up/down procedure.
	264	+ * power on take effect immediately,
	265	+ * power down take effect by vsync.
	266	+ * we must check power_domain_status register
	267	+ * to make sure the power domain is down before
	268	+ * send a power on request.
	269	+ *
	270	+ */
	271	+ spinlock_t lock;
	272	+ unsigned int ref_count;
	273	+ bool on;
	274	+ /* @vp_mask: Bit mask of video port of the power domain's
	275	+ * module attached to.
	276	+ * For example: PD_CLUSTER0 belongs to module Cluster0, it's
	277	+ * bitmask is the VP which Cluster0 attached to. PD_ESMART is
	278	+ * shared between Esmart1/2/3, it's bitmask will be all the VP
	279	+ * which Esmart1/2/3 attached to.
	280	+ * This is used to check if we can power off a PD by vsync.
	281	+ */
	282	+ uint8_t vp_mask;
	283	+
	284	+ const struct vop2_power_domain_data *data;
	285	+ struct list_head list;
	286	+ struct delayed_work power_off_work;
	287	+};
	288	+
236	289	struct vop2_zpos {
237	290	struct drm_plane *plane;
238	291	int win_phys_id;
..	..	@@ -316,7 +369,6 @@
316	369	int global_alpha;
317	370	int blend_mode;
318	371	uint64_t color_key;
319		- void *yrgb_kvaddr;
320	372	unsigned long offset;
321	373	int pdaf_data_type;
322	374	bool async_commit;
..	..	@@ -338,11 +390,37 @@
338	390	bool two_win_mode;
339	391
340	392	/**
	393	+ * ---------------------------
	394	+ * \| \| \|
	395	+ * \| Left \| Right \|
	396	+ * \| \| \|
	397	+ * \| Cluster0 \| Cluster1 \|
	398	+ * ---------------------------
	399	+ */
	400	+
	401	+ /*
	402	+ * @splice_mode_right: As right part of the screen in splice mode.
	403	+ */
	404	+ bool splice_mode_right;
	405	+
	406	+ /**
	407	+ * @splice_win: splice win which used to splice for a plane
	408	+ * hdisplay > 4096
	409	+ */
	410	+ struct vop2_win *splice_win;
	411	+ struct vop2_win *left_win;
	412	+
	413	+ uint8_t splice_win_id;
	414	+
	415	+ struct vop2_power_domain *pd;
	416	+
	417	+ /**
341	418	* @phys_id: physical id for cluster0/1, esmart0/1, smart0/1
342	419	* Will be used as a identification for some register
343	420	* configuration such as OVL_LAYER_SEL/OVL_PORT_SEL.
344	421	*/
345	422	uint8_t phys_id;
	423	+
346	424	/**
347	425	* @win_id: graphic window id, a cluster maybe split into two
348	426	* graphics windows.
..	..	@@ -410,6 +488,7 @@
410	488	};
411	489
412	490	struct vop2_cluster {
	491	+ bool splice_mode;
413	492	struct vop2_win *main;
414	493	struct vop2_win *sub;
415	494	};
..	..	@@ -451,6 +530,17 @@
451	530
452	531	};
453	532
	533	+struct vop2_dsc {
	534	+ uint8_t id;
	535	+ uint8_t max_slice_num;
	536	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	537	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	538	+ bool enabled;
	539	+ char attach_vp_id;
	540	+ const struct vop2_dsc_regs *regs;
	541	+ struct vop2_power_domain *pd;
	542	+};
	543	+
454	544	enum vop2_wb_format {
455	545	VOP2_WB_ARGB8888,
456	546	VOP2_WB_BGR888,
..	..	@@ -471,12 +561,17 @@
471	561	};
472	562
473	563	struct vop2_video_port {
474		- struct drm_crtc crtc;
	564	+ struct rockchip_crtc rockchip_crtc;
	565	+ struct rockchip_mcu_timing mcu_timing;
475	566	struct vop2 *vop2;
	567	+ struct reset_control *dclk_rst;
476	568	struct clk *dclk;
	569	+ struct clk *dclk_parent;
477	570	uint8_t id;
478	571	bool layer_sel_update;
479	572	bool xmirror_en;
	573	+ bool need_reset_p2i_flag;
	574	+ atomic_t post_buf_empty_flag;
480	575	const struct vop2_video_port_regs *regs;
481	576
482	577	struct completion dsp_hold_completion;
..	..	@@ -524,6 +619,26 @@
524	619	int hdr_en;
525	620
526	621	/**
	622	+ * -----------------
	623	+ * \| \| \|
	624	+ * \| Left \| Right \|
	625	+ * \| \| \|
	626	+ * \| VP0 \| VP1 \|
	627	+ * -----------------
	628	+ * @splice_mode_right: As right part of the screen in splice mode.
	629	+ */
	630	+ bool splice_mode_right;
	631	+
	632	+ /**
	633	+ * @hdr10_at_splice_mode: enable hdr10 at splice mode on rk3588.
	634	+ */
	635	+ bool hdr10_at_splice_mode;
	636	+ /**
	637	+ * @left_vp: VP as left part of the screen in splice mode.
	638	+ */
	639	+ struct vop2_video_port *left_vp;
	640	+
	641	+ /**
527	642	* @win_mask: Bitmask of wins attached to the video port;
528	643	*/
529	644	uint32_t win_mask;
..	..	@@ -533,6 +648,12 @@
533	648	uint8_t nr_layers;
534	649
535	650	int cursor_win_id;
	651	+ /**
	652	+ * @output_if: output connector attached to the video port,
	653	+ * this flag is maintained in vop driver, updated in crtc_atomic_enable,
	654	+ * cleared in crtc_atomic_disable;
	655	+ */
	656	+ u32 output_if;
536	657
537	658	/**
538	659	* @active_tv_state: TV connector related states
..	..	@@ -555,6 +676,11 @@
555	676	bool gamma_lut_active;
556	677
557	678	/**
	679	+ * @lut_dma_rid: lut dma id
	680	+ */
	681	+ u16 lut_dma_rid;
	682	+
	683	+ /**
558	684	* @gamma_lut: atomic gamma look up table
559	685	*/
560	686	struct drm_color_lut *gamma_lut;
..	..	@@ -568,6 +694,11 @@
568	694	* @cubic_lut_gem_obj: gem obj to store cubic lut
569	695	*/
570	696	struct rockchip_gem_object *cubic_lut_gem_obj;
	697	+
	698	+ /**
	699	+ * @hdr_lut_gem_obj: gem obj to store hdr lut
	700	+ */
	701	+ struct rockchip_gem_object *hdr_lut_gem_obj;
571	702
572	703	/**
573	704	* @cubic_lut: cubic look up table
..	..	@@ -589,27 +720,78 @@
589	720	* @plane_mask_prop: plane mask interaction with userspace
590	721	*/
591	722	struct drm_property *plane_mask_prop;
	723	+ /**
	724	+ * @feature_prop: crtc feature interaction with userspace
	725	+ */
	726	+ struct drm_property *feature_prop;
	727	+
	728	+ /**
	729	+ * @variable_refresh_rate_prop: crtc variable refresh rate interaction with userspace
	730	+ */
	731	+ struct drm_property *variable_refresh_rate_prop;
	732	+
	733	+ /**
	734	+ * @max_refresh_rate_prop: crtc max refresh rate interaction with userspace
	735	+ */
	736	+ struct drm_property *max_refresh_rate_prop;
	737	+
	738	+ /**
	739	+ * @min_refresh_rate_prop: crtc min refresh rate interaction with userspace
	740	+ */
	741	+ struct drm_property *min_refresh_rate_prop;
	742	+
	743	+ /**
	744	+ * @hdr_ext_data_prop: hdr extend data interaction with userspace
	745	+ */
	746	+ struct drm_property *hdr_ext_data_prop;
	747	+
	748	+ int hdrvivid_mode;
	749	+
	750	+ /**
	751	+ * @acm_lut_data_prop: acm lut data interaction with userspace
	752	+ */
	753	+ struct drm_property *acm_lut_data_prop;
	754	+ /**
	755	+ * @post_csc_data_prop: post csc data interaction with userspace
	756	+ */
	757	+ struct drm_property *post_csc_data_prop;
	758	+ /**
	759	+ * @output_width_prop: vp max output width prop
	760	+ */
	761	+ struct drm_property *output_width_prop;
	762	+ /**
	763	+ * @output_dclk_prop: vp max output dclk prop
	764	+ */
	765	+ struct drm_property *output_dclk_prop;
592	766
593	767	/**
594	768	* @primary_plane_phy_id: vp primary plane phy id, the primary plane
595	769	* will be used to show uboot logo and kernel logo
596	770	*/
597	771	enum vop2_layer_phy_id primary_plane_phy_id;
	772	+
	773	+ /**
	774	+ * @refresh_rate_change: indicate whether refresh rate change
	775	+ */
	776	+ bool refresh_rate_change;
	777	+};
	778	+
	779	+struct vop2_extend_pll {
	780	+ struct list_head list;
	781	+ struct clk *clk;
	782	+ char clk_name[32];
	783	+ u32 vp_mask;
598	784	};
599	785
600	786	struct vop2 {
601	787	u32 version;
602	788	struct device *dev;
603	789	struct drm_device *drm_dev;
	790	+ struct vop2_dsc dscs[ROCKCHIP_MAX_CRTC];
604	791	struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
605	792	struct vop2_wb wb;
606	793	struct dentry *debugfs;
607	794	struct drm_info_list *debugfs_files;
608		- struct drm_property *soc_id_prop;
609		- struct drm_property *vp_id_prop;
610		- struct drm_property *aclk_prop;
611		- struct drm_property *bg_prop;
612		- struct drm_property *line_flag_prop;
613	795	struct drm_prop_enum_list *plane_name_list;
614	796	bool is_iommu_enabled;
615	797	bool is_iommu_needed;
..	..	@@ -645,6 +827,9 @@
645	827
646	828	bool loader_protect;
647	829
	830	+ bool aclk_rate_reset;
	831	+ unsigned long aclk_rate;
	832	+
648	833	const struct vop2_data *data;
649	834	/* Number of win that registered as plane,
650	835	* maybe less than the total number of hardware
..	..	@@ -652,6 +837,7 @@
652	837	*/
653	838	uint32_t registered_num_wins;
654	839	uint8_t used_mixers;
	840	+ uint8_t esmart_lb_mode;
655	841	/**
656	842	* @active_vp_mask: Bitmask of active video ports;
657	843	*/
..	..	@@ -662,6 +848,10 @@
662	848	struct resource *res;
663	849	void __iomem *regs;
664	850	struct regmap *grf;
	851	+ struct regmap *sys_grf;
	852	+ struct regmap *vo0_grf;
	853	+ struct regmap *vo1_grf;
	854	+ struct regmap *sys_pmu;
665	855
666	856	/* physical map length of vop2 register */
667	857	uint32_t len;
..	..	@@ -684,11 +874,34 @@
684	874	unsigned int enable_count;
685	875	struct clk *hclk;
686	876	struct clk *aclk;
	877	+ struct clk *pclk;
	878	+ struct reset_control *ahb_rst;
	879	+ struct reset_control *axi_rst;
	880	+
	881	+ /* list_head of extend clk */
	882	+ struct list_head extend_clk_list_head;
	883	+ /* list_head of internal clk */
	884	+ struct list_head clk_list_head;
	885	+ struct list_head pd_list_head;
	886	+ struct work_struct post_buf_empty_work;
	887	+ struct workqueue_struct *workqueue;
687	888
688	889	struct vop2_layer layers[ROCKCHIP_MAX_LAYER];
689	890	/* must put at the end of the struct */
690	891	struct vop2_win win[];
691	892	};
	893	+
	894	+struct vop2_clk {
	895	+ struct vop2 *vop2;
	896	+ struct list_head list;
	897	+ unsigned long rate;
	898	+ struct clk_hw hw;
	899	+ struct clk_divider div;
	900	+ int div_val;
	901	+ u8 parent_index;
	902	+};
	903	+
	904	+#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw)
692	905
693	906	/*
694	907	* bus-format types.
..	..	@@ -704,22 +917,32 @@
704	917	{ MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" },
705	918	{ MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" },
706	919	{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" },
707		- { MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA, "RGB666_1X7X3_JEIDA" },
708	920	{ MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" },
709	921	{ MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
710	922	{ MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
711	923	{ MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
712		- { MEDIA_BUS_FMT_SRGB888_3X8, "SRGB888_3X8" },
713		- { MEDIA_BUS_FMT_SRGB888_DUMMY_4X8, "SRGB888_DUMMY_4X8" },
	924	+ { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
	925	+ { MEDIA_BUS_FMT_RGB888_DUMMY_4X8, "RGB888_DUMMY_4X8" },
714	926	{ MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
715	927	{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
716	928	{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
717	929	{ MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" },
718	930	{ MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" },
719	931	{ MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" },
	932	+ { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" },
	933	+ { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" },
720	934	};
721	935
722	936	static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list)
	937	+
	938	+static inline struct vop2_video_port to_vop2_video_port(struct drm_crtc crtc)
	939	+{
	940	+ struct rockchip_crtc *rockchip_crtc;
	941	+
	942	+ rockchip_crtc = container_of(crtc, struct rockchip_crtc, crtc);
	943	+
	944	+ return container_of(rockchip_crtc, struct vop2_video_port, rockchip_crtc);
	945	+}
723	946
724	947	static void vop2_lock(struct vop2 *vop2)
725	948	{
..	..	@@ -733,17 +956,26 @@
733	956	mutex_unlock(&vop2->vop2_lock);
734	957	}
735	958
736		-static inline void vop2_grf_writel(struct vop2 *vop2, struct vop_reg reg, u32 v)
	959	+static inline void vop2_grf_writel(struct regmap *regmap, struct vop_reg reg, u32 v)
737	960	{
738	961	u32 val = 0;
739	962
740		- if (IS_ERR_OR_NULL(vop2->grf))
	963	+ if (IS_ERR_OR_NULL(regmap))
741	964	return;
742	965
743	966	if (reg.mask) {
744	967	val = (v << reg.shift) \| (reg.mask << (reg.shift + 16));
745		- regmap_write(vop2->grf, reg.offset, val);
	968	+ regmap_write(regmap, reg.offset, val);
746	969	}
	970	+}
	971	+
	972	+static inline uint32_t vop2_grf_readl(struct regmap regmap, const struct vop_reg reg)
	973	+{
	974	+ uint32_t v;
	975	+
	976	+ regmap_read(regmap, reg->offset, &v);
	977	+
	978	+ return v;
747	979	}
748	980
749	981	static inline void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -761,6 +993,26 @@
761	993	const struct vop_reg *reg)
762	994	{
763	995	return (vop2_readl(vop2, base + reg->offset) >> reg->shift) & reg->mask;
	996	+}
	997	+
	998	+static inline uint32_t vop2_read_reg_bak(struct vop2 *vop2, uint32_t base,
	999	+ const struct vop_reg *reg)
	1000	+{
	1001	+ return (vop2->regsbak[(base + reg->offset) >> 2] >> reg->shift) & reg->mask;
	1002	+}
	1003	+
	1004	+static inline uint32_t vop2_read_grf_reg(struct regmap regmap, const struct vop_reg reg)
	1005	+{
	1006	+ return (vop2_grf_readl(regmap, reg) >> reg->shift) & reg->mask;
	1007	+}
	1008	+
	1009	+static inline void vop2_write_reg_uncached(struct vop2 vop2, const struct vop_reg reg, uint32_t v)
	1010	+{
	1011	+ uint32_t offset = reg->offset;
	1012	+ uint32_t cached_val = vop2->regsbak[offset >> 2];
	1013	+
	1014	+ v = (cached_val & ~(reg->mask << reg->shift)) \| ((v & reg->mask) << reg->shift);
	1015	+ writel(v, vop2->regs + offset);
764	1016	}
765	1017
766	1018	static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset,
..	..	@@ -841,7 +1093,7 @@
841	1093	}
842	1094	}
843	1095
844		-void vop2_standby(struct drm_crtc *crtc, bool standby)
	1096	+static void vop2_crtc_standby(struct drm_crtc *crtc, bool standby)
845	1097	{
846	1098	struct vop2_video_port *vp = to_vop2_video_port(crtc);
847	1099	struct vop2 *vop2 = vp->vop2;
..	..	@@ -853,7 +1105,6 @@
853	1105	VOP_MODULE_SET(vop2, vp, standby, 0);
854	1106	}
855	1107	}
856		-EXPORT_SYMBOL(vop2_standby);
857	1108
858	1109	static inline const struct vop2_win_regs vop2_get_win_regs(struct vop2_win win,
859	1110	const struct vop_reg *reg)
..	..	@@ -899,6 +1150,32 @@
899	1150	return NULL;
900	1151	}
901	1152
	1153	+static struct vop2_power_domain vop2_find_pd_by_id(struct vop2 vop2, uint8_t id)
	1154	+{
	1155	+ struct vop2_power_domain pd, n;
	1156	+
	1157	+ list_for_each_entry_safe(pd, n, &vop2->pd_list_head, list) {
	1158	+ if (pd->data->id == id)
	1159	+ return pd;
	1160	+ }
	1161	+
	1162	+ return NULL;
	1163	+}
	1164	+
	1165	+static const struct vop2_connector_if_data vop2_find_connector_if_data(struct vop2 vop2, int id)
	1166	+{
	1167	+ const struct vop2_connector_if_data *if_data;
	1168	+ int i;
	1169	+
	1170	+ for (i = 0; i < vop2->data->nr_conns; i++) {
	1171	+ if_data = &vop2->data->conn[i];
	1172	+ if (if_data->id == id)
	1173	+ return if_data;
	1174	+ }
	1175	+
	1176	+ return NULL;
	1177	+}
	1178	+
902	1179	static struct drm_crtc vop2_find_crtc_by_plane_mask(struct vop2 vop2, uint8_t phys_id)
903	1180	{
904	1181	struct vop2_video_port *vp;
..	..	@@ -907,10 +1184,28 @@
907	1184	for (i = 0; i < vop2->data->nr_vps; i++) {
908	1185	vp = &vop2->vps[i];
909	1186	if (vp->plane_mask & BIT(phys_id))
910		- return &vp->crtc;
	1187	+ return &vp->rockchip_crtc.crtc;
911	1188	}
912	1189
913	1190	return NULL;
	1191	+}
	1192	+
	1193	+static int vop2_clk_reset(struct reset_control *rstc)
	1194	+{
	1195	+ int ret;
	1196	+
	1197	+ if (!rstc)
	1198	+ return 0;
	1199	+
	1200	+ ret = reset_control_assert(rstc);
	1201	+ if (ret < 0)
	1202	+ DRM_WARN("failed to assert reset\n");
	1203	+ udelay(10);
	1204	+ ret = reset_control_deassert(rstc);
	1205	+ if (ret < 0)
	1206	+ DRM_WARN("failed to deassert reset\n");
	1207	+
	1208	+ return ret;
914	1209	}
915	1210
916	1211	static void vop2_load_hdr2sdr_table(struct vop2_video_port *vp)
..	..	@@ -991,8 +1286,23 @@
991	1286	static uint32_t vop2_read_vcnt(struct vop2_video_port *vp)
992	1287	{
993	1288	uint32_t offset = RK3568_SYS_STATUS0 + (vp->id << 2);
	1289	+ uint32_t vcnt0, vcnt1;
	1290	+ int i = 0;
994	1291
995		- return vop2_readl(vp->vop2, offset) >> 16;
	1292	+ for (i = 0; i < 10; i++) {
	1293	+ vcnt0 = vop2_readl(vp->vop2, offset) >> 16;
	1294	+ vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
	1295	+
	1296	+ if ((vcnt1 - vcnt0) <= 1)
	1297	+ break;
	1298	+ }
	1299	+
	1300	+ if (i == 10) {
	1301	+ DRM_DEV_ERROR(vp->vop2->dev, "read VP%d vcnt error: %d %d\n", vp->id, vcnt0, vcnt1);
	1302	+ vcnt1 = vop2_readl(vp->vop2, offset) >> 16;
	1303	+ }
	1304	+
	1305	+ return vcnt1;
996	1306	}
997	1307
998	1308	static void vop2_wait_for_irq_handler(struct drm_crtc *crtc)
..	..	@@ -1112,7 +1422,7 @@
1112	1422	done_bits &= ~BIT(vp->id);
1113	1423	vp_id = ffs(done_bits) - 1;
1114	1424	done_vp = &vop2->vps[vp_id];
1115		- adjusted_mode = &done_vp->crtc.state->adjusted_mode;
	1425	+ adjusted_mode = &done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1116	1426	vcnt = vop2_read_vcnt(done_vp);
1117	1427	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1118	1428	vcnt >>= 1;
..	..	@@ -1133,7 +1443,7 @@
1133	1443
1134	1444	first_vp_id = ffs(done_bits) - 1;
1135	1445	first_done_vp = &vop2->vps[first_vp_id];
1136		- first_mode = &first_done_vp->crtc.state->adjusted_mode;
	1446	+ first_mode = &first_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1137	1447	/* set last 1/8 frame time as safe section */
1138	1448	vrefresh = drm_mode_vrefresh(first_mode);
1139	1449	if (!vrefresh) {
..	..	@@ -1145,7 +1455,7 @@
1145	1455	done_bits &= ~BIT(first_vp_id);
1146	1456	second_vp_id = ffs(done_bits) - 1;
1147	1457	second_done_vp = &vop2->vps[second_vp_id];
1148		- second_mode = &second_done_vp->crtc.state->adjusted_mode;
	1458	+ second_mode = &second_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1149	1459	/* set last 1/8 frame time as safe section */
1150	1460	vrefresh = drm_mode_vrefresh(second_mode);
1151	1461	if (!vrefresh) {
..	..	@@ -1190,6 +1500,26 @@
1190	1500	return done_bits;
1191	1501	}
1192	1502
	1503	+static inline void rk3588_vop2_dsc_cfg_done(struct drm_crtc *crtc)
	1504	+{
	1505	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1506	+ struct vop2 *vop2 = vp->vop2;
	1507	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1508	+ struct vop2_dsc *dsc = &vop2->dscs[vcstate->dsc_id];
	1509	+
	1510	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	1511	+ dsc = &vop2->dscs[0];
	1512	+ if (vcstate->dsc_enable)
	1513	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1514	+ dsc = &vop2->dscs[1];
	1515	+ if (vcstate->dsc_enable)
	1516	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1517	+ } else {
	1518	+ if (vcstate->dsc_enable)
	1519	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1520	+ }
	1521	+}
	1522	+
1193	1523	static inline void rk3568_vop2_cfg_done(struct drm_crtc *crtc)
1194	1524	{
1195	1525	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -1224,6 +1554,9 @@
1224	1554	* This is rather low probability for miss some done bit.
1225	1555	*/
1226	1556	val \|= vop2_readl(vop2, RK3568_REG_CFG_DONE) & 0x7;
	1557	+
	1558	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
	1559	+
1227	1560	vop2_writel(vop2, 0, val);
1228	1561
1229	1562	/**
..	..	@@ -1240,10 +1573,16 @@
1240	1573	static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
1241	1574	{
1242	1575	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1576	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1577	+ const struct vop2_video_port_data *vp_data = &vp->vop2->data->vp[vp->id];
1243	1578	struct vop2 *vop2 = vp->vop2;
1244	1579	uint32_t val;
1245	1580
1246	1581	val = RK3568_VOP2_GLB_CFG_DONE_EN \| BIT(vp->id) \| (BIT(vp->id) << 16);
	1582	+ if (vcstate->splice_mode)
	1583	+ val \|= BIT(vp_data->splice_vp_id) \| (BIT(vp_data->splice_vp_id) << 16);
	1584	+
	1585	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
1247	1586
1248	1587	vop2_writel(vop2, 0, val);
1249	1588	}
..	..	@@ -1265,6 +1604,7 @@
1265	1604	} else {
1266	1605	vop2_writel(vop2, 0, val);
1267	1606	}
	1607	+
1268	1608	}
1269	1609
1270	1610	static inline void vop2_cfg_done(struct drm_crtc *crtc)
..	..	@@ -1276,6 +1616,178 @@
1276	1616	return rk3568_vop2_cfg_done(crtc);
1277	1617	else
1278	1618	return rk3588_vop2_cfg_done(crtc);
	1619	+}
	1620	+
	1621	+/*
	1622	+ * A PD can power off by vsync when it's module attached to
	1623	+ * a activated VP.
	1624	+ */
	1625	+static uint32_t vop2_power_domain_can_off_by_vsync(struct vop2_power_domain *pd)
	1626	+{
	1627	+ struct vop2 *vop2 = pd->vop2;
	1628	+
	1629	+ if (vop2->active_vp_mask & pd->vp_mask)
	1630	+ return true;
	1631	+ else
	1632	+ return false;
	1633	+}
	1634	+
	1635	+/*
	1636	+ * Read VOP internal power domain on/off status.
	1637	+ * We should query BISR_STS register in PMU for
	1638	+ * power up/down status when memory repair is enabled.
	1639	+ * Return value: 1 for power on, 0 for power off;
	1640	+ */
	1641	+static uint32_t vop2_power_domain_status(struct vop2_power_domain *pd)
	1642	+{
	1643	+ struct vop2 *vop2 = pd->vop2;
	1644	+
	1645	+ if (vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->bisr_en_status))
	1646	+ return vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->pmu_status);
	1647	+ else
	1648	+ return vop2_read_reg(vop2, 0, &pd->data->regs->status) ? 0 : 1;
	1649	+}
	1650	+
	1651	+static void vop2_wait_power_domain_off(struct vop2_power_domain *pd)
	1652	+{
	1653	+ struct vop2 *vop2 = pd->vop2;
	1654	+ int val;
	1655	+ int ret;
	1656	+
	1657	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, !val, 0, 50 * 1000);
	1658	+
	1659	+ if (ret)
	1660	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d off timeout power_ctrl: 0x%x\n",
	1661	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1662	+}
	1663	+
	1664	+static void vop2_wait_power_domain_on(struct vop2_power_domain *pd)
	1665	+{
	1666	+ struct vop2 *vop2 = pd->vop2;
	1667	+ int val;
	1668	+ int ret;
	1669	+
	1670	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, val, 0, 50 * 1000);
	1671	+ if (ret)
	1672	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d on timeout power_ctrl: 0x%x\n",
	1673	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1674	+}
	1675	+
	1676	+/*
	1677	+ * Power domain on take effect immediately
	1678	+ */
	1679	+static void vop2_power_domain_on(struct vop2_power_domain *pd)
	1680	+{
	1681	+ struct vop2 *vop2 = pd->vop2;
	1682	+
	1683	+ if (!pd->on) {
	1684	+ dev_dbg(vop2->dev, "pd%d on\n", ffs(pd->data->id) - 1);
	1685	+ vop2_wait_power_domain_off(pd);
	1686	+ VOP_MODULE_SET(vop2, pd->data, pd, 0);
	1687	+ vop2_wait_power_domain_on(pd);
	1688	+ pd->on = true;
	1689	+ }
	1690	+}
	1691	+
	1692	+/*
	1693	+ * Power domain off take effect by vsync.
	1694	+ */
	1695	+static void vop2_power_domain_off(struct vop2_power_domain *pd)
	1696	+{
	1697	+ struct vop2 *vop2 = pd->vop2;
	1698	+
	1699	+ dev_dbg(vop2->dev, "pd%d off\n", ffs(pd->data->id) - 1);
	1700	+ pd->on = false;
	1701	+ VOP_MODULE_SET(vop2, pd->data, pd, 1);
	1702	+}
	1703	+
	1704	+static void vop2_power_domain_get(struct vop2_power_domain *pd)
	1705	+{
	1706	+ if (pd->parent)
	1707	+ vop2_power_domain_get(pd->parent);
	1708	+
	1709	+ spin_lock(&pd->lock);
	1710	+ if (pd->ref_count == 0) {
	1711	+ if (pd->vop2->data->delayed_pd)
	1712	+ cancel_delayed_work(&pd->power_off_work);
	1713	+ vop2_power_domain_on(pd);
	1714	+ }
	1715	+ pd->ref_count++;
	1716	+ spin_unlock(&pd->lock);
	1717	+}
	1718	+
	1719	+static void vop2_power_domain_put(struct vop2_power_domain *pd)
	1720	+{
	1721	+ spin_lock(&pd->lock);
	1722	+
	1723	+ /*
	1724	+ * For a nested power domain(PD_Cluster0 is the parent of PD_CLuster1/2/3)
	1725	+ * the parent power domain must be enabled before child power domain
	1726	+ * is on.
	1727	+ *
	1728	+ * So we may met this condition: Cluster0 is not on a activated VP,
	1729	+ * but PD_Cluster0 must enabled as one of the child PD_CLUSTER1/2/3 is enabled.
	1730	+ * when all child PD is disabled, we want disable the parent
	1731	+ * PD(PD_CLUSTER0), but as module CLUSTER0 is not attcthed on a activated VP,
	1732	+ * the turn off operation(which is take effect by vsync) will never take effect.
	1733	+ * so we will see a "wait pd0 off timeout" log when we turn on PD_CLUSTER0 next time.
	1734	+ *
	1735	+ * So we have a check here
	1736	+ */
	1737	+ if (--pd->ref_count == 0 && vop2_power_domain_can_off_by_vsync(pd)) {
	1738	+ if (pd->vop2->data->delayed_pd)
	1739	+ schedule_delayed_work(&pd->power_off_work, msecs_to_jiffies(2500));
	1740	+ else
	1741	+ vop2_power_domain_off(pd);
	1742	+ }
	1743	+
	1744	+ spin_unlock(&pd->lock);
	1745	+ if (pd->parent)
	1746	+ vop2_power_domain_put(pd->parent);
	1747	+}
	1748	+
	1749	+/*
	1750	+ * Called if the pd ref_count reach 0 after 2.5
	1751	+ * seconds.
	1752	+ */
	1753	+static void vop2_power_domain_off_work(struct work_struct *work)
	1754	+{
	1755	+ struct vop2_power_domain *pd;
	1756	+
	1757	+ pd = container_of(to_delayed_work(work), struct vop2_power_domain, power_off_work);
	1758	+
	1759	+ spin_lock(&pd->lock);
	1760	+ if (pd->ref_count == 0)
	1761	+ vop2_power_domain_off(pd);
	1762	+ spin_unlock(&pd->lock);
	1763	+}
	1764	+
	1765	+static void vop2_win_enable(struct vop2_win *win)
	1766	+{
	1767	+ /*
	1768	+ * a win such as cursor update by async:
	1769	+ * first frame enable win pd, enable win, return without wait vsync
	1770	+ * second frame come, but the first frame may still not enabled
	1771	+ * in this case, the win pd is turn on by fist frame, so we don't
	1772	+ * need get pd again.
	1773	+ *
	1774	+ * another case:
	1775	+ * first frame: disable win, disable pd, return without wait vsync
	1776	+ * second frame come very soon, the previous win disable may still not
	1777	+ * take effect, but the pd is disable in progress, we should do pd_get
	1778	+ * at this situation.
	1779	+ *
	1780	+ * check the backup register for previous enable operation.
	1781	+ */
	1782	+ if (!VOP_WIN_GET_REG_BAK(win->vop2, win, enable)) {
	1783	+ if (win->pd) {
	1784	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1785	+ return;
	1786	+
	1787	+ vop2_power_domain_get(win->pd);
	1788	+ win->pd->vp_mask \|= win->vp_mask;
	1789	+ }
	1790	+ }
1279	1791	}
1280	1792
1281	1793	static void vop2_win_multi_area_disable(struct vop2_win *parent)
..	..	@@ -1291,31 +1803,63 @@
1291	1803	}
1292	1804	}
1293	1805
1294		-static void vop2_win_disable(struct vop2_win *win)
	1806	+static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win)
1295	1807	{
1296	1808	struct vop2 *vop2 = win->vop2;
1297	1809
1298		- VOP_WIN_SET(vop2, win, enable, 0);
1299		- if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
1300		- struct vop2_win *sub_win;
1301		- int i = 0;
1302		-
1303		- for (i = 0; i < vop2->registered_num_wins; i++) {
1304		- sub_win = &vop2->win[i];
1305		-
1306		- if ((sub_win->phys_id == win->phys_id) &&
1307		- (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
1308		- VOP_WIN_SET(vop2, sub_win, enable, 0);
1309		- }
1310		-
1311		- VOP_CLUSTER_SET(vop2, win, enable, 0);
	1810	+ /* Disable the right splice win */
	1811	+ if (win->splice_win && !skip_splice_win) {
	1812	+ vop2_win_disable(win->splice_win, false);
	1813	+ win->splice_win = NULL;
1312	1814	}
1313	1815
1314		- /*
1315		- * disable all other multi area win if we want disable area0 here
1316		- */
1317		- if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
1318		- vop2_win_multi_area_disable(win);
	1816	+ if (VOP_WIN_GET(vop2, win, enable) \|\| VOP_WIN_GET_REG_BAK(vop2, win, enable)) {
	1817	+ VOP_WIN_SET(vop2, win, enable, 0);
	1818	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
	1819	+ struct vop2_win *sub_win;
	1820	+ int i = 0;
	1821	+
	1822	+ for (i = 0; i < vop2->registered_num_wins; i++) {
	1823	+ sub_win = &vop2->win[i];
	1824	+
	1825	+ if ((sub_win->phys_id == win->phys_id) &&
	1826	+ (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
	1827	+ VOP_WIN_SET(vop2, sub_win, enable, 0);
	1828	+ }
	1829	+
	1830	+ VOP_CLUSTER_SET(vop2, win, enable, 0);
	1831	+ }
	1832	+
	1833	+ /*
	1834	+ * disable all other multi area win if we want disable area0 here
	1835	+ */
	1836	+ if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
	1837	+ vop2_win_multi_area_disable(win);
	1838	+
	1839	+ if (win->pd) {
	1840	+
	1841	+ /*
	1842	+ * Don't dynamic turn on/off PD_ESMART.
	1843	+ * (1) There is a design issue for PD_EMSART when attached
	1844	+ * on VP1/2/3, we found it will trigger POST_BUF_EMPTY irq at vp0
	1845	+ * in splice mode.
	1846	+ * (2) PD_ESMART will be closed at esmart layers attathed on VPs
	1847	+ * config done + FS, but different VP FS time is different, this
	1848	+ * maybe lead to PD_ESMART closed at wrong time and display error.
	1849	+ * (3) PD_ESMART power up maybe have 4 us delay, this will lead to POST_BUF_EMPTY.
	1850	+ */
	1851	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1852	+ return;
	1853	+
	1854	+ vop2_power_domain_put(win->pd);
	1855	+ win->pd->vp_mask &= ~win->vp_mask;
	1856	+ }
	1857	+ }
	1858	+
	1859	+ if (win->left_win && win->splice_mode_right) {
	1860	+ win->left_win = NULL;
	1861	+ win->splice_mode_right = false;
	1862	+ }
1319	1863	}
1320	1864
1321	1865	static inline void vop2_write_lut(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -1331,6 +1875,11 @@
1331	1875	static enum vop2_data_format vop2_convert_format(uint32_t format)
1332	1876	{
1333	1877	switch (format) {
	1878	+ case DRM_FORMAT_XRGB2101010:
	1879	+ case DRM_FORMAT_ARGB2101010:
	1880	+ case DRM_FORMAT_XBGR2101010:
	1881	+ case DRM_FORMAT_ABGR2101010:
	1882	+ return VOP2_FMT_XRGB101010;
1334	1883	case DRM_FORMAT_XRGB8888:
1335	1884	case DRM_FORMAT_ARGB8888:
1336	1885	case DRM_FORMAT_XBGR8888:
..	..	@@ -1343,16 +1892,22 @@
1343	1892	case DRM_FORMAT_BGR565:
1344	1893	return VOP2_FMT_RGB565;
1345	1894	case DRM_FORMAT_NV12:
	1895	+ case DRM_FORMAT_NV21:
	1896	+ case DRM_FORMAT_YUV420_8BIT:
1346	1897	return VOP2_FMT_YUV420SP;
1347		- case DRM_FORMAT_NV12_10:
	1898	+ case DRM_FORMAT_NV15:
	1899	+ case DRM_FORMAT_YUV420_10BIT:
1348	1900	return VOP2_FMT_YUV420SP_10;
1349	1901	case DRM_FORMAT_NV16:
	1902	+ case DRM_FORMAT_NV61:
1350	1903	return VOP2_FMT_YUV422SP;
1351		- case DRM_FORMAT_NV16_10:
	1904	+ case DRM_FORMAT_NV20:
	1905	+ case DRM_FORMAT_Y210:
1352	1906	return VOP2_FMT_YUV422SP_10;
1353	1907	case DRM_FORMAT_NV24:
	1908	+ case DRM_FORMAT_NV42:
1354	1909	return VOP2_FMT_YUV444SP;
1355		- case DRM_FORMAT_NV24_10:
	1910	+ case DRM_FORMAT_NV30:
1356	1911	return VOP2_FMT_YUV444SP_10;
1357	1912	case DRM_FORMAT_YUYV:
1358	1913	case DRM_FORMAT_YVYU:
..	..	@@ -1369,6 +1924,11 @@
1369	1924	static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format)
1370	1925	{
1371	1926	switch (format) {
	1927	+ case DRM_FORMAT_XRGB2101010:
	1928	+ case DRM_FORMAT_ARGB2101010:
	1929	+ case DRM_FORMAT_XBGR2101010:
	1930	+ case DRM_FORMAT_ABGR2101010:
	1931	+ return VOP2_AFBC_FMT_ARGB2101010;
1372	1932	case DRM_FORMAT_XRGB8888:
1373	1933	case DRM_FORMAT_ARGB8888:
1374	1934	case DRM_FORMAT_XBGR8888:
..	..	@@ -1380,14 +1940,16 @@
1380	1940	case DRM_FORMAT_RGB565:
1381	1941	case DRM_FORMAT_BGR565:
1382	1942	return VOP2_AFBC_FMT_RGB565;
1383		- case DRM_FORMAT_NV12:
	1943	+ case DRM_FORMAT_YUV420_8BIT:
1384	1944	return VOP2_AFBC_FMT_YUV420;
1385		- case DRM_FORMAT_NV12_10:
	1945	+ case DRM_FORMAT_YUV420_10BIT:
1386	1946	return VOP2_AFBC_FMT_YUV420_10BIT;
1387		- case DRM_FORMAT_NV16:
	1947	+ case DRM_FORMAT_YVYU:
1388	1948	case DRM_FORMAT_YUYV:
	1949	+ case DRM_FORMAT_VYUY:
	1950	+ case DRM_FORMAT_UYVY:
1389	1951	return VOP2_AFBC_FMT_YUV422;
1390		- case DRM_FORMAT_NV16_10:
	1952	+ case DRM_FORMAT_Y210:
1391	1953	return VOP2_AFBC_FMT_YUV422_10BIT;
1392	1954
1393	1955	/* either of the below should not be reachable */
..	..	@@ -1411,11 +1973,11 @@
1411	1973	case DRM_FORMAT_NV24:
1412	1974	case DRM_FORMAT_NV42:
1413	1975	return VOP2_TILED_8X8_FMT_YUV444SP;
1414		- case DRM_FORMAT_NV12_10:
	1976	+ case DRM_FORMAT_NV15:
1415	1977	return VOP2_TILED_8X8_FMT_YUV420SP_10;
1416		- case DRM_FORMAT_NV16_10:
	1978	+ case DRM_FORMAT_NV20:
1417	1979	return VOP2_TILED_8X8_FMT_YUV422SP_10;
1418		- case DRM_FORMAT_NV24_10:
	1980	+ case DRM_FORMAT_NV30:
1419	1981	return VOP2_TILED_8X8_FMT_YUV444SP_10;
1420	1982	default:
1421	1983	DRM_WARN_ONCE("unsupported tiled format[%08x]\n", format);
..	..	@@ -1440,13 +2002,13 @@
1440	2002	case DRM_FORMAT_NV42:
1441	2003	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1442	2004	VOP3_TILED_8X8_FMT_YUV444SP : VOP3_TILED_4X4_FMT_YUV444SP;
1443		- case DRM_FORMAT_NV12_10:
	2005	+ case DRM_FORMAT_NV15:
1444	2006	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1445	2007	VOP3_TILED_8X8_FMT_YUV420SP_10 : VOP3_TILED_4X4_FMT_YUV420SP_10;
1446		- case DRM_FORMAT_NV16_10:
	2008	+ case DRM_FORMAT_NV20:
1447	2009	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1448	2010	VOP3_TILED_8X8_FMT_YUV422SP_10 : VOP3_TILED_4X4_FMT_YUV422SP_10;
1449		- case DRM_FORMAT_NV24_10:
	2011	+ case DRM_FORMAT_NV30:
1450	2012	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1451	2013	VOP3_TILED_8X8_FMT_YUV444SP_10 : VOP3_TILED_4X4_FMT_YUV444SP_10;
1452	2014	default:
..	..	@@ -1485,6 +2047,8 @@
1485	2047	static bool vop2_win_rb_swap(uint32_t format)
1486	2048	{
1487	2049	switch (format) {
	2050	+ case DRM_FORMAT_XBGR2101010:
	2051	+ case DRM_FORMAT_ABGR2101010:
1488	2052	case DRM_FORMAT_XBGR8888:
1489	2053	case DRM_FORMAT_ABGR8888:
1490	2054	case DRM_FORMAT_BGR888:
..	..	@@ -1499,7 +2063,7 @@
1499	2063	{
1500	2064	switch (format) {
1501	2065	case DRM_FORMAT_NV24:
1502		- case DRM_FORMAT_NV24_10:
	2066	+ case DRM_FORMAT_NV30:
1503	2067	return true;
1504	2068	default:
1505	2069	return false;
..	..	@@ -1512,8 +2076,9 @@
1512	2076	case DRM_FORMAT_NV12:
1513	2077	case DRM_FORMAT_NV16:
1514	2078	case DRM_FORMAT_YUYV:
1515		- case DRM_FORMAT_NV12_10:
1516		- case DRM_FORMAT_NV16_10:
	2079	+ case DRM_FORMAT_Y210:
	2080	+ case DRM_FORMAT_YUV420_8BIT:
	2081	+ case DRM_FORMAT_YUV420_10BIT:
1517	2082	return true;
1518	2083	default:
1519	2084	return false;
..	..	@@ -1526,9 +2091,9 @@
1526	2091	case DRM_FORMAT_NV12:
1527	2092	case DRM_FORMAT_NV16:
1528	2093	case DRM_FORMAT_NV24:
1529		- case DRM_FORMAT_NV12_10:
1530		- case DRM_FORMAT_NV16_10:
1531		- case DRM_FORMAT_NV24_10:
	2094	+ case DRM_FORMAT_NV15:
	2095	+ case DRM_FORMAT_NV20:
	2096	+ case DRM_FORMAT_NV30:
1532	2097	case DRM_FORMAT_YUYV:
1533	2098	case DRM_FORMAT_UYVY:
1534	2099	return true;
..	..	@@ -1572,6 +2137,19 @@
1572	2137	return false;
1573	2138	}
1574	2139
	2140	+static bool vop3_output_rb_swap(uint32_t bus_format, uint32_t output_mode)
	2141	+{
	2142	+ /*
	2143	+ * The default component order of serial rgb3x8 formats
	2144	+ * is BGR. So it is needed to enable RB swap.
	2145	+ */
	2146	+ if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 \|\|
	2147	+ bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
	2148	+ return true;
	2149	+ else
	2150	+ return false;
	2151	+}
	2152	+
1575	2153	static bool vop2_output_yc_swap(uint32_t bus_format)
1576	2154	{
1577	2155	switch (bus_format) {
..	..	@@ -1590,6 +2168,7 @@
1590	2168	switch (bus_format) {
1591	2169	case MEDIA_BUS_FMT_YUV8_1X24:
1592	2170	case MEDIA_BUS_FMT_YUV10_1X30:
	2171	+ case MEDIA_BUS_FMT_YUYV10_1X20:
1593	2172	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1594	2173	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1595	2174	case MEDIA_BUS_FMT_YUYV8_2X8:
..	..	@@ -1685,6 +2264,15 @@
1685	2264	return (win->feature & WIN_FEATURE_CLUSTER_SUB);
1686	2265	}
1687	2266
	2267	+static inline bool vop2_has_feature(struct vop2 *vop2, uint64_t feature)
	2268	+{
	2269	+ return (vop2->data->feature & feature);
	2270	+}
	2271	+
	2272	+/*
	2273	+ * 0: Full mode, 16 lines for one tail
	2274	+ * 1: half block mode
	2275	+ */
1688	2276	static int vop2_afbc_half_block_enable(struct vop2_plane_state *vpstate)
1689	2277	{
1690	2278	if (vpstate->rotate_270_en \|\| vpstate->rotate_90_en)
..	..	@@ -1693,11 +2281,15 @@
1693	2281	return 1;
1694	2282	}
1695	2283
1696		-static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate)
	2284	+/*
	2285	+ * @xoffset: the src x offset of the right win in splice mode, other wise it
	2286	+ * must be zero.
	2287	+ */
	2288	+static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate, int xoffset)
1697	2289	{
1698	2290	struct drm_rect *src = &vpstate->src;
1699	2291	struct drm_framebuffer *fb = vpstate->base.fb;
1700		- uint32_t bpp = fb->format->bpp[0];
	2292	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
1701	2293	uint32_t vir_width = (fb->pitches[0] << 3) / (bpp ? bpp : 1);
1702	2294	uint32_t width = drm_rect_width(src) >> 16;
1703	2295	uint32_t height = drm_rect_height(src) >> 16;
..	..	@@ -1713,6 +2305,7 @@
1713	2305	uint8_t top_crop_line_num = 0;
1714	2306	uint8_t bottom_crop_line_num = 0;
1715	2307
	2308	+ act_xoffset += xoffset;
1716	2309	/* 16 pixel align */
1717	2310	if (height & 0xf)
1718	2311	align16_crop = 16 - (height & 0xf);
..	..	@@ -1864,7 +2457,7 @@
1864	2457	#define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \
1865	2458	(fac * (dst - 1) >> 16 < (src - 1))
1866	2459	#define VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac) \
1867		- (fac * (dst - 1) >> 16 <= (src - 1))
	2460	+ (fac * (dst - 1) >> 16 < (src - 1))
1868	2461
1869	2462	static uint16_t vop2_scale_factor(enum scale_mode mode,
1870	2463	int32_t filter_mode,
..	..	@@ -1956,12 +2549,12 @@
1956	2549	{
1957	2550	const struct vop2_data *vop2_data = vop2->data;
1958	2551	const struct vop2_win_data *win_data = &vop2_data->win[win->win_id];
1959		- const struct drm_format_info *info;
1960	2552	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
1961	2553	struct drm_framebuffer *fb = pstate->fb;
1962	2554	uint32_t pixel_format = fb->format->format;
1963		- int hsub = drm_format_horz_chroma_subsampling(pixel_format);
1964		- int vsub = drm_format_vert_chroma_subsampling(pixel_format);
	2555	+ const struct drm_format_info *info = drm_format_info(pixel_format);
	2556	+ uint8_t hsub = info->hsub;
	2557	+ uint8_t vsub = info->vsub;
1965	2558	uint16_t cbcr_src_w = src_w / hsub;
1966	2559	uint16_t cbcr_src_h = src_h / vsub;
1967	2560	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
..	..	@@ -1970,8 +2563,6 @@
1970	2563	uint8_t xgt2 = 0, xgt4 = 0;
1971	2564	uint8_t ygt2 = 0, ygt4 = 0;
1972	2565	uint32_t val;
1973		-
1974		- info = drm_format_info(pixel_format);
1975	2566
1976	2567	if (is_vop3(vop2)) {
1977	2568	if (src_w >= (4 * dst_w)) {
..	..	@@ -1983,12 +2574,30 @@
1983	2574	}
1984	2575	}
1985	2576
1986		- if (src_h >= (4 * dst_h)) {
1987		- ygt4 = 1;
1988		- src_h >>= 2;
1989		- } else if (src_h >= (2 * dst_h)) {
1990		- ygt2 = 1;
1991		- src_h >>= 1;
	2577	+ /**
	2578	+ * The rk3528 is processed as 2 pixel/cycle,
	2579	+ * so ygt2/ygt4 needs to be triggered in advance to improve performance
	2580	+ * when src_w is bigger than 1920.
	2581	+ * dst_h / src_h is at [1, 0.65) ygt2=0; ygt4=0;
	2582	+ * dst_h / src_h is at [0.65, 0.35) ygt2=1; ygt4=0;
	2583	+ * dst_h / src_h is at [0.35, 0) ygt2=0; ygt4=1;
	2584	+ */
	2585	+ if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) {
	2586	+ if (src_h >= (100 * dst_h / 35)) {
	2587	+ ygt4 = 1;
	2588	+ src_h >>= 2;
	2589	+ } else if ((src_h >= 100 * dst_h / 65) && (src_h < 100 * dst_h / 35)) {
	2590	+ ygt2 = 1;
	2591	+ src_h >>= 1;
	2592	+ }
	2593	+ } else {
	2594	+ if (src_h >= (4 * dst_h)) {
	2595	+ ygt4 = 1;
	2596	+ src_h >>= 2;
	2597	+ } else if (src_h >= (2 * dst_h)) {
	2598	+ ygt2 = 1;
	2599	+ src_h >>= 1;
	2600	+ }
1992	2601	}
1993	2602
1994	2603	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
..	..	@@ -2065,10 +2674,17 @@
2065	2674	if (!is_vop3(vop2) \|\|
2066	2675	(!vpstate->afbc_en && !vpstate->tiled_en) \|\|
2067	2676	win_data->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) {
2068		- if (cbcr_src_h >= (4 * dst_h))
2069		- ygt4 = 1;
2070		- else if (cbcr_src_h >= (2 * dst_h))
2071		- ygt2 = 1;
	2677	+ if (vop2->version == VOP_VERSION_RK3528 && src_w > 1920) {
	2678	+ if (cbcr_src_h >= (100 * dst_h / 35))
	2679	+ ygt4 = 1;
	2680	+ else if ((cbcr_src_h >= 100 * dst_h / 65) && (cbcr_src_h < 100 * dst_h / 35))
	2681	+ ygt2 = 1;
	2682	+ } else {
	2683	+ if (cbcr_src_h >= (4 * dst_h))
	2684	+ ygt4 = 1;
	2685	+ else if (cbcr_src_h >= (2 * dst_h))
	2686	+ ygt2 = 1;
	2687	+ }
2072	2688
2073	2689	if (ygt4)
2074	2690	cbcr_src_h >>= 2;
..	..	@@ -2166,7 +2782,7 @@
2166	2782	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
2167	2783	win = vop2_find_win_by_phys_id(vop2, phys_id);
2168	2784	need_wait_win_disabled \|= VOP_WIN_GET(vop2, win, enable);
2169		- vop2_win_disable(win);
	2785	+ vop2_win_disable(win, false);
2170	2786	}
2171	2787
2172	2788	if (need_wait_win_disabled) {
..	..	@@ -2215,7 +2831,7 @@
2215	2831	struct vop2_plane_state *vpstate)
2216	2832	{
2217	2833	struct drm_plane_state *pstate = &vpstate->base;
2218		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
	2834	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->rockchip_crtc.crtc.state);
2219	2835	int is_input_yuv = pstate->fb->format->is_yuv;
2220	2836	int is_output_yuv = vcstate->yuv_overlay;
2221	2837	int input_csc = vpstate->color_space;
..	..	@@ -2230,29 +2846,49 @@
2230	2846	vpstate->r2y_en = 0;
2231	2847	vpstate->csc_mode = 0;
2232	2848
2233		- /* hdr2sdr and sdr2hdr will do csc itself */
2234		- if (vpstate->hdr2sdr_en) {
2235		- /*
2236		- * This is hdr2sdr enabled plane
2237		- * If it's RGB layer do hdr2sdr, we need to do r2y before send to hdr2sdr,
2238		- * because hdr2sdr only support yuv input.
2239		- */
2240		- if (!is_input_yuv) {
2241		- vpstate->r2y_en = 1;
2242		- vpstate->csc_mode = vop2_convert_csc_mode(output_csc, CSC_10BIT_DEPTH);
	2849	+ if (is_vop3(vp->vop2)) {
	2850	+ if (vpstate->hdr_in) {
	2851	+ if (is_input_yuv) {
	2852	+ vpstate->y2r_en = 1;
	2853	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2854	+ CSC_13BIT_DEPTH);
	2855	+ }
	2856	+ return;
	2857	+ } else if (vp->sdr2hdr_en) {
	2858	+ if (is_input_yuv) {
	2859	+ vpstate->y2r_en = 1;
	2860	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2861	+ csc_y2r_bit_depth);
	2862	+ }
	2863	+ return;
2243	2864	}
2244		- return;
2245		- } else if (!vpstate->hdr_in && vp->sdr2hdr_en) {
2246		- /*
2247		- * This is sdr2hdr enabled plane
2248		- * If it's YUV layer do sdr2hdr, we need to do y2r before send to sdr2hdr,
2249		- * because sdr2hdr only support rgb input.
2250		- */
2251		- if (is_input_yuv) {
2252		- vpstate->y2r_en = 1;
2253		- vpstate->csc_mode = vop2_convert_csc_mode(input_csc, csc_y2r_bit_depth);
	2865	+ } else {
	2866	+ /* hdr2sdr and sdr2hdr will do csc itself */
	2867	+ if (vpstate->hdr2sdr_en) {
	2868	+ /*
	2869	+ * This is hdr2sdr enabled plane
	2870	+ * If it's RGB layer do hdr2sdr, we need to do r2y before send to hdr2sdr,
	2871	+ * because hdr2sdr only support yuv input.
	2872	+ */
	2873	+ if (!is_input_yuv) {
	2874	+ vpstate->r2y_en = 1;
	2875	+ vpstate->csc_mode = vop2_convert_csc_mode(output_csc,
	2876	+ CSC_10BIT_DEPTH);
	2877	+ }
	2878	+ return;
	2879	+ } else if (!vpstate->hdr_in && vp->sdr2hdr_en) {
	2880	+ /*
	2881	+ * This is sdr2hdr enabled plane
	2882	+ * If it's YUV layer do sdr2hdr, we need to do y2r before send to sdr2hdr,
	2883	+ * because sdr2hdr only support rgb input.
	2884	+ */
	2885	+ if (is_input_yuv) {
	2886	+ vpstate->y2r_en = 1;
	2887	+ vpstate->csc_mode = vop2_convert_csc_mode(input_csc,
	2888	+ csc_y2r_bit_depth);
	2889	+ }
	2890	+ return;
2254	2891	}
2255		- return;
2256	2892	}
2257	2893
2258	2894	if (is_input_yuv && !is_output_yuv) {
..	..	@@ -2380,8 +3016,14 @@
2380	3016	if (ret < 0)
2381	3017	goto err_disable_hclk;
2382	3018
	3019	+ ret = clk_enable(vop2->pclk);
	3020	+ if (ret < 0)
	3021	+ goto err_disable_aclk;
	3022	+
2383	3023	return 0;
2384	3024
	3025	+err_disable_aclk:
	3026	+ clk_disable(vop2->aclk);
2385	3027	err_disable_hclk:
2386	3028	clk_disable(vop2->hclk);
2387	3029	return ret;
..	..	@@ -2389,6 +3031,7 @@
2389	3031
2390	3032	static void vop2_core_clks_disable(struct vop2 *vop2)
2391	3033	{
	3034	+ clk_disable(vop2->pclk);
2392	3035	clk_disable(vop2->aclk);
2393	3036	clk_disable(vop2->hclk);
2394	3037	}
..	..	@@ -2499,6 +3142,18 @@
2499	3142	return MODE_OK;
2500	3143	}
2501	3144
	3145	+static inline bool
	3146	+vop2_wb_connector_changed_only(struct drm_crtc_state cstate, struct drm_connector conn)
	3147	+{
	3148	+ struct drm_crtc_state *old_state;
	3149	+ u32 changed_connectors;
	3150	+
	3151	+ old_state = drm_atomic_get_old_crtc_state(cstate->state, cstate->crtc);
	3152	+ changed_connectors = cstate->connector_mask ^ old_state->connector_mask;
	3153	+
	3154	+ return BIT(drm_connector_index(conn)) == changed_connectors;
	3155	+}
	3156	+
2502	3157	static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder,
2503	3158	struct drm_crtc_state *cstate,
2504	3159	struct drm_connector_state *conn_state)
..	..	@@ -2507,7 +3162,18 @@
2507	3162	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
2508	3163	struct vop2_video_port *vp = to_vop2_video_port(cstate->crtc);
2509	3164	struct drm_framebuffer *fb;
	3165	+ struct drm_gem_object obj, uv_obj;
	3166	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
2510	3167
	3168	+ /*
	3169	+ * No need for a full modested when the only connector changed is the
	3170	+ * writeback connector.
	3171	+ */
	3172	+ if (cstate->connectors_changed &&
	3173	+ vop2_wb_connector_changed_only(cstate, conn_state->connector)) {
	3174	+ cstate->connectors_changed = false;
	3175	+ DRM_DEBUG("VP%d force change connectors_changed to false when only wb changed\n", vp->id);
	3176	+ }
2511	3177	if (!conn_state->writeback_job \|\| !conn_state->writeback_job->fb)
2512	3178	return 0;
2513	3179
..	..	@@ -2520,7 +3186,7 @@
2520	3186	}
2521	3187
2522	3188	if ((fb->width > cstate->mode.hdisplay) \|\|
2523		- ((fb->height != cstate->mode.vdisplay) &&
	3189	+ ((fb->height < cstate->mode.vdisplay) &&
2524	3190	(fb->height != (cstate->mode.vdisplay >> 1)))) {
2525	3191	DRM_DEBUG_KMS("Invalid framebuffer size %ux%u, Only support x scale down and 1/2 y scale down\n",
2526	3192	fb->width, fb->height);
..	..	@@ -2528,7 +3194,7 @@
2528	3194	}
2529	3195
2530	3196	wb_state->scale_x_factor = vop2_scale_factor(SCALE_DOWN, VOP2_SCALE_DOWN_BIL,
2531		- cstate->mode.hdisplay, fb->width);
	3197	+ cstate->mode.hdisplay, fb->width);
2532	3198	wb_state->scale_x_en = (fb->width < cstate->mode.hdisplay) ? 1 : 0;
2533	3199	wb_state->scale_y_en = (fb->height < cstate->mode.vdisplay) ? 1 : 0;
2534	3200
..	..	@@ -2543,15 +3209,15 @@
2543	3209	}
2544	3210
2545	3211	wb_state->vp_id = vp->id;
2546		- wb_state->yrgb_addr = rockchip_fb_get_dma_addr(fb, 0);
2547		- /*
2548		- * uv address must follow yrgb address without gap.
2549		- * the fb->offsets is include stride, so we should
2550		- * not use it.
2551		- */
	3212	+ obj = fb->obj[0];
	3213	+ rk_obj = to_rockchip_obj(obj);
	3214	+ wb_state->yrgb_addr = rk_obj->dma_addr + fb->offsets[0];
	3215	+
2552	3216	if (fb->format->is_yuv) {
2553		- wb_state->uv_addr = wb_state->yrgb_addr;
2554		- wb_state->uv_addr += DIV_ROUND_UP(fb->width * fb->format->bpp[0], 8) * fb->height;
	3217	+ uv_obj = fb->obj[1];
	3218	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	3219	+
	3220	+ wb_state->uv_addr = rk_uv_obj->dma_addr + fb->offsets[1];
2555	3221	}
2556	3222
2557	3223	return 0;
..	..	@@ -2641,10 +3307,12 @@
2641	3307	if (conn_state->writeback_job && conn_state->writeback_job->fb) {
2642	3308	struct drm_framebuffer *fb = conn_state->writeback_job->fb;
2643	3309
2644		- DRM_DEV_DEBUG(vop2->dev, "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
2645		- fb->width, fb->height, wb_state->format, fb->pitches[0], &wb_state->yrgb_addr);
	3310	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_WB,
	3311	+ "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
	3312	+ fb->width, fb->height, wb_state->format,
	3313	+ fb->pitches[0], &wb_state->yrgb_addr);
2646	3314
2647		- drm_writeback_queue_job(wb_conn, conn_state->writeback_job);
	3315	+ drm_writeback_queue_job(wb_conn, conn_state);
2648	3316	conn_state->writeback_job = NULL;
2649	3317
2650	3318	spin_lock_irqsave(&wb->job_lock, flags);
..	..	@@ -2657,7 +3325,7 @@
2657	3325	fifo_throd = fb->pitches[0] >> 4;
2658	3326	if (fifo_throd >= vop2->data->wb->fifo_depth)
2659	3327	fifo_throd = vop2->data->wb->fifo_depth;
2660		- r2y = fb->format->is_yuv && (!is_yuv_output(vcstate->bus_format));
	3328	+ r2y = !vcstate->yuv_overlay && fb->format->is_yuv;
2661	3329
2662	3330	/*
2663	3331	* the vp_id register config done immediately
..	..	@@ -2673,6 +3341,7 @@
2673	3341	VOP_MODULE_SET(vop2, wb, r2y_en, r2y);
2674	3342	VOP_MODULE_SET(vop2, wb, enable, 1);
2675	3343	vop2_wb_irqs_enable(vop2);
	3344	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 1);
2676	3345	}
2677	3346	}
2678	3347
..	..	@@ -2697,6 +3366,7 @@
2697	3366
2698	3367	return;
2699	3368	}
	3369	+
2700	3370	spin_lock(&vop2->reg_lock);
2701	3371	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 0);
2702	3372	vop2_cfg_done(crtc);
..	..	@@ -2712,7 +3382,7 @@
2712	3382	spin_lock(&vop2->reg_lock);
2713	3383
2714	3384	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2715		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
	3385	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2716	3386	vop2_cfg_done(crtc);
2717	3387	vp->gamma_lut_active = true;
2718	3388
..	..	@@ -2733,7 +3403,7 @@
2733	3403	vop2_write_lut(vop2, i << 2, lut[i]);
2734	3404
2735	3405	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2736		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
	3406	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2737	3407	vp->gamma_lut_active = true;
2738	3408
2739	3409	spin_unlock(&vop2->reg_lock);
..	..	@@ -2753,7 +3423,13 @@
2753	3423	if (vop2->version == VOP_VERSION_RK3568) {
2754	3424	rk3568_crtc_load_lut(crtc);
2755	3425	} else {
2756		- rk3588_crtc_load_lut(crtc, vp->lut);
	3426	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	3427	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3428	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3429	+
	3430	+ rk3588_crtc_load_lut(&vp->rockchip_crtc.crtc, vp->lut);
	3431	+ if (vcstate->splice_mode)
	3432	+ rk3588_crtc_load_lut(&splice_vp->rockchip_crtc.crtc, vp->lut);
2757	3433	vop2_cfg_done(crtc);
2758	3434	}
2759	3435	/*
..	..	@@ -2848,9 +3524,11 @@
2848	3524	return 0;
2849	3525	}
2850	3526
	3527	+#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
2851	3528	static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
2852	3529	struct drm_crtc_state *old_state)
2853	3530	{
	3531	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
2854	3532	struct vop2_video_port *vp = to_vop2_video_port(crtc);
2855	3533	struct rockchip_drm_private *private = crtc->dev->dev_private;
2856	3534	struct drm_color_lut *lut = vp->cubic_lut;
..	..	@@ -2901,13 +3579,61 @@
2901	3579	*cubic_lut_kvaddr = 0;
2902	3580	}
2903	3581
	3582	+ VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid);
2904	3583	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
2905	3584	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 1);
2906	3585	VOP_MODULE_SET(vop2, vp, cubic_lut_en, 1);
2907	3586	VOP_CTRL_SET(vop2, lut_dma_en, 1);
2908	3587
	3588	+ if (vcstate->splice_mode) {
	3589	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3590	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3591	+
	3592	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_mst, cubic_lut_mst);
	3593	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_update_en, 1);
	3594	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_en, 1);
	3595	+ }
	3596	+
2909	3597	return 0;
2910	3598	}
	3599	+
	3600	+static void drm_crtc_enable_cubic_lut(struct drm_crtc *crtc, unsigned int cubic_lut_size)
	3601	+{
	3602	+ struct drm_device *dev = crtc->dev;
	3603	+ struct drm_mode_config *config = &dev->mode_config;
	3604	+
	3605	+ if (cubic_lut_size) {
	3606	+ drm_object_attach_property(&crtc->base,
	3607	+ config->cubic_lut_property, 0);
	3608	+ drm_object_attach_property(&crtc->base,
	3609	+ config->cubic_lut_size_property,
	3610	+ cubic_lut_size);
	3611	+ }
	3612	+}
	3613	+
	3614	+static void vop2_cubic_lut_init(struct vop2 *vop2)
	3615	+{
	3616	+ const struct vop2_data *vop2_data = vop2->data;
	3617	+ const struct vop2_video_port_data *vp_data;
	3618	+ struct vop2_video_port *vp;
	3619	+ struct drm_crtc *crtc;
	3620	+ int i;
	3621	+
	3622	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	3623	+ vp = &vop2->vps[i];
	3624	+ crtc = &vp->rockchip_crtc.crtc;
	3625	+ if (!crtc->dev)
	3626	+ continue;
	3627	+ vp_data = &vop2_data->vp[vp->id];
	3628	+ vp->cubic_lut_len = vp_data->cubic_lut_len;
	3629	+
	3630	+ if (vp->cubic_lut_len)
	3631	+ drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
	3632	+ }
	3633	+}
	3634	+#else
	3635	+static void vop2_cubic_lut_init(struct vop2 *vop2) { }
	3636	+#endif
2911	3637
2912	3638	static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
2913	3639	{
..	..	@@ -2925,7 +3651,15 @@
2925	3651	goto err;
2926	3652	}
2927	3653
	3654	+ ret = clk_prepare_enable(vop2->pclk);
	3655	+ if (ret < 0) {
	3656	+ dev_err(vop2->dev, "failed to enable pclk - %d\n", ret);
	3657	+ goto err1;
	3658	+ }
	3659	+
2928	3660	return 0;
	3661	+err1:
	3662	+ clk_disable_unprepare(vop2->aclk);
2929	3663	err:
2930	3664	clk_disable_unprepare(vop2->hclk);
2931	3665
..	..	@@ -2963,25 +3697,16 @@
2963	3697	*/
2964	3698	static void vop3_layer_map_initial(struct vop2 *vop2, uint32_t current_vp_id)
2965	3699	{
2966		- struct vop2_video_port *vp;
2967		- struct vop2_win *win;
2968		- unsigned long win_mask;
2969	3700	uint16_t vp_id;
2970		- int phys_id;
2971		- int i;
	3701	+ struct drm_plane *plane = NULL;
2972	3702
2973		- for (i = 0; i < vop2->data->nr_vps; i++) {
2974		- vp_id = i;
2975		- vp = &vop2->vps[vp_id];
2976		- vp->win_mask = vp->plane_mask;
2977		- win_mask = vp->win_mask;
2978		- for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
2979		- win = vop2_find_win_by_phys_id(vop2, phys_id);
2980		- VOP_CTRL_SET(vop2, win_vp_id[phys_id], vp_id);
2981		- win->vp_mask = BIT(vp_id);
2982		- win->old_vp_mask = win->vp_mask;
2983		- DRM_DEV_DEBUG(vop2->dev, "%s attach to vp%d\n", win->name, vp_id);
2984		- }
	3703	+ drm_for_each_plane(plane, vop2->drm_dev) {
	3704	+ struct vop2_win *win = to_vop2_win(plane);
	3705	+
	3706	+ vp_id = VOP_CTRL_GET(vop2, win_vp_id[win->phys_id]);
	3707	+ win->vp_mask = BIT(vp_id);
	3708	+ win->old_vp_mask = win->vp_mask;
	3709	+ vop2->vps[vp_id].win_mask \|= BIT(win->phys_id);
2985	3710	}
2986	3711	}
2987	3712
..	..	@@ -3051,6 +3776,18 @@
3051	3776
3052	3777	}
3053	3778
	3779	+static void rk3588_vop2_regsbak(struct vop2 *vop2)
	3780	+{
	3781	+ uint32_t *base = vop2->regs;
	3782	+ int i;
	3783	+
	3784	+ /*
	3785	+ * No need to backup DSC/GAMMA_LUT/BPP_LUT/MMU
	3786	+ */
	3787	+ for (i = 0; i < (0x2000 >> 2); i++)
	3788	+ vop2->regsbak[i] = base[i];
	3789	+}
	3790	+
3054	3791	static void vop2_initial(struct drm_crtc *crtc)
3055	3792	{
3056	3793	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3075,14 +3812,29 @@
3075	3812	if (vop2_soc_is_rk3566())
3076	3813	VOP_CTRL_SET(vop2, otp_en, 1);
3077	3814
3078		- memcpy(vop2->regsbak, vop2->regs, vop2->len);
	3815	+ /*
	3816	+ * rk3588 don't support access mmio by memcpy
	3817	+ */
	3818	+ if (vop2->version == VOP_VERSION_RK3588)
	3819	+ rk3588_vop2_regsbak(vop2);
	3820	+ else
	3821	+ memcpy(vop2->regsbak, vop2->regs, vop2->len);
3079	3822
3080	3823	VOP_MODULE_SET(vop2, wb, axi_yrgb_id, 0xd);
3081	3824	VOP_MODULE_SET(vop2, wb, axi_uv_id, 0xe);
3082	3825	vop2_wb_cfg_done(vp);
3083	3826
3084		- if (is_vop3(vop2))
3085		- VOP_CTRL_SET(vop2, esmart_lb_mode, vop2->data->esmart_lb_mode);
	3827	+ if (is_vop3(vop2)) {
	3828	+ VOP_CTRL_SET(vop2, dsp_vs_t_sel, 0);
	3829	+ VOP_CTRL_SET(vop2, esmart_lb_mode, vop2->esmart_lb_mode);
	3830	+ }
	3831	+
	3832	+ /*
	3833	+ * This is unused and error init value for rk3528/rk3562 vp1, if less of this config,
	3834	+ * vp1 can't display normally.
	3835	+ */
	3836	+ if (vop2->version == VOP_VERSION_RK3528 \|\| vop2->version == VOP_VERSION_RK3562)
	3837	+ vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true);
3086	3838
3087	3839	VOP_CTRL_SET(vop2, cfg_done_en, 1);
3088	3840	/*
..	..	@@ -3092,6 +3844,7 @@
3092	3844	VOP_CTRL_SET(vop2, auto_gating_en, 0);
3093	3845
3094	3846	VOP_CTRL_SET(vop2, aclk_pre_auto_gating_en, 0);
	3847	+
3095	3848	/*
3096	3849	* Register OVERLAY_LAYER_SEL and OVERLAY_PORT_SEL should take effect immediately,
3097	3850	* than windows configuration(CLUSTER/ESMART/SMART) can take effect according the
..	..	@@ -3104,9 +3857,17 @@
3104	3857	*/
3105	3858	VOP_CTRL_SET(vop2, if_ctrl_cfg_done_imd, 1);
3106	3859
	3860	+ /* Close dynamic turn on/off rk3588 PD_ESMART and keep esmart pd on when enable */
	3861	+ if (vop2->version == VOP_VERSION_RK3588) {
	3862	+ struct vop2_power_domain *esmart_pd = vop2_find_pd_by_id(vop2, VOP2_PD_ESMART);
	3863	+
	3864	+ if (vop2_power_domain_status(esmart_pd))
	3865	+ esmart_pd->on = true;
	3866	+ else
	3867	+ vop2_power_domain_on(esmart_pd);
	3868	+ }
3107	3869	vop2_layer_map_initial(vop2, current_vp_id);
3108	3870	vop2_axi_irqs_enable(vop2);
3109		-
3110	3871	vop2->is_enabled = true;
3111	3872	}
3112	3873
..	..	@@ -3120,6 +3881,93 @@
3120	3881	vp->id, ret);
3121	3882	}
3122	3883
	3884	+/*
	3885	+ * The internal PD of VOP2 on rk3588 take effect immediately
	3886	+ * for power up and take effect by vsync for power down.
	3887	+ *
	3888	+ * And the PD_CLUSTER0 is a parent PD of PD_CLUSTER1/2/3,
	3889	+ * we may have this use case:
	3890	+ * Cluster0 is attached to VP0 for HDMI output,
	3891	+ * Cluster1 is attached to VP1 for MIPI DSI,
	3892	+
	3893	+ * When we enable Cluster1 on VP1, we should enable PD_CLUSTER0 as
	3894	+ * it is the parent PD, event though HDMI is plugout, VP1 is disabled,
	3895	+ * the PD of Cluster0 should keep power on.
	3896	+
	3897	+ * When system go to suspend:
	3898	+ * (1) Power down PD of Cluster1 before VP1 standby(the power down is take
	3899	+ * effect by vsync)
	3900	+ * (2) Power down PD of Cluster0
	3901	+ *
	3902	+ * But we have problem at step (2), Cluster0 is attached to VP0. but VP0
	3903	+ * is in standby mode, as it is never used or hdmi plugout. So there is
	3904	+ * no vsync, the power down will never take effect.
	3905	+
	3906	+ * According to IC designer: We must power down all internal PD of VOP
	3907	+ * before we power down the global PD_VOP.
	3908	+
	3909	+ * So we get this workaround:
	3910	+ * If we found a VP is in standby mode when we want power down a PD is
	3911	+ * attached to it, we release the VP from standby mode, than it will
	3912	+ * run a default timing and generate vsync. Than we can power down the
	3913	+ * PD by this vsync. After all this is done, we standby the VP at last.
	3914	+ */
	3915	+static void vop2_power_domain_off_by_disabled_vp(struct vop2_power_domain *pd)
	3916	+{
	3917	+ struct vop2_video_port *vp = NULL;
	3918	+ struct vop2 *vop2 = pd->vop2;
	3919	+ struct vop2_win *win;
	3920	+ struct drm_crtc *crtc;
	3921	+ uint32_t vp_id;
	3922	+ uint8_t phys_id;
	3923	+ int ret;
	3924	+
	3925	+ if (pd->data->id == VOP2_PD_CLUSTER0 \|\| pd->data->id == VOP2_PD_CLUSTER1 \|\|
	3926	+ pd->data->id == VOP2_PD_CLUSTER2 \|\| pd->data->id == VOP2_PD_CLUSTER3 \|\|
	3927	+ pd->data->id == VOP2_PD_ESMART) {
	3928	+ phys_id = ffs(pd->data->module_id_mask) - 1;
	3929	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	3930	+ vp_id = ffs(win->vp_mask) - 1;
	3931	+ vp = &vop2->vps[vp_id];
	3932	+ } else {
	3933	+ DRM_DEV_ERROR(vop2->dev, "unexpected power on pd%d\n", ffs(pd->data->id) - 1);
	3934	+ }
	3935	+
	3936	+ if (vp) {
	3937	+ ret = clk_prepare_enable(vp->dclk);
	3938	+ if (ret < 0)
	3939	+ DRM_DEV_ERROR(vop2->dev, "failed to enable dclk for video port%d - %d\n",
	3940	+ vp->id, ret);
	3941	+ crtc = &vp->rockchip_crtc.crtc;
	3942	+ VOP_MODULE_SET(vop2, vp, standby, 0);
	3943	+ vop2_power_domain_off(pd);
	3944	+ vop2_cfg_done(crtc);
	3945	+ vop2_wait_power_domain_off(pd);
	3946	+
	3947	+ reinit_completion(&vp->dsp_hold_completion);
	3948	+ vop2_dsp_hold_valid_irq_enable(crtc);
	3949	+ VOP_MODULE_SET(vop2, vp, standby, 1);
	3950	+ ret = wait_for_completion_timeout(&vp->dsp_hold_completion, msecs_to_jiffies(50));
	3951	+ if (!ret)
	3952	+ DRM_DEV_INFO(vop2->dev, "wait for vp%d dsp_hold timeout\n", vp->id);
	3953	+
	3954	+ vop2_dsp_hold_valid_irq_disable(crtc);
	3955	+ clk_disable_unprepare(vp->dclk);
	3956	+ }
	3957	+}
	3958	+
	3959	+static void vop2_power_off_all_pd(struct vop2 *vop2)
	3960	+{
	3961	+ struct vop2_power_domain pd, n;
	3962	+
	3963	+ list_for_each_entry_safe_reverse(pd, n, &vop2->pd_list_head, list) {
	3964	+ if (vop2_power_domain_status(pd))
	3965	+ vop2_power_domain_off_by_disabled_vp(pd);
	3966	+ pd->on = false;
	3967	+ pd->vp_mask = 0;
	3968	+ }
	3969	+}
	3970	+
3123	3971	static void vop2_disable(struct drm_crtc *crtc)
3124	3972	{
3125	3973	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3130,7 +3978,6 @@
3130	3978	if (--vop2->enable_count > 0)
3131	3979	return;
3132	3980
3133		- vop2->is_enabled = false;
3134	3981	if (vop2->is_iommu_enabled) {
3135	3982	/*
3136	3983	* vop2 standby complete, so iommu detach is safe.
..	..	@@ -3139,32 +3986,409 @@
3139	3986	rockchip_drm_dma_detach_device(vop2->drm_dev, vop2->dev);
3140	3987	vop2->is_iommu_enabled = false;
3141	3988	}
	3989	+ if (vop2->version == VOP_VERSION_RK3588)
	3990	+ vop2_power_off_all_pd(vop2);
3142	3991
	3992	+ vop2->is_enabled = false;
3143	3993	pm_runtime_put_sync(vop2->dev);
3144	3994
	3995	+ clk_disable_unprepare(vop2->pclk);
3145	3996	clk_disable_unprepare(vop2->aclk);
3146	3997	clk_disable_unprepare(vop2->hclk);
	3998	+}
	3999	+
	4000	+static void vop2_crtc_disable_dsc(struct vop2 *vop2, u8 dsc_id)
	4001	+{
	4002	+ struct vop2_dsc *dsc = &vop2->dscs[dsc_id];
	4003	+
	4004	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	4005	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, 0);
	4006	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 0);
	4007	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 0);
	4008	+}
	4009	+
	4010	+static struct vop2_clk vop2_clk_get(struct vop2 vop2, const char *name)
	4011	+{
	4012	+ struct vop2_clk clk, n;
	4013	+
	4014	+ if (!name)
	4015	+ return NULL;
	4016	+
	4017	+ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
	4018	+ if (!strcmp(clk_hw_get_name(&clk->hw), name))
	4019	+ return clk;
	4020	+ }
	4021	+
	4022	+ return NULL;
	4023	+}
	4024	+
	4025	+static void vop2_clk_set_parent(struct clk clk, struct clk parent)
	4026	+{
	4027	+ int ret = 0;
	4028	+
	4029	+ if (parent)
	4030	+ ret = clk_set_parent(clk, parent);
	4031	+ if (ret < 0)
	4032	+ DRM_WARN("failed to set %s as parent for %s\n",
	4033	+ __clk_get_name(parent), __clk_get_name(clk));
	4034	+}
	4035	+
	4036	+static int vop2_extend_clk_init(struct vop2 *vop2)
	4037	+{
	4038	+ const char * const extend_clk_name[] = {
	4039	+ "hdmi0_phy_pll", "hdmi1_phy_pll"};
	4040	+ struct drm_device *drm_dev = vop2->drm_dev;
	4041	+ struct clk *clk;
	4042	+ struct vop2_extend_pll *extend_pll;
	4043	+ int i;
	4044	+
	4045	+ INIT_LIST_HEAD(&vop2->extend_clk_list_head);
	4046	+
	4047	+ if (vop2->version != VOP_VERSION_RK3588)
	4048	+ return 0;
	4049	+
	4050	+ for (i = 0; i < ARRAY_SIZE(extend_clk_name); i++) {
	4051	+ clk = devm_clk_get_optional(drm_dev->dev, extend_clk_name[i]);
	4052	+ if (IS_ERR(clk)) {
	4053	+ dev_warn(drm_dev->dev, "failed to get %s: %ld\n",
	4054	+ extend_clk_name[i], PTR_ERR(clk));
	4055	+ continue;
	4056	+ }
	4057	+
	4058	+ if (!clk)
	4059	+ continue;
	4060	+
	4061	+ extend_pll = devm_kzalloc(drm_dev->dev, sizeof(*extend_pll), GFP_KERNEL);
	4062	+ if (!extend_pll)
	4063	+ return -ENOMEM;
	4064	+
	4065	+ extend_pll->clk = clk;
	4066	+ extend_pll->vp_mask = 0;
	4067	+ strncpy(extend_pll->clk_name, extend_clk_name[i], sizeof(extend_pll->clk_name));
	4068	+ list_add_tail(&extend_pll->list, &vop2->extend_clk_list_head);
	4069	+ }
	4070	+
	4071	+ return 0;
	4072	+}
	4073	+
	4074	+static struct vop2_extend_pll vop2_extend_clk_find_by_name(struct vop2 vop2, char *clk_name)
	4075	+{
	4076	+ struct vop2_extend_pll *extend_pll;
	4077	+
	4078	+ list_for_each_entry(extend_pll, &vop2->extend_clk_list_head, list) {
	4079	+ if (!strcmp(extend_pll->clk_name, clk_name))
	4080	+ return extend_pll;
	4081	+ }
	4082	+
	4083	+ return NULL;
	4084	+}
	4085	+
	4086	+static int vop2_extend_clk_switch_pll(struct vop2 vop2, struct vop2_extend_pll src,
	4087	+ struct vop2_extend_pll *dst)
	4088	+{
	4089	+ struct vop2_clk *dclk;
	4090	+ u32 vp_mask;
	4091	+ int i = 0;
	4092	+ char clk_name[32];
	4093	+
	4094	+ if (!src->vp_mask)
	4095	+ return -EINVAL;
	4096	+
	4097	+ if (dst->vp_mask)
	4098	+ return -EBUSY;
	4099	+
	4100	+ vp_mask = src->vp_mask;
	4101	+
	4102	+ while (vp_mask) {
	4103	+ if ((BIT(i) & src->vp_mask)) {
	4104	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", i);
	4105	+ dclk = vop2_clk_get(vop2, clk_name);
	4106	+ clk_set_rate(dst->clk, dclk->rate);
	4107	+ vop2_clk_set_parent(vop2->vps[i].dclk, dst->clk);
	4108	+ src->vp_mask &= ~BIT(i);
	4109	+ dst->vp_mask \|= BIT(i);
	4110	+ }
	4111	+ i++;
	4112	+ vp_mask = vp_mask >> 1;
	4113	+ }
	4114	+
	4115	+ return 0;
	4116	+}
	4117	+
	4118	+static inline int vop2_extend_clk_get_vp_id(struct vop2_extend_pll *ext_pll)
	4119	+{
	4120	+ return ffs(ext_pll->vp_mask) - 1;
	4121	+}
	4122	+
	4123	+/*
	4124	+ * Here are 2 hdmi phy pll can use for video port dclk. The strategies of how to use hdmi phy pll
	4125	+ * as follow:
	4126	+ *
	4127	+ * 1. hdmi phy pll can be used for video port0/1/2 when output format under 4K@60Hz;
	4128	+ *
	4129	+ * 2. When a video port connect both hdmi0 and hdmi1(may also connect other output interface),
	4130	+ * it must hold the hdmi0 and hdmi1 phy pll, and other video port can't use it. if request dclk
	4131	+ * is under 4K@60Hz, set the video port dlk parent as hdmi0 phy pll.if hdmi0 or hdmi1 phy pll
	4132	+ * is used by other video port, report a error.
	4133	+ *
	4134	+ * 3. When a video port(A) connect hdmi0(may also connect other output interface but not hdmi1),
	4135	+ * it must hold the hdmi0 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4136	+ * phy pll is used by other video port, report a error. If hdmi0 phy pll is used by another
	4137	+ * video port(B) and hdmi1 phy pll is free, set hdmi1 phy pll as video port(B) dclk parent and
	4138	+ * video port(A) hold hdmi0 phy pll. If hdmi0 phy pll is free, video port(A) hold hdmi0 pll.If
	4139	+ * video port(A) hold hdmi0 phy pll and request dclk is under 4k@60Hz, set hdmi0 phy pll as
	4140	+ * video port(A) dclk parent.
	4141	+ *
	4142	+ * 4. When a video port(A) connect hdmi1(may also connect other output interface but not hdmi0),
	4143	+ * it must hold the hdmi1 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4144	+ * phy pll is used by other video port, report a error. If hdmi1 phy pll is used by another
	4145	+ * video port(B) and hdmi0 phy pll is free, set hdmi0 phy pll as video port(B) dclk parent and
	4146	+ * video port(A) hold hdmi1 phy pll. If hdmi1 phy pll is free, video port(A) hold hdmi1 pll. If
	4147	+ * video port(A) hold hdmi1 phy pll and request dclk is under 4k@60Hz, set hdmi1 phy pll as
	4148	+ * video port(A) dclk parent.
	4149	+ *
	4150	+ * 5. When a video port connect dp(0, 1, or both, may also connect other output type but not hdmi0
	4151	+ * and hdmi1). If the request dclk is higher than 4K@60Hz or video port id is 2, do nothing.
	4152	+ * Otherwise get a free hdmi phy pll as video port dclk parent. If no free hdmi phy pll can be
	4153	+ * get, report a error.
	4154	+ */
	4155	+
	4156	+static int vop2_clk_set_parent_extend(struct vop2_video_port *vp,
	4157	+ struct rockchip_crtc_state *vcstate, bool enable)
	4158	+{
	4159	+ struct vop2 *vop2 = vp->vop2;
	4160	+ struct vop2_extend_pll hdmi0_phy_pll, hdmi1_phy_pll;
	4161	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	4162	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	4163	+
	4164	+ hdmi0_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	4165	+ hdmi1_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	4166	+
	4167	+ if (hdmi0_phy_pll)
	4168	+ clk_get_rate(hdmi0_phy_pll->clk);
	4169	+ if (hdmi1_phy_pll)
	4170	+ clk_get_rate(hdmi1_phy_pll->clk);
	4171	+
	4172	+ if ((!hdmi0_phy_pll && !hdmi1_phy_pll) \|\|
	4173	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) && !hdmi0_phy_pll) \|\|
	4174	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI1) && !hdmi1_phy_pll))
	4175	+ return 0;
	4176	+
	4177	+ if (enable) {
	4178	+ if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4179	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4180	+ if (hdmi0_phy_pll->vp_mask) {
	4181	+ DRM_ERROR("hdmi0 phy pll is used by vp%d\n",
	4182	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4183	+ return -EBUSY;
	4184	+ }
	4185	+
	4186	+ if (hdmi1_phy_pll->vp_mask) {
	4187	+ DRM_ERROR("hdmi1 phy pll is used by vp%d\n",
	4188	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4189	+ return -EBUSY;
	4190	+ }
	4191	+
	4192	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4193	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4194	+ else
	4195	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4196	+
	4197	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4198	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4199	+ } else if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4200	+ !(vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4201	+ if (hdmi0_phy_pll->vp_mask) {
	4202	+ if (hdmi1_phy_pll) {
	4203	+ if (hdmi1_phy_pll->vp_mask) {
	4204	+ DRM_ERROR("hdmi0: phy pll is used by vp%d:vp%d\n",
	4205	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4206	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4207	+ return -EBUSY;
	4208	+ }
	4209	+
	4210	+ vop2_extend_clk_switch_pll(vop2, hdmi0_phy_pll,
	4211	+ hdmi1_phy_pll);
	4212	+ } else {
	4213	+ DRM_ERROR("hdmi0: phy pll is used by vp%d\n",
	4214	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4215	+ return -EBUSY;
	4216	+ }
	4217	+ }
	4218	+
	4219	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4220	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4221	+ else
	4222	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4223	+
	4224	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4225	+ } else if (!(vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4226	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4227	+ if (hdmi1_phy_pll->vp_mask) {
	4228	+ if (hdmi0_phy_pll) {
	4229	+ if (hdmi0_phy_pll->vp_mask) {
	4230	+ DRM_ERROR("hdmi1: phy pll is used by vp%d:vp%d\n",
	4231	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4232	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4233	+ return -EBUSY;
	4234	+ }
	4235	+
	4236	+ vop2_extend_clk_switch_pll(vop2, hdmi1_phy_pll,
	4237	+ hdmi0_phy_pll);
	4238	+ } else {
	4239	+ DRM_ERROR("hdmi1: phy pll is used by vp%d\n",
	4240	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4241	+ return -EBUSY;
	4242	+ }
	4243	+ }
	4244	+
	4245	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4246	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4247	+ else
	4248	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4249	+
	4250	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4251	+ } else if (output_if_is_dp(vcstate->output_if)) {
	4252	+ if (vp->id == 2) {
	4253	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4254	+ return 0;
	4255	+ }
	4256	+
	4257	+ if (hdmi0_phy_pll && !hdmi0_phy_pll->vp_mask) {
	4258	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4259	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4260	+ } else if (hdmi1_phy_pll && !hdmi1_phy_pll->vp_mask) {
	4261	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4262	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4263	+ } else {
	4264	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4265	+ DRM_INFO("No free hdmi phy pll for DP, use default parent\n");
	4266	+ }
	4267	+ }
	4268	+ } else {
	4269	+ if (hdmi0_phy_pll && (BIT(vp->id) & hdmi0_phy_pll->vp_mask))
	4270	+ hdmi0_phy_pll->vp_mask &= ~BIT(vp->id);
	4271	+
	4272	+ if (hdmi1_phy_pll && (BIT(vp->id) & hdmi1_phy_pll->vp_mask))
	4273	+ hdmi1_phy_pll->vp_mask &= ~BIT(vp->id);
	4274	+ }
	4275	+
	4276	+ return 0;
	4277	+}
	4278	+
	4279	+static void vop2_crtc_atomic_disable_for_psr(struct drm_crtc *crtc,
	4280	+ struct drm_crtc_state *old_state)
	4281	+{
	4282	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4283	+ struct vop2 *vop2 = vp->vop2;
	4284	+
	4285	+ vop2_disable_all_planes_for_crtc(crtc);
	4286	+ drm_crtc_vblank_off(crtc);
	4287	+ if (hweight8(vop2->active_vp_mask) == 1) {
	4288	+ u32 adjust_aclk_rate = 0;
	4289	+ u32 htotal = (VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16) & 0xffff;
	4290	+ u32 pre_scan_dly = VOP_MODULE_GET(vop2, vp, pre_scan_htiming);
	4291	+ u32 pre_scan_hblank = pre_scan_dly & 0x1fff;
	4292	+ u32 pre_scan_hactive = (pre_scan_dly >> 16) & 0x1fff;
	4293	+ u32 dclk_rate = crtc->state->adjusted_mode.crtc_clock / 1000;
	4294	+ /**
	4295	+ * (pre_scan_hblank + pre_scan_hactive) x aclk_margin / adjust_aclk_rate = hotal / dclk_rate
	4296	+ * aclk_margin = 1.2, so
	4297	+ * adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) x 1.2 * aclk_margin / htotal
	4298	+ */
	4299	+
	4300	+ adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) * dclk_rate * 12 / 10 / htotal;
	4301	+
	4302	+ vop2->aclk_rate = clk_get_rate(vop2->aclk);
	4303	+ clk_set_rate(vop2->aclk, adjust_aclk_rate * 1000000L);
	4304	+ vop2->aclk_rate_reset = true;
	4305	+ }
3147	4306	}
3148	4307
3149	4308	static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
3150	4309	struct drm_crtc_state *old_state)
3151	4310	{
3152	4311	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4312	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3153	4313	struct vop2 *vop2 = vp->vop2;
	4314	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	4315	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	4316	+ bool dual_channel = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE);
3154	4317	int ret;
3155	4318
3156	4319	WARN_ON(vp->event);
	4320	+
	4321	+ if (crtc->state->self_refresh_active) {
	4322	+ vop2_crtc_atomic_disable_for_psr(crtc, old_state);
	4323	+ goto out;
	4324	+ }
	4325	+
3157	4326	vop2_lock(vop2);
3158	4327	DRM_DEV_INFO(vop2->dev, "Crtc atomic disable vp%d\n", vp->id);
	4328	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 0);
	4329	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 0);
3159	4330	drm_crtc_vblank_off(crtc);
	4331	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4332	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4333	+ vop2->data->nr_dscs) {
	4334	+ if (dual_channel) {
	4335	+ vop2_crtc_disable_dsc(vop2, 0);
	4336	+ vop2_crtc_disable_dsc(vop2, 1);
	4337	+ } else {
	4338	+ vop2_crtc_disable_dsc(vop2, vcstate->dsc_id);
	4339	+ }
	4340	+ }
3160	4341
3161	4342	if (vp->cubic_lut) {
3162	4343	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
3163	4344	VOP_MODULE_SET(vop2, vp, cubic_lut_en, 0);
3164	4345	}
3165	4346
	4347	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	4348	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 0);
3166	4349	vop2_disable_all_planes_for_crtc(crtc);
3167	4350
	4351	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4352	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4353	+ vop2->data->nr_dscs && vop2->dscs[vcstate->dsc_id].pd) {
	4354	+ if (dual_channel) {
	4355	+ vop2_power_domain_put(vop2->dscs[0].pd);
	4356	+ vop2_power_domain_put(vop2->dscs[1].pd);
	4357	+ vop2->dscs[0].pd->vp_mask = 0;
	4358	+ vop2->dscs[1].pd->vp_mask = 0;
	4359	+ vop2->dscs[0].attach_vp_id = -1;
	4360	+ vop2->dscs[1].attach_vp_id = -1;
	4361	+ } else {
	4362	+ vop2_power_domain_put(vop2->dscs[vcstate->dsc_id].pd);
	4363	+ vop2->dscs[vcstate->dsc_id].pd->vp_mask = 0;
	4364	+ vop2->dscs[vcstate->dsc_id].attach_vp_id = -1;
	4365	+ }
	4366	+ vop2->dscs[vcstate->dsc_id].enabled = false;
	4367	+ vcstate->dsc_enable = false;
	4368	+ }
	4369	+
	4370	+ if (vp->output_if & VOP_OUTPUT_IF_eDP0)
	4371	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 0);
	4372	+
	4373	+ if (vp->output_if & VOP_OUTPUT_IF_eDP1)
	4374	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 0);
	4375	+
	4376	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI0) {
	4377	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 0);
	4378	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 0);
	4379	+ }
	4380	+
	4381	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI1) {
	4382	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 0);
	4383	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 0);
	4384	+ }
	4385	+
	4386	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 0);
	4387	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 0);
	4388	+
	4389	+ vp->output_if = 0;
	4390	+
	4391	+ vop2_clk_set_parent_extend(vp, vcstate, false);
3168	4392	/*
3169	4393	* Vop standby will take effect at end of current frame,
3170	4394	* if dsp hold valid irq happen, it means standby complete.
..	..	@@ -3177,6 +4401,8 @@
3177	4401
3178	4402	spin_lock(&vop2->reg_lock);
3179	4403
	4404	+ VOP_MODULE_SET(vop2, vp, splice_en, 0);
	4405	+
3180	4406	VOP_MODULE_SET(vop2, vp, standby, 1);
3181	4407
3182	4408	spin_unlock(&vop2->reg_lock);
..	..	@@ -3188,11 +4414,21 @@
3188	4414	vop2_dsp_hold_valid_irq_disable(crtc);
3189	4415
3190	4416	vop2_disable(crtc);
3191		- vop2_unlock(vop2);
3192	4417
3193	4418	vop2->active_vp_mask &= ~BIT(vp->id);
	4419	+ if (vcstate->splice_mode)
	4420	+ vop2->active_vp_mask &= ~BIT(splice_vp->id);
	4421	+ vcstate->splice_mode = false;
	4422	+ vcstate->output_flags = 0;
	4423	+ vp->splice_mode_right = false;
	4424	+ vp->loader_protect = false;
	4425	+ splice_vp->splice_mode_right = false;
	4426	+ memset(&vp->active_tv_state, 0, sizeof(vp->active_tv_state));
	4427	+ vop2_unlock(vop2);
	4428	+
3194	4429	vop2_set_system_status(vop2);
3195	4430
	4431	+out:
3196	4432	if (crtc->state->event && !crtc->state->active) {
3197	4433	spin_lock_irq(&crtc->dev->event_lock);
3198	4434	drm_crtc_send_vblank_event(crtc, crtc->state->event);
..	..	@@ -3202,23 +4438,140 @@
3202	4438	}
3203	4439	}
3204	4440
	4441	+static int vop2_cluster_two_win_mode_check(struct drm_plane_state *pstate)
	4442	+{
	4443	+ struct drm_atomic_state *state = pstate->state;
	4444	+ struct drm_plane *plane = pstate->plane;
	4445	+ struct vop2_win *win = to_vop2_win(plane);
	4446	+ struct vop2 *vop2 = win->vop2;
	4447	+ struct vop2_win *main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
	4448	+ struct drm_plane_state *main_pstate;
	4449	+ int actual_w = drm_rect_width(&pstate->src) >> 16;
	4450	+ int xoffset;
	4451	+
	4452	+ if (pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4453	+ xoffset = 0;
	4454	+ else
	4455	+ xoffset = pstate->src.x1 >> 16;
	4456	+
	4457	+ if ((actual_w + xoffset % 16) > 2048) {
	4458	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4459	+ win->name, actual_w, xoffset);
	4460	+ return -EINVAL;
	4461	+ }
	4462	+
	4463	+ main_pstate = drm_atomic_get_new_plane_state(state, &main_win->base);
	4464	+
	4465	+ if (pstate->fb->modifier != main_pstate->fb->modifier) {
	4466	+ DRM_ERROR("%s(fb->modifier: 0x%llx) must use same data layout as %s(fb->modifier: 0x%llx)\n",
	4467	+ win->name, pstate->fb->modifier, main_win->name, main_pstate->fb->modifier);
	4468	+ return -EINVAL;
	4469	+ }
	4470	+
	4471	+ if (main_pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4472	+ xoffset = 0;
	4473	+ else
	4474	+ xoffset = main_pstate->src.x1 >> 16;
	4475	+ actual_w = drm_rect_width(&main_pstate->src) >> 16;
	4476	+
	4477	+ if ((actual_w + xoffset % 16) > 2048) {
	4478	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4479	+ main_win->name, actual_w, xoffset);
	4480	+ return -EINVAL;
	4481	+ }
	4482	+
	4483	+ return 0;
	4484	+}
	4485	+
	4486	+static int vop2_cluter_splice_scale_check(struct vop2_win win, struct drm_plane_state pstate,
	4487	+ u16 hdisplay)
	4488	+{
	4489	+ struct drm_rect src = drm_plane_state_src(pstate);
	4490	+ struct drm_rect dst = drm_plane_state_dest(pstate);
	4491	+ u16 half_hdisplay = hdisplay >> 1;
	4492	+
	4493	+ /* scale up is ok */
	4494	+ if ((drm_rect_width(&src) >> 16) <= drm_rect_width(&dst))
	4495	+ return 0;
	4496	+
	4497	+ if ((drm_rect_width(&src) >> 16) <= VOP2_MAX_VP_OUTPUT_WIDTH)
	4498	+ return 0;
	4499	+ /*
	4500	+ * Cluster scale down limitation in splice mode:
	4501	+ * If scale down, must display at horizontal center
	4502	+ */
	4503	+ if ((dst.x1 < half_hdisplay) && (dst.x2 > half_hdisplay)) {
	4504	+ if ((dst.x2 + dst.x1) != hdisplay) {
	4505	+ DRM_ERROR("%s src_w: %d dst_w %d dst(%d %d) must scale down at center in splice mode\n",
	4506	+ win->name, drm_rect_width(&src) >> 16,
	4507	+ drm_rect_width(&dst), dst.x1, dst.x2);
	4508	+ return -EINVAL;
	4509	+ }
	4510	+
	4511	+ if (drm_rect_calc_hscale(&src, &dst, 1, FRAC_16_16(6, 5)) < 0) {
	4512	+ DRM_ERROR("%s %d --> %d scale down factor should < 1.2 in splice mode\n",
	4513	+ win->name, drm_rect_width(&src) >> 16, drm_rect_width(&dst));
	4514	+ return -EINVAL;
	4515	+ }
	4516	+ }
	4517	+
	4518	+ return 0;
	4519	+}
	4520	+
	4521	+static int vop2_plane_splice_check(struct drm_plane plane, struct drm_plane_state pstate,
	4522	+ struct drm_display_mode *mode)
	4523	+{
	4524	+ struct vop2_win *win = to_vop2_win(plane);
	4525	+ int ret = 0;
	4526	+
	4527	+ if (!(win->feature & WIN_FEATURE_SPLICE_LEFT)) {
	4528	+ DRM_ERROR("%s can't be left win in splice mode\n", win->name);
	4529	+ return -EINVAL;
	4530	+ }
	4531	+
	4532	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4533	+ DRM_ERROR("%s can't use two win mode in splice mode\n", win->name);
	4534	+ return -EINVAL;
	4535	+ }
	4536	+
	4537	+ if ((pstate->rotation & DRM_MODE_ROTATE_270) \|\|
	4538	+ (pstate->rotation & DRM_MODE_ROTATE_90) \|\|
	4539	+ (pstate->rotation & DRM_MODE_REFLECT_X)) {
	4540	+ DRM_ERROR("%s can't rotate 270/90 and xmirror in splice mode\n", win->name);
	4541	+ return -EINVAL;
	4542	+ }
	4543	+
	4544	+ /* check for cluster splice scale down */
	4545	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4546	+ ret = vop2_cluter_splice_scale_check(win, pstate, mode->hdisplay);
	4547	+
	4548	+ return ret;
	4549	+}
	4550	+
3205	4551	static int vop2_plane_atomic_check(struct drm_plane plane, struct drm_plane_state state)
3206	4552	{
3207	4553	struct vop2_plane_state *vpstate = to_vop2_plane_state(state);
3208	4554	struct vop2_win *win = to_vop2_win(plane);
	4555	+ struct vop2_win *splice_win;
	4556	+ struct vop2 *vop2 = win->vop2;
3209	4557	struct drm_framebuffer *fb = state->fb;
	4558	+ struct drm_display_mode *mode;
3210	4559	struct drm_crtc *crtc = state->crtc;
3211	4560	struct drm_crtc_state *cstate;
	4561	+ struct rockchip_crtc_state *vcstate;
3212	4562	struct vop2_video_port *vp;
3213	4563	const struct vop2_data *vop2_data;
3214	4564	struct drm_rect *dest = &vpstate->dest;
3215	4565	struct drm_rect *src = &vpstate->src;
	4566	+ struct drm_gem_object obj, uv_obj;
	4567	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
3216	4568	int min_scale = win->regs->scl ? FRAC_16_16(1, 8) : DRM_PLANE_HELPER_NO_SCALING;
3217	4569	int max_scale = win->regs->scl ? FRAC_16_16(8, 1) : DRM_PLANE_HELPER_NO_SCALING;
3218	4570	uint32_t tile_size = 1;
	4571	+ int max_input_w;
	4572	+ int max_input_h;
3219	4573	unsigned long offset;
3220	4574	dma_addr_t dma_addr;
3221		- void *kvaddr;
3222	4575	int ret;
3223	4576
3224	4577	crtc = crtc ? crtc : plane->state->crtc;
..	..	@@ -3234,6 +4587,26 @@
3234	4587	if (WARN_ON(!cstate))
3235	4588	return -EINVAL;
3236	4589
	4590	+ mode = &cstate->mode;
	4591	+ vcstate = to_rockchip_crtc_state(cstate);
	4592	+
	4593	+ max_input_w = vop2_data->max_input.width;
	4594	+ max_input_h = vop2_data->max_input.height;
	4595	+
	4596	+ if (vop2_has_feature(win->vop2, VOP_FEATURE_SPLICE)) {
	4597	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	4598	+ vcstate->splice_mode = true;
	4599	+ ret = vop2_plane_splice_check(plane, state, mode);
	4600	+ if (ret < 0)
	4601	+ return ret;
	4602	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	4603	+ splice_win->splice_mode_right = true;
	4604	+ splice_win->left_win = win;
	4605	+ win->splice_win = splice_win;
	4606	+ max_input_w <<= 1;
	4607	+ }
	4608	+ }
	4609	+
3237	4610	vpstate->xmirror_en = (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0;
3238	4611	vpstate->ymirror_en = (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0;
3239	4612	vpstate->rotate_270_en = (state->rotation & DRM_MODE_ROTATE_270) ? 1 : 0;
..	..	@@ -3243,7 +4616,6 @@
3243	4616	DRM_ERROR("Can't rotate 90 and 270 at the same time\n");
3244	4617	return -EINVAL;
3245	4618	}
3246		-
3247	4619
3248	4620	ret = drm_atomic_helper_check_plane_state(state, cstate,
3249	4621	min_scale, max_scale,
..	..	@@ -3284,13 +4656,13 @@
3284	4656	return 0;
3285	4657	}
3286	4658
3287		- if (drm_rect_width(src) >> 16 > vop2_data->max_input.width \|\|
3288		- drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
	4659	+ if (drm_rect_width(src) >> 16 > max_input_w \|\|
	4660	+ drm_rect_height(src) >> 16 > max_input_h) {
3289	4661	DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
3290	4662	drm_rect_width(src) >> 16,
3291	4663	drm_rect_height(src) >> 16,
3292		- vop2_data->max_input.width,
3293		- vop2_data->max_input.height);
	4664	+ max_input_w,
	4665	+ max_input_h);
3294	4666	return -EINVAL;
3295	4667	}
3296	4668
..	..	@@ -3313,11 +4685,31 @@
3313	4685	* This is special feature at rk356x, the cluster layer only can support
3314	4686	* afbc format and can't support linear format;
3315	4687	*/
3316		- if (VOP_MAJOR(vop2_data->version) == 0x40 && VOP_MINOR(vop2_data->version) == 0x15) {
	4688	+ if (vp->vop2->version == VOP_VERSION_RK3568) {
3317	4689	if (vop2_cluster_window(win) && !vpstate->afbc_en) {
3318	4690	DRM_ERROR("Unsupported linear format at %s\n", win->name);
3319	4691	return -EINVAL;
3320	4692	}
	4693	+ }
	4694	+
	4695	+ if (vp->vop2->version > VOP_VERSION_RK3568) {
	4696	+ if (vop2_cluster_window(win) && !vpstate->afbc_en && fb->format->is_yuv && !is_vop3(vop2)) {
	4697	+ DRM_ERROR("Unsupported linear yuv format at %s\n", win->name);
	4698	+ return -EINVAL;
	4699	+ }
	4700	+
	4701	+ if (vop2_cluster_window(win) && !vpstate->afbc_en &&
	4702	+ (win->supported_rotations & state->rotation)) {
	4703	+ DRM_ERROR("Unsupported linear rotation(%d) format at %s\n",
	4704	+ state->rotation, win->name);
	4705	+ return -EINVAL;
	4706	+ }
	4707	+ }
	4708	+
	4709	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4710	+ ret = vop2_cluster_two_win_mode_check(state);
	4711	+ if (ret < 0)
	4712	+ return ret;
3321	4713	}
3322	4714
3323	4715	/*
..	..	@@ -3329,7 +4721,10 @@
3329	4721	return -EINVAL;
3330	4722	}
3331	4723
3332		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[0] / 8 * tile_size;
	4724	+ if (fb->format->char_per_block[0] == 0)
	4725	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[0] * tile_size;
	4726	+ else
	4727	+ offset = drm_format_info_min_pitch(fb->format, 0, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size;
3333	4728	vpstate->offset = offset + fb->offsets[0];
3334	4729
3335	4730	/*
..	..	@@ -3342,30 +4737,33 @@
3342	4737	else
3343	4738	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[0];
3344	4739
3345		- dma_addr = rockchip_fb_get_dma_addr(fb, 0);
3346		- kvaddr = rockchip_fb_get_kvaddr(fb, 0);
	4740	+ obj = fb->obj[0];
	4741	+ rk_obj = to_rockchip_obj(obj);
3347	4742
3348		- vpstate->yrgb_mst = dma_addr + offset + fb->offsets[0];
3349		- vpstate->yrgb_kvaddr = kvaddr + offset + fb->offsets[0];
3350		- if (fb->format->is_yuv) {
3351		- int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
3352		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
	4743	+ vpstate->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
	4744	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	4745	+ int hsub = fb->format->hsub;
	4746	+ int vsub = fb->format->vsub;
3353	4747
3354		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[1] / hsub / 8 * tile_size;
	4748	+ if (fb->format->char_per_block[0] == 0)
	4749	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[1] / hsub * tile_size;
	4750	+ else
	4751	+ offset = drm_format_info_min_pitch(fb->format, 1, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size / hsub;
	4752	+
3355	4753	if (vpstate->tiled_en)
3356	4754	offset /= vsub;
3357	4755	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[1] / vsub;
	4756	+
	4757	+ uv_obj = fb->obj[1];
	4758	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	4759	+
3358	4760	if (vpstate->ymirror_en && !vpstate->afbc_en)
3359	4761	offset += fb->pitches[1] * ((state->src_h >> 16) - 2) / vsub;
3360		- dma_addr = rockchip_fb_get_dma_addr(fb, 1);
3361		- dma_addr += offset + fb->offsets[1];
	4762	+ dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
3362	4763	vpstate->uv_mst = dma_addr;
3363		-
3364	4764	/* tile 4x4 m0 format, y and uv is packed together */
3365		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0) {
	4765	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0)
3366	4766	vpstate->yrgb_mst += offset;
3367		- vpstate->yrgb_kvaddr += offset;
3368		- }
3369	4767	}
3370	4768
3371	4769	return 0;
..	..	@@ -3379,15 +4777,17 @@
3379	4777	struct vop2_plane_state *vpstate = to_vop2_plane_state(plane->state);
3380	4778	#endif
3381	4779
3382		- DRM_DEV_DEBUG(vop2->dev, "%s disable\n", win->name);
	4780	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE, "%s disable %s\n",
	4781	+ win->name, current->comm);
3383	4782
3384	4783	if (!old_state->crtc)
3385	4784	return;
3386	4785
3387	4786	spin_lock(&vop2->reg_lock);
3388	4787
3389		- vop2_win_disable(win);
3390		- VOP_WIN_SET(vop2, win, yuv_clip, 0);
	4788	+ vop2_win_disable(win, false);
	4789	+ if (win->splice_win)
	4790	+ vop2_win_disable(win->splice_win, false);
3391	4791
3392	4792	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
3393	4793	kfree(vpstate->planlist);
..	..	@@ -3451,6 +4851,64 @@
3451	4851	VOP_WIN_SET(vop2, win, color_key, color_key);
3452	4852	}
3453	4853
	4854	+static void vop2_calc_drm_rect_for_splice(struct vop2_plane_state *vpstate,
	4855	+ struct drm_rect left_src, struct drm_rect left_dst,
	4856	+ struct drm_rect right_src, struct drm_rect right_dst)
	4857	+{
	4858	+ struct drm_crtc *crtc = vpstate->base.crtc;
	4859	+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	4860	+ struct drm_rect *dst = &vpstate->dest;
	4861	+ struct drm_rect *src = &vpstate->src;
	4862	+ u16 half_hdisplay = mode->crtc_hdisplay >> 1;
	4863	+ int hscale = drm_rect_calc_hscale(src, dst, 0, INT_MAX);
	4864	+ int dst_w = drm_rect_width(dst);
	4865	+ int src_w = drm_rect_width(src) >> 16;
	4866	+ int left_src_w, left_dst_w, right_dst_w;
	4867	+ struct drm_plane_state *pstate = &vpstate->base;
	4868	+ struct drm_framebuffer *fb = pstate->fb;
	4869	+
	4870	+ left_dst_w = min_t(u16, half_hdisplay, dst->x2) - dst->x1;
	4871	+ if (left_dst_w < 0)
	4872	+ left_dst_w = 0;
	4873	+ right_dst_w = dst_w - left_dst_w;
	4874	+
	4875	+ if (!right_dst_w)
	4876	+ left_src_w = src_w;
	4877	+ else
	4878	+ left_src_w = (left_dst_w * hscale) >> 16;
	4879	+
	4880	+ /*
	4881	+ * Make sure the yrgb/uv mst of right win are byte aligned
	4882	+ * with full pixel.
	4883	+ */
	4884	+ if (right_dst_w) {
	4885	+ if (fb->format->format == DRM_FORMAT_NV15)
	4886	+ left_src_w &= ~0x7;
	4887	+ else if (fb->format->format == DRM_FORMAT_NV12)
	4888	+ left_src_w &= ~0x1;
	4889	+ }
	4890	+ left_src->x1 = src->x1;
	4891	+ left_src->x2 = src->x1 + (left_src_w << 16);
	4892	+ left_dst->x1 = dst->x1;
	4893	+ left_dst->x2 = dst->x1 + left_dst_w;
	4894	+ right_src->x1 = left_src->x2;
	4895	+ right_src->x2 = src->x2;
	4896	+ right_dst->x1 = dst->x1 + left_dst_w - half_hdisplay;
	4897	+ if (right_dst->x1 < 0)
	4898	+ right_dst->x1 = 0;
	4899	+
	4900	+ right_dst->x2 = right_dst->x1 + right_dst_w;
	4901	+
	4902	+ left_src->y1 = src->y1;
	4903	+ left_src->y2 = src->y2;
	4904	+ left_dst->y1 = dst->y1;
	4905	+ left_dst->y2 = dst->y2;
	4906	+ right_src->y1 = src->y1;
	4907	+ right_src->y2 = src->y2;
	4908	+ right_dst->y1 = dst->y1;
	4909	+ right_dst->y2 = dst->y2;
	4910	+}
	4911	+
3454	4912	static void rk3588_vop2_win_cfg_axi(struct vop2_win *win)
3455	4913	{
3456	4914	struct vop2 *vop2 = win->vop2;
..	..	@@ -3485,18 +4943,17 @@
3485	4943	}
3486	4944	}
3487	4945
3488		-static void vop2_plane_atomic_update(struct drm_plane plane, struct drm_plane_state old_state)
	4946	+static void vop2_win_atomic_update(struct vop2_win win, struct drm_rect src, struct drm_rect *dst,
	4947	+ struct drm_plane_state *pstate)
3489	4948	{
3490		- struct drm_plane_state *pstate = plane->state;
3491	4949	struct drm_crtc *crtc = pstate->crtc;
3492		- struct vop2_win *win = to_vop2_win(plane);
3493	4950	struct vop2_video_port *vp = to_vop2_video_port(crtc);
3494	4951	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
3495	4952	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
3496		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3497	4953	struct vop2 *vop2 = win->vop2;
3498	4954	struct drm_framebuffer *fb = pstate->fb;
3499		- uint32_t bpp = fb->format->bpp[0];
	4955	+ struct drm_rect *left_src = &vpstate->src;
	4956	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
3500	4957	uint32_t actual_w, actual_h, dsp_w, dsp_h;
3501	4958	uint32_t dsp_stx, dsp_sty;
3502	4959	uint32_t act_info, dsp_info, dsp_st;
..	..	@@ -3504,30 +4961,283 @@
3504	4961	uint32_t afbc_format;
3505	4962	uint32_t rb_swap;
3506	4963	uint32_t uv_swap;
3507		- struct drm_rect *src = &vpstate->src;
3508		- struct drm_rect *dest = &vpstate->dest;
3509		- uint32_t afbc_tile_num;
3510	4964	uint32_t afbc_half_block_en;
	4965	+ uint32_t afbc_tile_num;
3511	4966	uint32_t lb_mode;
3512	4967	uint32_t stride, uv_stride = 0;
3513	4968	uint32_t transform_offset;
	4969	+ /* offset of the right window in splice mode */
	4970	+ uint32_t splice_pixel_offset = 0;
	4971	+ uint32_t splice_yrgb_offset = 0;
	4972	+ uint32_t splice_uv_offset = 0;
	4973	+ uint32_t afbc_xoffset;
	4974	+ uint32_t hsub;
	4975	+ dma_addr_t yrgb_mst;
	4976	+ dma_addr_t uv_mst;
	4977	+
3514	4978	struct drm_format_name_buf format_name;
3515	4979	bool dither_up;
3516	4980	bool tile_4x4_m0 = vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 ? true : false;
3517	4981
	4982	+ actual_w = drm_rect_width(src) >> 16;
	4983	+ actual_h = drm_rect_height(src) >> 16;
	4984	+
	4985	+ if (!actual_w \|\| !actual_h) {
	4986	+ vop2_win_disable(win, true);
	4987	+ return;
	4988	+ }
	4989	+
	4990	+ dsp_w = drm_rect_width(dst);
	4991	+ /*
	4992	+ * This win is for the right part of the plane,
	4993	+ * we need calculate the fb offset for it.
	4994	+ */
	4995	+ if (win->splice_mode_right) {
	4996	+ splice_pixel_offset = (src->x1 - left_src->x1) >> 16;
	4997	+ splice_yrgb_offset = drm_format_info_min_pitch(fb->format, 0, splice_pixel_offset);
	4998	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	4999	+ hsub = fb->format->hsub;
	5000	+ splice_uv_offset = drm_format_info_min_pitch(fb->format, 1, splice_pixel_offset / hsub);
	5001	+ }
	5002	+ }
	5003	+
	5004	+ if (dst->x1 + dsp_w > adjusted_mode->crtc_hdisplay) {
	5005	+ DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
	5006	+ vp->id, win->name, dst->x1, dsp_w, adjusted_mode->crtc_hdisplay);
	5007	+ dsp_w = adjusted_mode->crtc_hdisplay - dst->x1;
	5008	+ if (dsp_w < 4)
	5009	+ dsp_w = 4;
	5010	+ actual_w = dsp_w * actual_w / drm_rect_width(dst);
	5011	+ }
	5012	+ dsp_h = drm_rect_height(dst);
	5013	+ if (dst->y1 + dsp_h > adjusted_mode->crtc_vdisplay) {
	5014	+ DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
	5015	+ vp->id, win->name, dst->y1, dsp_h, adjusted_mode->crtc_vdisplay);
	5016	+ dsp_h = adjusted_mode->crtc_vdisplay - dst->y1;
	5017	+ if (dsp_h < 4)
	5018	+ dsp_h = 4;
	5019	+ actual_h = dsp_h * actual_h / drm_rect_height(dst);
	5020	+ }
	5021	+
	5022	+ /*
	5023	+ * Workaround only for rk3568 vop
	5024	+ */
	5025	+ if (vop2->version == VOP_VERSION_RK3568) {
	5026	+ /*
	5027	+ * This is workaround solution for IC design:
	5028	+ * esmart can't support scale down when actual_w % 16 == 1.
	5029	+ */
	5030	+ if (!(win->feature & WIN_FEATURE_AFBDC)) {
	5031	+ if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
	5032	+ DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
	5033	+ actual_w -= 1;
	5034	+ }
	5035	+ }
	5036	+
	5037	+ if (vpstate->afbc_en && actual_w % 4) {
	5038	+ DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
	5039	+ vp->id, win->name, actual_w);
	5040	+ actual_w = ALIGN_DOWN(actual_w, 4);
	5041	+ }
	5042	+ }
	5043	+
	5044	+ act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
	5045	+ dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
	5046	+ stride = DIV_ROUND_UP(fb->pitches[0], 4);
	5047	+ dsp_stx = dst->x1;
	5048	+ dsp_sty = dst->y1;
	5049	+ dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
	5050	+
	5051	+ if (vpstate->tiled_en) {
	5052	+ if (is_vop3(vop2))
	5053	+ format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
	5054	+ else
	5055	+ format = vop2_convert_tiled_format(fb->format->format);
	5056	+ } else {
	5057	+ format = vop2_convert_format(fb->format->format);
	5058	+ }
	5059	+
	5060	+ vop2_setup_csc_mode(vp, vpstate);
	5061	+
	5062	+ afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
	5063	+
	5064	+ vop2_win_enable(win);
	5065	+ spin_lock(&vop2->reg_lock);
	5066	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
	5067	+ "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad] by %s\n",
	5068	+ vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
	5069	+ dsp_stx, dsp_sty,
	5070	+ drm_get_format_name(fb->format->format, &format_name),
	5071	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst, current->comm);
	5072	+
	5073	+ if (vop2->version != VOP_VERSION_RK3568)
	5074	+ rk3588_vop2_win_cfg_axi(win);
	5075	+
	5076	+ if (!win->parent && !vop2_cluster_window(win) && is_vop3(vop2))
	5077	+ VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
	5078	+
	5079	+ if (vpstate->afbc_en) {
	5080	+ /* the afbc superblock is 16 x 16 */
	5081	+ afbc_format = vop2_convert_afbc_format(fb->format->format);
	5082	+ /* Enable color transform for YTR */
	5083	+ if (fb->modifier & AFBC_FORMAT_MOD_YTR)
	5084	+ afbc_format \|= (1 << 4);
	5085	+ afbc_tile_num = ALIGN(actual_w, 16) >> 4;
	5086	+
	5087	+ /* The right win should have a src offset in splice mode */
	5088	+ afbc_xoffset = (src->x1 >> 16);
	5089	+ /* AFBC pic_vir_width is count by pixel, this is different
	5090	+ * with WIN_VIR_STRIDE.
	5091	+ */
	5092	+ if (!bpp) {
	5093	+ WARN(1, "bpp is zero\n");
	5094	+ bpp = 1;
	5095	+ }
	5096	+ stride = (fb->pitches[0] << 3) / bpp;
	5097	+ if ((stride & 0x3f) &&
	5098	+ (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
	5099	+ DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
	5100	+ vp->id, win->name, stride, pstate->rotation);
	5101	+
	5102	+ rb_swap = vop2_afbc_rb_swap(fb->format->format);
	5103	+ uv_swap = vop2_afbc_uv_swap(fb->format->format);
	5104	+ vpstate->afbc_half_block_en = afbc_half_block_en;
	5105	+
	5106	+ transform_offset = vop2_afbc_transform_offset(vpstate, splice_pixel_offset);
	5107	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
	5108	+ VOP_AFBC_SET(vop2, win, format, afbc_format);
	5109	+ VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
	5110	+ VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
	5111	+
	5112	+ if (vop2->version == VOP_VERSION_RK3568)
	5113	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
	5114	+ else
	5115	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
	5116	+ VOP_AFBC_SET(vop2, win, block_split_en, 0);
	5117	+ VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
	5118	+ VOP_AFBC_SET(vop2, win, pic_size, act_info);
	5119	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5120	+ VOP_AFBC_SET(vop2, win, pic_offset, (afbc_xoffset \| src->y1));
	5121	+ VOP_AFBC_SET(vop2, win, dsp_offset, (dst->x1 \| (dst->y1 << 16)));
	5122	+ VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
	5123	+ VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
	5124	+ VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5125	+ VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5126	+ VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
	5127	+ VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
	5128	+ } else {
	5129	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
	5130	+ transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
	5131	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5132	+ VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5133	+ VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5134	+ }
	5135	+
	5136	+ if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
	5137	+ act_info = swahw32(act_info);
	5138	+ actual_w = drm_rect_height(src) >> 16;
	5139	+ actual_h = drm_rect_width(src) >> 16;
	5140	+ }
	5141	+
	5142	+ yrgb_mst = vpstate->yrgb_mst + splice_yrgb_offset;
	5143	+ uv_mst = vpstate->uv_mst + splice_uv_offset;
	5144	+ /* rk3588 should set half_blocK_en to 1 in line and tile mode */
	5145	+ VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
	5146	+
	5147	+ VOP_WIN_SET(vop2, win, format, format);
	5148	+ VOP_WIN_SET(vop2, win, yrgb_mst, yrgb_mst);
	5149	+
	5150	+ rb_swap = vop2_win_rb_swap(fb->format->format);
	5151	+ uv_swap = vop2_win_uv_swap(fb->format->format);
	5152	+ if (vpstate->tiled_en) {
	5153	+ uv_swap = 1;
	5154	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5155	+ stride <<= 3;
	5156	+ else
	5157	+ stride <<= 2;
	5158	+ }
	5159	+ VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
	5160	+ VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
	5161	+
	5162	+ if (fb->format->is_yuv) {
	5163	+ uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
	5164	+ if (vpstate->tiled_en) {
	5165	+ int vsub = fb->format->vsub;
	5166	+
	5167	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5168	+ uv_stride = uv_stride * 8 / vsub;
	5169	+ else
	5170	+ uv_stride = uv_stride * 4 / vsub;
	5171	+ VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
	5172	+ }
	5173	+
	5174	+ VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
	5175	+ VOP_WIN_SET(vop2, win, uv_mst, uv_mst);
	5176	+ }
	5177	+
	5178	+ /* tile 4x4 m0 format, y and uv is packed together */
	5179	+ if (tile_4x4_m0)
	5180	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
	5181	+ else
	5182	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride);
	5183	+
	5184	+ vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
	5185	+ vop2_plane_setup_color_key(&win->base);
	5186	+ VOP_WIN_SET(vop2, win, act_info, act_info);
	5187	+ VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
	5188	+ VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
	5189	+
	5190	+ VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
	5191	+ VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
	5192	+ VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
	5193	+
	5194	+ if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
	5195	+ VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
	5196	+
	5197	+ dither_up = vop2_win_dither_up(fb->format->format);
	5198	+ VOP_WIN_SET(vop2, win, dither_up, dither_up);
	5199	+
	5200	+ VOP_WIN_SET(vop2, win, enable, 1);
	5201	+ if (vop2_cluster_window(win)) {
	5202	+ lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
	5203	+ VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
	5204	+ VOP_CLUSTER_SET(vop2, win, scl_lb_mode, lb_mode == 1 ? 3 : 0);
	5205	+ VOP_CLUSTER_SET(vop2, win, enable, 1);
	5206	+ VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1);
	5207	+ }
	5208	+ spin_unlock(&vop2->reg_lock);
	5209	+}
	5210	+
	5211	+static void vop2_plane_atomic_update(struct drm_plane plane, struct drm_plane_state old_state)
	5212	+{
	5213	+ struct drm_plane_state *pstate = plane->state;
	5214	+ struct drm_crtc *crtc = pstate->crtc;
	5215	+ struct vop2_win *win = to_vop2_win(plane);
	5216	+ struct vop2_win *splice_win;
	5217	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5218	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	5219	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	5220	+ struct drm_framebuffer *fb = pstate->fb;
	5221	+ struct drm_format_name_buf format_name;
	5222	+ struct vop2 *vop2 = win->vop2;
	5223	+ struct drm_rect wsrc;
	5224	+ struct drm_rect wdst;
	5225	+ /* right part in splice mode */
	5226	+ struct drm_rect right_wsrc;
	5227	+ struct drm_rect right_wdst;
	5228	+
3518	5229	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
	5230	+ struct drm_rect *psrc = &vpstate->src;
3519	5231	bool AFBC_flag = false;
3520	5232	struct vop_dump_list *planlist;
3521	5233	unsigned long num_pages;
3522	5234	struct page **pages;
3523		- struct rockchip_drm_fb *rk_fb;
3524	5235	struct drm_gem_object *obj;
3525	5236	struct rockchip_gem_object *rk_obj;
3526	5237
3527	5238	num_pages = 0;
3528	5239	pages = NULL;
3529		- rk_fb = to_rockchip_fb(fb);
3530		- obj = rk_fb->obj[0];
	5240	+ obj = fb->obj[0];
3531	5241	rk_obj = to_rockchip_obj(obj);
3532	5242	if (rk_obj) {
3533	5243	num_pages = rk_obj->num_pages;
..	..	@@ -3566,211 +5276,24 @@
3566	5276	vp->skip_vsync = false;
3567	5277	}
3568	5278
3569		- actual_w = drm_rect_width(src) >> 16;
3570		- actual_h = drm_rect_height(src) >> 16;
3571		- dsp_w = drm_rect_width(dest);
3572		- if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
3573		- DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
3574		- vp->id, win->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
3575		- dsp_w = adjusted_mode->hdisplay - dest->x1;
3576		- if (dsp_w < 4)
3577		- dsp_w = 4;
3578		- actual_w = dsp_w * actual_w / drm_rect_width(dest);
3579		- }
3580		- dsp_h = drm_rect_height(dest);
3581		- if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
3582		- DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
3583		- vp->id, win->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
3584		- dsp_h = adjusted_mode->vdisplay - dest->y1;
3585		- if (dsp_h < 4)
3586		- dsp_h = 4;
3587		- actual_h = dsp_h * actual_h / drm_rect_height(dest);
3588		- }
	5279	+ if (vcstate->splice_mode) {
	5280	+ DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@(%d,%d)] fmt[%.4s%s] addr[%pad]\n",
	5281	+ vp->id, win->name, drm_rect_width(&vpstate->src) >> 16,
	5282	+ drm_rect_height(&vpstate->src) >> 16,
	5283	+ drm_rect_width(&vpstate->dest), drm_rect_height(&vpstate->dest),
	5284	+ vpstate->dest.x1, vpstate->dest.y1,
	5285	+ drm_get_format_name(fb->format->format, &format_name),
	5286	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst);
3589	5287
3590		- /*
3591		- * This is workaround solution for IC design:
3592		- * esmart can't support scale down when actual_w % 16 == 1.
3593		- */
3594		- if (!(win->feature & WIN_FEATURE_AFBDC)) {
3595		- if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
3596		- DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
3597		- actual_w -= 1;
3598		- }
3599		- }
3600		-
3601		- if (vpstate->afbc_en && actual_w % 4) {
3602		- DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
3603		- vp->id, win->name, actual_w);
3604		- actual_w = ALIGN_DOWN(actual_w, 4);
3605		- }
3606		-
3607		- act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
3608		- dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
3609		- stride = DIV_ROUND_UP(fb->pitches[0], 4);
3610		- dsp_stx = dest->x1;
3611		- dsp_sty = dest->y1;
3612		- dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
3613		-
3614		- if (vpstate->tiled_en) {
3615		- if (is_vop3(vop2))
3616		- format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
3617		- else
3618		- format = vop2_convert_tiled_format(fb->format->format);
	5288	+ vop2_calc_drm_rect_for_splice(vpstate, &wsrc, &wdst, &right_wsrc, &right_wdst);
	5289	+ splice_win = win->splice_win;
	5290	+ vop2_win_atomic_update(splice_win, &right_wsrc, &right_wdst, pstate);
3619	5291	} else {
3620		- format = vop2_convert_format(fb->format->format);
	5292	+ memcpy(&wsrc, &vpstate->src, sizeof(struct drm_rect));
	5293	+ memcpy(&wdst, &vpstate->dest, sizeof(struct drm_rect));
3621	5294	}
3622	5295
3623		- vop2_setup_csc_mode(vp, vpstate);
3624		- afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
3625		-
3626		- spin_lock(&vop2->reg_lock);
3627		- DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%.4s%s] addr[%pad] zpos[%d]\n",
3628		- vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
3629		- dsp_stx, dsp_sty,
3630		- drm_get_format_name(fb->format->format, &format_name),
3631		- modifier_to_string(fb->modifier), &vpstate->yrgb_mst, vpstate->zpos);
3632		-
3633		- if (vop2->version != VOP_VERSION_RK3568)
3634		- rk3588_vop2_win_cfg_axi(win);
3635		-
3636		- if (is_vop3(vop2) && !vop2_cluster_window(win))
3637		- VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
3638		-
3639		- if (vpstate->afbc_en) {
3640		- /* the afbc superblock is 16 x 16 */
3641		- afbc_format = vop2_convert_afbc_format(fb->format->format);
3642		- /* Enable color transform for YTR */
3643		- if (fb->modifier & AFBC_FORMAT_MOD_YTR)
3644		- afbc_format \|= (1 << 4);
3645		- afbc_tile_num = ALIGN(actual_w, 16) >> 4;
3646		- /* AFBC pic_vir_width is count by pixel, this is different
3647		- * with WIN_VIR_STRIDE.
3648		- */
3649		- if (!bpp) {
3650		- WARN(1, "bpp is zero\n");
3651		- bpp = 1;
3652		- }
3653		- stride = (fb->pitches[0] << 3) / bpp;
3654		- if ((stride & 0x3f) &&
3655		- (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
3656		- DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
3657		- vp->id, win->name, stride, pstate->rotation);
3658		-
3659		- rb_swap = vop2_afbc_rb_swap(fb->format->format);
3660		- uv_swap = vop2_afbc_uv_swap(fb->format->format);
3661		- /*
3662		- * This is a workaround for crazy IC design, Cluster
3663		- * and Esmart/Smart use different format configuration map:
3664		- * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
3665		- *
3666		- * This is one thing we can make the convert simple:
3667		- * AFBCD decode all the YUV data to YUV444. So we just
3668		- * set all the yuv 10 bit to YUV444_10.
3669		- */
3670		- if (fb->format->is_yuv && (bpp == 10) && (vop2->version == VOP_VERSION_RK3568))
3671		- format = VOP2_CLUSTER_YUV444_10;
3672		-
3673		- vpstate->afbc_half_block_en = afbc_half_block_en;
3674		- transform_offset = vop2_afbc_transform_offset(vpstate);
3675		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
3676		- VOP_AFBC_SET(vop2, win, format, afbc_format);
3677		- VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
3678		- VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
3679		- if (vop2->version == VOP_VERSION_RK3568)
3680		- VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
3681		- else
3682		- VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
3683		- VOP_AFBC_SET(vop2, win, block_split_en, 0);
3684		- VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
3685		- VOP_AFBC_SET(vop2, win, pic_size, act_info);
3686		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3687		- VOP_AFBC_SET(vop2, win, pic_offset, ((src->x1 >> 16) \| src->y1));
3688		- VOP_AFBC_SET(vop2, win, dsp_offset, (dest->x1 \| (dest->y1 << 16)));
3689		- VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
3690		- VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
3691		- VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
3692		- VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
3693		- VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
3694		- VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
3695		- } else {
3696		- VOP_AFBC_SET(vop2, win, enable, 0);
3697		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
3698		- transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
3699		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3700		- VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
3701		- VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
3702		- }
3703		-
3704		- if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
3705		- act_info = swahw32(act_info);
3706		- actual_w = drm_rect_height(src) >> 16;
3707		- actual_h = drm_rect_width(src) >> 16;
3708		- }
3709		- VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
3710		-
3711		- VOP_WIN_SET(vop2, win, format, format);
3712		- VOP_WIN_SET(vop2, win, yrgb_mst, vpstate->yrgb_mst);
3713		-
3714		- rb_swap = vop2_win_rb_swap(fb->format->format);
3715		- uv_swap = vop2_win_uv_swap(fb->format->format);
3716		- if (vpstate->tiled_en) {
3717		- uv_swap = 1;
3718		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3719		- stride <<= 3;
3720		- else
3721		- stride <<= 2;
3722		- }
3723		- VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
3724		- VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
3725		-
3726		- if (fb->format->is_yuv) {
3727		- uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
3728		- if (vpstate->tiled_en) {
3729		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
3730		-
3731		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3732		- uv_stride = uv_stride * 8 / vsub;
3733		- else
3734		- uv_stride = uv_stride * 4 / vsub;
3735		- VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
3736		- }
3737		-
3738		- VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
3739		- VOP_WIN_SET(vop2, win, uv_mst, vpstate->uv_mst);
3740		- }
3741		-
3742		- /* tile 4x4 m0 format, y and uv is packed together */
3743		- if (tile_4x4_m0)
3744		- VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
3745		- else
3746		- VOP_WIN_SET(vop2, win, yrgb_vir, stride);
3747		-
3748		- vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
3749		- vop2_plane_setup_color_key(plane);
3750		- VOP_WIN_SET(vop2, win, act_info, act_info);
3751		- VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
3752		- VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
3753		-
3754		- VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
3755		- VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
3756		- VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
3757		-
3758		- if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
3759		- VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
3760		-
3761		- dither_up = vop2_win_dither_up(fb->format->format);
3762		- VOP_WIN_SET(vop2, win, dither_up, dither_up);
3763		-
3764		- VOP_WIN_SET(vop2, win, enable, 1);
3765		- if (vop2_cluster_window(win)) {
3766		- lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
3767		- VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
3768		- VOP_CLUSTER_SET(vop2, win, enable, 1);
3769		- }
3770		- if (vcstate->output_if & VOP_OUTPUT_IF_BT1120 \|\|
3771		- vcstate->output_if & VOP_OUTPUT_IF_BT656)
3772		- VOP_WIN_SET(vop2, win, yuv_clip, 1);
3773		- spin_unlock(&vop2->reg_lock);
	5296	+ vop2_win_atomic_update(win, &wsrc, &wdst, pstate);
3774	5297
3775	5298	vop2->is_iommu_needed = true;
3776	5299	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
..	..	@@ -3787,18 +5310,18 @@
3787	5310	planlist->dump_info.pages = pages;
3788	5311	planlist->dump_info.offset = vpstate->offset;
3789	5312	planlist->dump_info.pitches = fb->pitches[0];
3790		- planlist->dump_info.height = actual_h;
3791		- planlist->dump_info.pixel_format = fb->format->format;
3792		- list_add_tail(&planlist->entry, &crtc->vop_dump_list_head);
	5313	+ planlist->dump_info.height = drm_rect_height(psrc) >> 16;
	5314	+ planlist->dump_info.format = fb->format;
	5315	+ list_add_tail(&planlist->entry, &vp->rockchip_crtc.vop_dump_list_head);
3793	5316	vpstate->planlist = planlist;
3794	5317	} else {
3795	5318	DRM_ERROR("can't alloc a node of planlist %p\n", planlist);
3796	5319	return;
3797	5320	}
3798		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
3799		- crtc->vop_dump_times > 0) {
3800		- vop_plane_dump(&planlist->dump_info, crtc->frame_count);
3801		- crtc->vop_dump_times--;
	5321	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	5322	+ vp->rockchip_crtc.vop_dump_times > 0) {
	5323	+ rockchip_drm_dump_plane_buffer(&planlist->dump_info, vp->rockchip_crtc.frame_count);
	5324	+ vp->rockchip_crtc.vop_dump_times--;
3802	5325	}
3803	5326	#endif
3804	5327	}
..	..	@@ -3944,11 +5467,8 @@
3944	5467	if (!vpstate)
3945	5468	return;
3946	5469
3947		- plane->state = &vpstate->base;
3948		- plane->state->plane = plane;
3949		- plane->state->zpos = win->zpos;
3950		- plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;
3951		- plane->state->rotation = DRM_MODE_ROTATE_0;
	5470	+ __drm_atomic_helper_plane_reset(plane, &vpstate->base);
	5471	+ vpstate->base.zpos = win->zpos;
3952	5472	}
3953	5473
3954	5474	static struct drm_plane_state vop2_atomic_plane_duplicate_state(struct drm_plane plane)
..	..	@@ -4136,6 +5656,192 @@
4136	5656	spin_unlock_irqrestore(&drm->event_lock, flags);
4137	5657	}
4138	5658
	5659	+static bool vop2_crtc_line_flag_irq_is_enabled(struct vop2_video_port *vp)
	5660	+{
	5661	+ struct vop2 *vop2 = vp->vop2;
	5662	+ const struct vop2_data *vop2_data = vop2->data;
	5663	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5664	+ const struct vop_intr *intr = vp_data->intr;
	5665	+ uint32_t line_flag_irq;
	5666	+ unsigned long flags;
	5667	+
	5668	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5669	+ line_flag_irq = VOP_INTR_GET_TYPE(vop2, intr, enable, LINE_FLAG_INTR);
	5670	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5671	+
	5672	+ return !!line_flag_irq;
	5673	+}
	5674	+
	5675	+static void vop2_crtc_line_flag_irq_enable(struct vop2_video_port *vp)
	5676	+{
	5677	+ struct vop2 *vop2 = vp->vop2;
	5678	+ const struct vop2_data *vop2_data = vop2->data;
	5679	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5680	+ const struct vop_intr *intr = vp_data->intr;
	5681	+ unsigned long flags;
	5682	+
	5683	+ if (!vop2->is_enabled)
	5684	+ return;
	5685	+
	5686	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5687	+ VOP_INTR_SET_TYPE(vop2, intr, clear, LINE_FLAG_INTR, 1);
	5688	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 1);
	5689	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5690	+}
	5691	+
	5692	+static void vop2_crtc_line_flag_irq_disable(struct vop2_video_port *vp)
	5693	+{
	5694	+ struct vop2 *vop2 = vp->vop2;
	5695	+ const struct vop2_data *vop2_data = vop2->data;
	5696	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5697	+ const struct vop_intr *intr = vp_data->intr;
	5698	+ unsigned long flags;
	5699	+
	5700	+ if (!vop2->is_enabled)
	5701	+ return;
	5702	+
	5703	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5704	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 0);
	5705	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5706	+}
	5707	+
	5708	+static void vop3_mcu_mode_setup(struct drm_crtc *crtc)
	5709	+{
	5710	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5711	+ struct vop2 *vop2 = vp->vop2;
	5712	+
	5713	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5714	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5715	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, vp->mcu_timing.mcu_pix_total);
	5716	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, vp->mcu_timing.mcu_cs_pst);
	5717	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, vp->mcu_timing.mcu_cs_pend);
	5718	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, vp->mcu_timing.mcu_rw_pst);
	5719	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, vp->mcu_timing.mcu_rw_pend);
	5720	+}
	5721	+
	5722	+static void vop3_mcu_bypass_mode_setup(struct drm_crtc *crtc)
	5723	+{
	5724	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5725	+ struct vop2 *vop2 = vp->vop2;
	5726	+
	5727	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5728	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5729	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, 53);
	5730	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, 6);
	5731	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, 48);
	5732	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, 12);
	5733	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, 30);
	5734	+}
	5735	+
	5736	+static u32 vop3_mode_done(struct vop2_video_port *vp)
	5737	+{
	5738	+ return VOP_MODULE_GET(vp->vop2, vp, out_mode);
	5739	+}
	5740	+
	5741	+static void vop3_set_out_mode(struct drm_crtc *crtc, u32 out_mode)
	5742	+{
	5743	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5744	+ struct vop2 *vop2 = vp->vop2;
	5745	+ int ret;
	5746	+ u32 val;
	5747	+
	5748	+ VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
	5749	+ vop2_cfg_done(crtc);
	5750	+ ret = readx_poll_timeout(vop3_mode_done, vp, val, val == out_mode,
	5751	+ 1000, 500 * 1000);
	5752	+ if (ret)
	5753	+ dev_err(vop2->dev, "wait mode 0x%x timeout\n", out_mode);
	5754	+}
	5755	+
	5756	+static void vop3_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value)
	5757	+{
	5758	+ struct drm_crtc_state *crtc_state;
	5759	+ struct drm_display_mode *adjusted_mode;
	5760	+ struct vop2_video_port *vp;
	5761	+ struct vop2 *vop2;
	5762	+
	5763	+ if (!crtc)
	5764	+ return;
	5765	+
	5766	+ crtc_state = crtc->state;
	5767	+ adjusted_mode = &crtc_state->adjusted_mode;
	5768	+ vp = to_vop2_video_port(crtc);
	5769	+ vop2 = vp->vop2;
	5770	+
	5771	+ /*
	5772	+ * 1.set mcu bypass mode timing.
	5773	+ * 2.set dclk rate to 150M.
	5774	+ */
	5775	+ if ((type == MCU_SETBYPASS) && value) {
	5776	+ vop3_mcu_bypass_mode_setup(crtc);
	5777	+ clk_set_rate(vp->dclk, 150000000);
	5778	+ }
	5779	+
	5780	+ mutex_lock(&vop2->vop2_lock);
	5781	+ if (vop2 && vop2->is_enabled) {
	5782	+ switch (type) {
	5783	+ case MCU_WRCMD:
	5784	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 0);
	5785	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5786	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5787	+ break;
	5788	+ case MCU_WRDATA:
	5789	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5790	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5791	+ break;
	5792	+ case MCU_SETBYPASS:
	5793	+ VOP_MODULE_SET(vop2, vp, mcu_bypass, value ? 1 : 0);
	5794	+ break;
	5795	+ default:
	5796	+ break;
	5797	+ }
	5798	+ }
	5799	+ mutex_unlock(&vop2->vop2_lock);
	5800	+
	5801	+ /*
	5802	+ * 1.restore mcu data mode timing.
	5803	+ * 2.restore dclk rate to crtc_clock.
	5804	+ */
	5805	+ if ((type == MCU_SETBYPASS) && !value) {
	5806	+ vop3_mcu_mode_setup(crtc);
	5807	+ clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	5808	+ }
	5809	+}
	5810	+
	5811	+static int vop2_crtc_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
	5812	+{
	5813	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5814	+ struct vop2 *vop2 = vp->vop2;
	5815	+ unsigned long jiffies_left;
	5816	+ int ret = 0;
	5817	+
	5818	+ if (!vop2->is_enabled)
	5819	+ return -ENODEV;
	5820	+
	5821	+ mutex_lock(&vop2->vop2_lock);
	5822	+
	5823	+ if (vop2_crtc_line_flag_irq_is_enabled(vp)) {
	5824	+ ret = -EBUSY;
	5825	+ goto out;
	5826	+ }
	5827	+
	5828	+ reinit_completion(&vp->line_flag_completion);
	5829	+ vop2_crtc_line_flag_irq_enable(vp);
	5830	+ jiffies_left = wait_for_completion_timeout(&vp->line_flag_completion,
	5831	+ msecs_to_jiffies(mstimeout));
	5832	+ vop2_crtc_line_flag_irq_disable(vp);
	5833	+
	5834	+ if (jiffies_left == 0) {
	5835	+ DRM_DEV_ERROR(vop2->dev, "timeout waiting for lineflag IRQ\n");
	5836	+ ret = -ETIMEDOUT;
	5837	+ goto out;
	5838	+ }
	5839	+
	5840	+out:
	5841	+ mutex_unlock(&vop2->vop2_lock);
	5842	+ return ret;
	5843	+}
	5844	+
4139	5845	static int vop2_crtc_enable_line_flag_event(struct drm_crtc *crtc, uint32_t line)
4140	5846	{
4141	5847	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -4179,20 +5885,69 @@
4179	5885	spin_unlock_irqrestore(&vop2->irq_lock, flags);
4180	5886	}
4181	5887
4182		-
4183	5888	static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on)
4184	5889	{
4185	5890	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5891	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4186	5892	struct vop2 *vop2 = vp->vop2;
4187	5893	struct rockchip_drm_private *private = crtc->dev->dev_private;
	5894	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	5895	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	5896	+ struct drm_crtc_state *crtc_state;
	5897	+ struct drm_display_mode *mode;
	5898	+ struct vop2_win win, splice_win;
	5899	+ struct vop2_extend_pll *ext_pll;
	5900	+ struct clk *parent_clk;
	5901	+ const char *clk_name;
4188	5902
4189	5903	if (on == vp->loader_protect)
4190	5904	return 0;
4191	5905
4192	5906	if (on) {
	5907	+ vp->loader_protect = true;
4193	5908	vop2->active_vp_mask \|= BIT(vp->id);
4194	5909	vop2_set_system_status(vop2);
4195	5910	vop2_initial(crtc);
	5911	+ if (crtc->primary) {
	5912	+ win = to_vop2_win(crtc->primary);
	5913	+ if (VOP_WIN_GET(vop2, win, enable)) {
	5914	+ if (win->pd) {
	5915	+ win->pd->ref_count++;
	5916	+ win->pd->vp_mask \|= BIT(vp->id);
	5917	+ }
	5918	+
	5919	+ crtc_state = drm_atomic_get_crtc_state(crtc->state->state, crtc);
	5920	+ mode = &crtc_state->adjusted_mode;
	5921	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	5922	+ vcstate->splice_mode = true;
	5923	+ splice_win = vop2_find_win_by_phys_id(vop2,
	5924	+ win->splice_win_id);
	5925	+ splice_win->splice_mode_right = true;
	5926	+ splice_win->left_win = win;
	5927	+ win->splice_win = splice_win;
	5928	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	5929	+ splice_win->vp_mask = BIT(splice_vp->id);
	5930	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	5931	+
	5932	+ if (splice_win->pd &&
	5933	+ VOP_WIN_GET(vop2, splice_win, enable)) {
	5934	+ splice_win->pd->ref_count++;
	5935	+ splice_win->pd->vp_mask \|= BIT(splice_vp->id);
	5936	+ }
	5937	+ }
	5938	+ }
	5939	+ }
	5940	+ parent_clk = clk_get_parent(vp->dclk);
	5941	+ clk_name = __clk_get_name(parent_clk);
	5942	+ if (!strcmp(clk_name, "clk_hdmiphy_pixel0")) {
	5943	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	5944	+ if (ext_pll)
	5945	+ ext_pll->vp_mask \|= BIT(vp->id);
	5946	+ } else if (!strcmp(clk_name, "clk_hdmiphy_pixel1")) {
	5947	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	5948	+ if (ext_pll)
	5949	+ ext_pll->vp_mask \|= BIT(vp->id);
	5950	+ }
4196	5951	drm_crtc_vblank_on(crtc);
4197	5952	if (private->cubic_lut[vp->id].enable) {
4198	5953	dma_addr_t cubic_lut_mst;
..	..	@@ -4201,10 +5956,8 @@
4201	5956	cubic_lut_mst = cubic_lut->offset + private->cubic_lut_dma_addr;
4202	5957	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
4203	5958	}
4204		- vp->loader_protect = true;
4205	5959	} else {
4206	5960	vop2_crtc_atomic_disable(crtc, NULL);
4207		- vp->loader_protect = false;
4208	5961	}
4209	5962
4210	5963	return 0;
..	..	@@ -4226,6 +5979,10 @@
4226	5979	struct drm_rect src, dest;
4227	5980	struct drm_framebuffer *fb = pstate->fb;
4228	5981	struct drm_format_name_buf format_name;
	5982	+ struct drm_gem_object *obj;
	5983	+ struct rockchip_gem_object *rk_obj;
	5984	+ dma_addr_t fb_addr;
	5985	+
4229	5986	int i;
4230	5987
4231	5988	DEBUG_PRINT(" %s: %s\n", win->name, pstate->crtc ? "ACTIVE" : "DISABLED");
..	..	@@ -4256,8 +6013,10 @@
4256	6013	DEBUG_PRINT("\tdst: pos[%d, %d] rect[%d x %d]\n", dest->x1, dest->y1,
4257	6014	drm_rect_width(dest), drm_rect_height(dest));
4258	6015
4259		- for (i = 0; i < drm_format_num_planes(fb->format->format); i++) {
4260		- dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
	6016	+ for (i = 0; i < fb->format->num_planes; i++) {
	6017	+ obj = fb->obj[0];
	6018	+ rk_obj = to_rockchip_obj(obj);
	6019	+ fb_addr = rk_obj->dma_addr + fb->offsets[0];
4261	6020
4262	6021	DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
4263	6022	i, &fb_addr, fb->pitches[i], fb->offsets[i]);
..	..	@@ -4337,8 +6096,8 @@
4337	6096
4338	6097	/* only need to dump once at first active crtc for vop2 */
4339	6098	for (i = 0; i < vop2_data->nr_vps; i++) {
4340		- if (vop2->vps[i].crtc.state->active) {
4341		- first_active_crtc = &vop2->vps[i].crtc;
	6099	+ if (vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6100	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4342	6101	break;
4343	6102	}
4344	6103	}
..	..	@@ -4380,8 +6139,8 @@
4380	6139
4381	6140	/* only need to dump once at first active crtc for vop2 */
4382	6141	for (i = 0; i < vop2_data->nr_vps; i++) {
4383		- if (vop2->vps[i].crtc.state->active) {
4384		- first_active_crtc = &vop2->vps[i].crtc;
	6142	+ if (vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6143	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4385	6144	break;
4386	6145	}
4387	6146	}
..	..	@@ -4417,7 +6176,7 @@
4417	6176	struct vop2_video_port *vp = &vop2->vps[i];
4418	6177
4419	6178	if (!vp->lut \|\| !vp->gamma_lut_active \|\|
4420		- !vop2->lut_regs \|\| !vp->crtc.state->enable) {
	6179	+ !vop2->lut_regs \|\| !vp->rockchip_crtc.crtc.state->enable) {
4421	6180	DEBUG_PRINT("Video port%d gamma disabled\n", vp->id);
4422	6181	continue;
4423	6182	}
..	..	@@ -4444,7 +6203,7 @@
4444	6203	struct vop2_video_port *vp = &vop2->vps[i];
4445	6204
4446	6205	if ((!vp->cubic_lut_gem_obj && !private->cubic_lut[vp->id].enable) \|\|
4447		- !vp->cubic_lut \|\| !vp->crtc.state->enable) {
	6206	+ !vp->cubic_lut \|\| !vp->rockchip_crtc.crtc.state->enable) {
4448	6207	DEBUG_PRINT("Video port%d cubic lut disabled\n", vp->id);
4449	6208	continue;
4450	6209	}
..	..	@@ -4487,24 +6246,17 @@
4487	6246	goto remove;
4488	6247	}
4489	6248	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4490		- drm_debugfs_vop_add(crtc, vop2->debugfs);
	6249	+ rockchip_drm_add_dump_buffer(crtc, vop2->debugfs);
	6250	+ rockchip_drm_debugfs_add_color_bar(crtc, vop2->debugfs);
4491	6251	#endif
4492	6252	for (i = 0; i < ARRAY_SIZE(vop2_debugfs_files); i++)
4493	6253	vop2->debugfs_files[i].data = vop2;
4494	6254
4495		- ret = drm_debugfs_create_files(vop2->debugfs_files,
4496		- ARRAY_SIZE(vop2_debugfs_files),
4497		- vop2->debugfs,
4498		- minor);
4499		- if (ret) {
4500		- dev_err(vop2->dev, "could not install rockchip_debugfs_list\n");
4501		- goto free;
4502		- }
4503		-
	6255	+ drm_debugfs_create_files(vop2->debugfs_files,
	6256	+ ARRAY_SIZE(vop2_debugfs_files),
	6257	+ vop2->debugfs,
	6258	+ minor);
4504	6259	return 0;
4505		-free:
4506		- kfree(vop2->debugfs_files);
4507		- vop2->debugfs_files = NULL;
4508	6260	remove:
4509	6261	debugfs_remove(vop2->debugfs);
4510	6262	vop2->debugfs = NULL;
..	..	@@ -4512,29 +6264,59 @@
4512	6264	}
4513	6265
4514	6266	static enum drm_mode_status
4515		-vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode,
4516		- int output_type)
	6267	+vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode)
4517	6268	{
	6269	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4518	6270	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4519	6271	struct vop2 *vop2 = vp->vop2;
4520	6272	const struct vop2_data *vop2_data = vop2->data;
4521	6273	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4522	6274	int request_clock = mode->clock;
4523	6275	int clock;
	6276	+ unsigned long aclk_rate;
	6277	+ uint8_t active_vp_mask = vop2->active_vp_mask;
	6278	+
	6279	+ /*
	6280	+ * For RK3588, VP0 and VP1 will be both used in splice mode. All display
	6281	+ * modes of the right VP should be set as invalid when vop2 is working in
	6282	+ * splice mode.
	6283	+ */
	6284	+ if (vp->splice_mode_right)
	6285	+ return MODE_BAD;
	6286	+
	6287	+ if ((active_vp_mask & BIT(ROCKCHIP_VOP_VP1)) && !vcstate->splice_mode &&
	6288	+ mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	6289	+ DRM_DEV_DEBUG(vop2->dev, "can not support resolution %dx%d, vp1 is busy\n",
	6290	+ mode->hdisplay, mode->vdisplay);
	6291	+ return MODE_BAD;
	6292	+ }
4524	6293
4525	6294	if (mode->hdisplay > vp_data->max_output.width)
4526	6295	return MODE_BAD_HVALUE;
4527	6296
4528		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6297	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4529	6298	request_clock *= 2;
4530	6299
4531		- clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
	6300	+ aclk_rate = clk_get_rate(vop2->aclk) / 1000;
	6301	+
	6302	+ if (request_clock > VOP2_MAX_DCLK_RATE && aclk_rate <= VOP2_COMMON_ACLK_RATE)
	6303	+ return MODE_BAD;
	6304	+
	6305	+ if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
	6306	+ (vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") \|\|
	6307	+ vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"))) {
	6308	+ clock = request_clock;
	6309	+ } else {
	6310	+ if (request_clock > VOP2_MAX_DCLK_RATE)
	6311	+ request_clock = request_clock >> 2;
	6312	+ clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
	6313	+ }
4532	6314
4533	6315	/*
4534	6316	* Hdmi or DisplayPort request a Accurate clock.
4535	6317	*/
4536		- if (output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
4537		- output_type == DRM_MODE_CONNECTOR_DisplayPort)
	6318	+ if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
	6319	+ vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort)
4538	6320	if (clock != request_clock)
4539	6321	return MODE_CLOCK_RANGE;
4540	6322
..	..	@@ -4561,7 +6343,7 @@
4561	6343	struct drm_framebuffer *fb = pstate->fb;
4562	6344	struct drm_rect *dst = &vpstate->dest;
4563	6345	struct drm_rect *src = &vpstate->src;
4564		- int bpp = fb->format->bpp[0];
	6346	+ int bpp = rockchip_drm_get_bpp(fb->format);
4565	6347	int src_width = drm_rect_width(src) >> 16;
4566	6348	int src_height = drm_rect_height(src) >> 16;
4567	6349	int dst_width = drm_rect_width(dst);
..	..	@@ -4609,10 +6391,9 @@
4609	6391
4610	6392	static size_t vop2_crtc_bandwidth(struct drm_crtc *crtc,
4611	6393	struct drm_crtc_state *crtc_state,
4612		- size_t *frame_bw_mbyte,
4613		- unsigned int *plane_num_total)
	6394	+ struct dmcfreq_vop_info *vop_bw_info)
4614	6395	{
4615		- struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
	6396	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
4616	6397	uint16_t htotal = adjusted_mode->crtc_htotal;
4617	6398	uint16_t vdisplay = adjusted_mode->crtc_vdisplay;
4618	6399	int clock = adjusted_mode->crtc_clock;
..	..	@@ -4621,44 +6402,49 @@
4621	6402	struct drm_plane_state *pstate;
4622	6403	struct vop2_bandwidth *pbandwidth;
4623	6404	struct drm_plane *plane;
4624		- uint64_t line_bandwidth;
	6405	+ u64 line_bw_mbyte = 0;
4625	6406	int8_t cnt = 0, plane_num = 0;
	6407	+ int i = 0;
4626	6408	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4627	6409	struct vop_dump_list pos, n;
	6410	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
4628	6411	#endif
4629	6412
4630	6413	if (!htotal \|\| !vdisplay)
4631	6414	return 0;
4632	6415
4633	6416	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4634		- if (!crtc->vop_dump_list_init_flag) {
4635		- INIT_LIST_HEAD(&crtc->vop_dump_list_head);
4636		- crtc->vop_dump_list_init_flag = true;
	6417	+ if (!vp->rockchip_crtc.vop_dump_list_init_flag) {
	6418	+ INIT_LIST_HEAD(&vp->rockchip_crtc.vop_dump_list_head);
	6419	+ vp->rockchip_crtc.vop_dump_list_init_flag = true;
4637	6420	}
4638		- list_for_each_entry_safe(pos, n, &crtc->vop_dump_list_head, entry) {
	6421	+ list_for_each_entry_safe(pos, n, &vp->rockchip_crtc.vop_dump_list_head, entry) {
4639	6422	list_del(&pos->entry);
4640	6423	}
4641		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
4642		- crtc->vop_dump_times > 0) {
4643		- crtc->frame_count++;
	6424	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	6425	+ vp->rockchip_crtc.vop_dump_times > 0) {
	6426	+ vp->rockchip_crtc.frame_count++;
4644	6427	}
4645	6428	#endif
4646	6429
4647		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
4648		- plane_num++;
	6430	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6431	+ if (pstate->crtc == crtc)
	6432	+ plane_num++;
	6433	+ }
4649	6434
4650		- if (plane_num_total)
4651		- *plane_num_total += plane_num;
	6435	+ vop_bw_info->plane_num += plane_num;
4652	6436	pbandwidth = kmalloc_array(plane_num, sizeof(*pbandwidth),
4653	6437	GFP_KERNEL);
4654	6438	if (!pbandwidth)
4655	6439	return -ENOMEM;
4656		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
4657		- int act_w, act_h, bpp, afbc_fac;
4658	6440
4659		- pstate = drm_atomic_get_new_plane_state(state, plane);
	6441	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6442	+ int act_w, act_h, bpp, afbc_fac;
	6443	+ int fps = drm_mode_vrefresh(adjusted_mode);
	6444	+
4660	6445	if (!pstate \|\| pstate->crtc != crtc \|\| !pstate->fb)
4661	6446	continue;
	6447	+
4662	6448	/* This is an empirical value, if it's afbc format, the frame buffer size div 2 */
4663	6449	afbc_fac = rockchip_afbc(plane, pstate->fb->modifier) ? 2 : 1;
4664	6450
..	..	@@ -4669,24 +6455,25 @@
4669	6455
4670	6456	act_w = drm_rect_width(&pstate->src) >> 16;
4671	6457	act_h = drm_rect_height(&pstate->src) >> 16;
4672		- bpp = pstate->fb->format->bpp[0];
	6458	+ bpp = rockchip_drm_get_bpp(pstate->fb->format);
4673	6459
4674		- frame_bw_mbyte += act_w act_h / 1000 * bpp / 8 * adjusted_mode->vrefresh / afbc_fac / 1000;
	6460	+ vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000;
4675	6461	}
4676	6462
4677	6463	sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop2_bandwidth_cmp, NULL);
4678	6464
4679		- line_bandwidth = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
	6465	+ line_bw_mbyte = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
4680	6466	kfree(pbandwidth);
4681	6467	/*
4682	6468	* line_bandwidth(MB/s)
4683		- * = line_bandwidth(Byte) / line_time(s)
	6469	+ * = line_bandwidth / line_time
4684	6470	* = line_bandwidth(Byte) * clock(KHZ) / 1000 / htotal
4685	6471	*/
4686		- line_bandwidth *= clock;
4687		- do_div(line_bandwidth, htotal * 1000);
	6472	+ line_bw_mbyte *= clock;
	6473	+ do_div(line_bw_mbyte, htotal * 1000);
	6474	+ vop_bw_info->line_bw_mbyte = line_bw_mbyte;
4688	6475
4689		- return line_bandwidth;
	6476	+ return 0;
4690	6477	}
4691	6478
4692	6479	static void vop2_crtc_close(struct drm_crtc *crtc)
..	..	@@ -4718,6 +6505,44 @@
4718	6505	VOP_MODULE_SET(vop2, vp, edpi_wms_fs, 1);
4719	6506	}
4720	6507
	6508	+static int vop2_crtc_set_color_bar(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode)
	6509	+{
	6510	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6511	+ struct vop2 *vop2 = vp->vop2;
	6512	+ int ret = 0;
	6513	+
	6514	+ if (!crtc->state->active) {
	6515	+ DRM_INFO("Video port%d disabled\n", vp->id);
	6516	+ return -EINVAL;
	6517	+ }
	6518	+
	6519	+ switch (mode) {
	6520	+ case ROCKCHIP_COLOR_BAR_OFF:
	6521	+ DRM_INFO("disable color bar in VP%d\n", vp->id);
	6522	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 0);
	6523	+ vop2_cfg_done(crtc);
	6524	+ break;
	6525	+ case ROCKCHIP_COLOR_BAR_HORIZONTAL:
	6526	+ DRM_INFO("enable horizontal color bar in VP%d\n", vp->id);
	6527	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 0);
	6528	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6529	+ vop2_cfg_done(crtc);
	6530	+ break;
	6531	+ case ROCKCHIP_COLOR_BAR_VERTICAL:
	6532	+ DRM_INFO("enable vertical color bar in VP%d\n", vp->id);
	6533	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 1);
	6534	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6535	+ vop2_cfg_done(crtc);
	6536	+ break;
	6537	+ default:
	6538	+ DRM_INFO("Unsupported color bar mode\n");
	6539	+ ret = -EINVAL;
	6540	+ break;
	6541	+ }
	6542	+
	6543	+ return ret;
	6544	+}
	6545	+
4721	6546	static const struct rockchip_crtc_funcs private_crtc_funcs = {
4722	6547	.loader_protect = vop2_crtc_loader_protect,
4723	6548	.cancel_pending_vblank = vop2_crtc_cancel_pending_vblank,
..	..	@@ -4725,10 +6550,13 @@
4725	6550	.debugfs_dump = vop2_crtc_debugfs_dump,
4726	6551	.regs_dump = vop2_crtc_regs_dump,
4727	6552	.active_regs_dump = vop2_crtc_active_regs_dump,
4728		- .mode_valid = vop2_crtc_mode_valid,
4729	6553	.bandwidth = vop2_crtc_bandwidth,
4730	6554	.crtc_close = vop2_crtc_close,
4731	6555	.te_handler = vop2_crtc_te_handler,
	6556	+ .crtc_send_mcu_cmd = vop3_crtc_send_mcu_cmd,
	6557	+ .wait_vact_end = vop2_crtc_wait_vact_end,
	6558	+ .crtc_standby = vop2_crtc_standby,
	6559	+ .crtc_set_color_bar = vop2_crtc_set_color_bar,
4732	6560	};
4733	6561
4734	6562	static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
..	..	@@ -4736,15 +6564,58 @@
4736	6564	struct drm_display_mode *adj_mode)
4737	6565	{
4738	6566	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6567	+ struct vop2 *vop2 = vp->vop2;
	6568	+ struct drm_connector *connector;
	6569	+ struct drm_connector_list_iter conn_iter;
	6570	+ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
	6571	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(new_crtc_state);
	6572	+
	6573	+ /*
	6574	+ * For RK3568 and RK3588, the hactive of video timing must
	6575	+ * be 4-pixel aligned.
	6576	+ */
	6577	+ if (vop2->version == VOP_VERSION_RK3568 \|\| vop2->version == VOP_VERSION_RK3588) {
	6578	+ if (adj_mode->hdisplay % 4) {
	6579	+ u16 old_hdisplay = adj_mode->hdisplay;
	6580	+ u16 align;
	6581	+
	6582	+ align = 4 - (adj_mode->hdisplay % 4);
	6583	+ adj_mode->hdisplay += align;
	6584	+ adj_mode->hsync_start += align;
	6585	+ adj_mode->hsync_end += align;
	6586	+ adj_mode->htotal += align;
	6587	+
	6588	+ DRM_WARN("VP%d: hactive need to be aligned with 4-pixel, %d -> %d\n",
	6589	+ vp->id, old_hdisplay, adj_mode->hdisplay);
	6590	+ }
	6591	+ }
4739	6592
4740	6593	drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V \| CRTC_STEREO_DOUBLE);
4741	6594
4742		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6595	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4743	6596	adj_mode->crtc_clock *= 2;
4744	6597
4745		- adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
4746		- adj_mode->crtc_clock * 1000), 1000);
	6598	+ if (vp->mcu_timing.mcu_pix_total) {
	6599	+ if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888)
	6600	+ adj_mode->crtc_clock *= 3;
	6601	+ else if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888_DUMMY)
	6602	+ adj_mode->crtc_clock *= 4;
	6603	+ }
4747	6604
	6605	+ drm_connector_list_iter_begin(crtc->dev, &conn_iter);
	6606	+ drm_for_each_connector_iter(connector, &conn_iter) {
	6607	+ if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) &&
	6608	+ ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) \|\|
	6609	+ (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) {
	6610	+ drm_connector_list_iter_end(&conn_iter);
	6611	+ return true;
	6612	+ }
	6613	+ }
	6614	+ drm_connector_list_iter_end(&conn_iter);
	6615	+
	6616	+ if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE)
	6617	+ adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
	6618	+ adj_mode->crtc_clock * 1000), 1000);
4748	6619	return true;
4749	6620	}
4750	6621
..	..	@@ -4763,24 +6634,25 @@
4763	6634	case MEDIA_BUS_FMT_RGB666_1X18:
4764	6635	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
4765	6636	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
4766		- case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
4767	6637	VOP_MODULE_SET(vop2, vp, dither_down_en, 1);
4768	6638	VOP_MODULE_SET(vop2, vp, dither_down_mode, RGB888_TO_RGB666);
4769	6639	VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
4770	6640	break;
	6641	+ case MEDIA_BUS_FMT_YUYV8_1X16:
4771	6642	case MEDIA_BUS_FMT_YUV8_1X24:
4772	6643	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
4773	6644	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4774	6645	VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
4775	6646	break;
	6647	+ case MEDIA_BUS_FMT_YUYV10_1X20:
4776	6648	case MEDIA_BUS_FMT_YUV10_1X30:
4777	6649	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
4778	6650	case MEDIA_BUS_FMT_RGB101010_1X30:
4779	6651	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4780	6652	VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0);
4781	6653	break;
4782		- case MEDIA_BUS_FMT_SRGB888_3X8:
4783		- case MEDIA_BUS_FMT_SRGB888_DUMMY_4X8:
	6654	+ case MEDIA_BUS_FMT_RGB888_3X8:
	6655	+ case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
4784	6656	case MEDIA_BUS_FMT_RGB888_1X24:
4785	6657	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
4786	6658	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
..	..	@@ -4799,6 +6671,8 @@
4799	6671	to_rockchip_crtc_state(crtc->state);
4800	6672	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4801	6673	struct vop2 *vop2 = vp->vop2;
	6674	+ const struct vop2_data *vop2_data = vop2->data;
	6675	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4802	6676	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
4803	6677	u16 vtotal = mode->crtc_vtotal;
4804	6678	u16 hdisplay = mode->crtc_hdisplay;
..	..	@@ -4838,8 +6712,16 @@
4838	6712	val = vact_st_f1 << 16 \| vact_end_f1;
4839	6713	VOP_MODULE_SET(vop2, vp, vpost_st_end_f1, val);
4840	6714	}
4841		- VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y,
4842		- is_yuv_output(vcstate->bus_format));
	6715	+
	6716	+ /*
	6717	+ * BCSH[R2Y] -> POST Linebuffer[post scale] -> the background R2Y will be deal by post_dsp_out_r2y
	6718	+ *
	6719	+ * POST Linebuffer[post scale] -> ACM[R2Y] -> the background R2Y will be deal by ACM[R2Y]
	6720	+ */
	6721	+ if (vp_data->feature & VOP_FEATURE_POST_ACM)
	6722	+ VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y, vcstate->yuv_overlay);
	6723	+ else
	6724	+ VOP_MODULE_SET(vop2, vp, post_dsp_out_r2y, is_yuv_output(vcstate->bus_format));
4843	6725	}
4844	6726
4845	6727	/*
..	..	@@ -4866,13 +6748,13 @@
4866	6748	u16 vact_end = vact_st + vdisplay;
4867	6749	u32 htotal_sync = htotal << 16 \| hsync_len;
4868	6750	u32 hactive_st_end = hact_st << 16 \| hact_end;
4869		- u32 vtotal_sync = vtotal << 16 \| vsync_len;
4870	6751	u32 vactive_st_end = vact_st << 16 \| vact_end;
4871	6752	u32 crtc_clock = adjusted_mode->crtc_clock * 100;
4872	6753
4873	6754	if (htotal_sync != VOP_MODULE_GET(vop2, vp, htotal_pw) \|\|
4874	6755	hactive_st_end != VOP_MODULE_GET(vop2, vp, hact_st_end) \|\|
4875		- vtotal_sync != VOP_MODULE_GET(vop2, vp, vtotal_pw) \|\|
	6756	+ vtotal != VOP_MODULE_GET(vop2, vp, dsp_vtotal) \|\|
	6757	+ vsync_len != VOP_MODULE_GET(vop2, vp, dsp_vs_end) \|\|
4876	6758	vactive_st_end != VOP_MODULE_GET(vop2, vp, vact_st_end) \|\|
4877	6759	crtc_clock != clk_get_rate(vp->dclk))
4878	6760	return true;
..	..	@@ -4880,15 +6762,706 @@
4880	6762	return false;
4881	6763	}
4882	6764
	6765	+static int vop2_cru_set_rate(struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	6766	+{
	6767	+ int ret = 0;
	6768	+
	6769	+ if (if_pixclk) {
	6770	+ ret = clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate);
	6771	+ if (ret < 0) {
	6772	+ DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n",
	6773	+ clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret);
	6774	+ return ret;
	6775	+ }
	6776	+ }
	6777	+
	6778	+ if (if_dclk) {
	6779	+ ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate);
	6780	+ if (ret < 0)
	6781	+ DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n",
	6782	+ clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret);
	6783	+ }
	6784	+
	6785	+ return ret;
	6786	+}
	6787	+
	6788	+static int vop2_set_dsc_clk(struct drm_crtc *crtc, u8 dsc_id)
	6789	+{
	6790	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6791	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6792	+ struct vop2 *vop2 = vp->vop2;
	6793	+ const struct vop2_data *vop2_data = vop2->data;
	6794	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	6795	+ struct vop2_clk dsc_txp_clk, dsc_pxl_clk, dsc_cds_clk, dsc_txp_clk_parent;
	6796	+ char clk_name[32];
	6797	+ int ret = 0;
	6798	+
	6799	+ /* set clk parent */
	6800	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	6801	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_src_name);
	6802	+ dsc_txp_clk_parent = vop2_clk_get(vop2, clk_name);
	6803	+ if (!dsc_txp_clk \|\| !dsc_txp_clk_parent) {
	6804	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc clk\n");
	6805	+ return -ENODEV;
	6806	+ }
	6807	+ ret = clk_set_parent(dsc_txp_clk->hw.clk, dsc_txp_clk_parent->hw.clk);
	6808	+ if (ret < 0) {
	6809	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	6810	+ __clk_get_name(dsc_txp_clk_parent->hw.clk),
	6811	+ __clk_get_name(dsc_txp_clk->hw.clk), ret);
	6812	+ return ret;
	6813	+ }
	6814	+
	6815	+ /* set dsc txp clk rate */
	6816	+ clk_set_rate(dsc_txp_clk->hw.clk, vcstate->dsc_txp_clk_rate);
	6817	+
	6818	+ /* set dsc pxl clk rate */
	6819	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	6820	+ if (!dsc_pxl_clk) {
	6821	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_pxl_clk\n");
	6822	+ return -ENODEV;
	6823	+ }
	6824	+ clk_set_rate(dsc_pxl_clk->hw.clk, vcstate->dsc_pxl_clk_rate);
	6825	+
	6826	+ /* set dsc cds clk rate */
	6827	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	6828	+ if (!dsc_cds_clk) {
	6829	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_cds_clk\n");
	6830	+ return -ENODEV;
	6831	+ }
	6832	+ clk_set_rate(dsc_cds_clk->hw.clk, vcstate->dsc_cds_clk_rate);
	6833	+
	6834	+ return 0;
	6835	+}
	6836	+
	6837	+static int vop2_calc_if_clk(struct drm_crtc crtc, const struct vop2_connector_if_data if_data,
	6838	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk, int conn_id)
	6839	+{
	6840	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6841	+ struct vop2 *vop2 = vp->vop2;
	6842	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	6843	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6844	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	6845	+ unsigned long dclk_core_rate, dclk_out_rate = 0;
	6846	+ /conn_dclk = conn_pixclk or conn_dclk = conn_pixclk / 2 /
	6847	+ u64 hdmi_edp_pixclk, hdmi_edp_dclk, mipi_pixclk;
	6848	+ char dclk_core_div_shift = 2;
	6849	+ char K = 1;
	6850	+ char clk_name[32];
	6851	+ struct vop2_clk dclk_core, dclk_out, *dclk;
	6852	+ int ret;
	6853	+ bool dsc_txp_clk_is_biggest = false;
	6854	+ u8 dsc_id = conn_id & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	6855	+
	6856	+ dclk_core_div_shift = if_data->post_proc_div_shift;
	6857	+ dclk_core_rate = v_pixclk >> dclk_core_div_shift;
	6858	+
	6859	+ if (!if_dclk && (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id)))
	6860	+ return -EINVAL;
	6861	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) &&
	6862	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420)) {
	6863	+ DRM_DEV_ERROR(vop2->dev, "Dual channel and YUV420 can't work together\n");
	6864	+ return -EINVAL;
	6865	+ }
	6866	+
	6867	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) \|\|
	6868	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420))
	6869	+ K = 2;
	6870	+
	6871	+ if (output_if_is_hdmi(conn_id)) {
	6872	+ if (vcstate->dsc_enable) {
	6873	+ hdmi_edp_pixclk = vcstate->dsc_cds_clk_rate << 1;
	6874	+ hdmi_edp_dclk = vcstate->dsc_cds_clk_rate;
	6875	+ } else {
	6876	+ hdmi_edp_pixclk = (dclk_core_rate << 1) / K;
	6877	+ hdmi_edp_dclk = dclk_core_rate / K;
	6878	+ }
	6879	+
	6880	+ if_pixclk->rate = hdmi_edp_pixclk;
	6881	+ if_dclk->rate = hdmi_edp_dclk;
	6882	+ } else if (output_if_is_edp(conn_id)) {
	6883	+ hdmi_edp_pixclk = v_pixclk;
	6884	+ do_div(hdmi_edp_pixclk, K);
	6885	+ hdmi_edp_dclk = hdmi_edp_pixclk;
	6886	+
	6887	+ if_pixclk->rate = hdmi_edp_pixclk;
	6888	+ if_dclk->rate = hdmi_edp_dclk;
	6889	+ } else if (output_if_is_dp(conn_id)) {
	6890	+ dclk_out_rate = v_pixclk >> 2;
	6891	+ dclk_out_rate = dclk_out_rate / K;
	6892	+ if_pixclk->rate = dclk_out_rate;
	6893	+ } else if (output_if_is_mipi(conn_id)) {
	6894	+ if (vcstate->dsc_enable)
	6895	+ /* dsc output is 96bit, dsi input is 192 bit */
	6896	+ mipi_pixclk = vcstate->dsc_cds_clk_rate >> 1;
	6897	+ else
	6898	+ mipi_pixclk = dclk_core_rate / K;
	6899	+
	6900	+ dclk_out_rate = dclk_core_rate / K;
	6901	+ if_pixclk->rate = mipi_pixclk;
	6902	+ } else if (output_if_is_dpi(conn_id)) {
	6903	+ if_pixclk->rate = v_pixclk;
	6904	+ }
	6905	+
	6906	+ /*
	6907	+ * RGB/eDP/HDMI: if_pixclk >= dclk_core
	6908	+ * DP: dp_pixclk = dclk_out <= dclk_core
	6909	+ * DSI: mipi_pixclk <= dclk_out <= dclk_core
	6910	+ *
	6911	+ */
	6912	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	6913	+ dclk_core = vop2_clk_get(vop2, clk_name);
	6914	+
	6915	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	6916	+ dclk_out = vop2_clk_get(vop2, clk_name);
	6917	+
	6918	+ /*
	6919	+ * HDMI use 1:1 dclk for rgb/yuv444, 1:2 for yuv420 when
	6920	+ * pixclk <= 600
	6921	+ * We want use HDMI PHY clk as dclk source for DP/HDMI.
	6922	+ * The max freq of HDMI PHY CLK is 600 MHZ.
	6923	+ * When used for HDMI, the input freq and v_pixclk must
	6924	+ * keep 1:1 for rgb/yuv444, 1:2 for yuv420
	6925	+ */
	6926	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_dp(conn_id) \|\| output_if_is_mipi(conn_id)) {
	6927	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	6928	+ dclk = vop2_clk_get(vop2, clk_name);
	6929	+ if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) {
	6930	+ if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420 \|\|
	6931	+ (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE))
	6932	+ v_pixclk = v_pixclk >> 1;
	6933	+ } else {
	6934	+ v_pixclk = v_pixclk >> 2;
	6935	+ }
	6936	+ clk_set_rate(dclk->hw.clk, v_pixclk);
	6937	+ }
	6938	+
	6939	+ if (vcstate->dsc_enable) {
	6940	+ if ((vcstate->dsc_txp_clk_rate >= dclk_core_rate) &&
	6941	+ (vcstate->dsc_txp_clk_rate >= if_pixclk->rate)) {
	6942	+ dsc_txp_clk_is_biggest = true;
	6943	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	6944	+ vop2_set_dsc_clk(crtc, 0);
	6945	+ vop2_set_dsc_clk(crtc, 1);
	6946	+ } else {
	6947	+ vop2_set_dsc_clk(crtc, dsc_id);
	6948	+ }
	6949	+ }
	6950	+ }
	6951	+
	6952	+ if (dclk_core_rate > if_pixclk->rate) {
	6953	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	6954	+ if (output_if_is_mipi(conn_id))
	6955	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	6956	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	6957	+ } else {
	6958	+ if (output_if_is_mipi(conn_id))
	6959	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	6960	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	6961	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	6962	+ }
	6963	+
	6964	+ if (!dsc_txp_clk_is_biggest && vcstate->dsc_enable) {
	6965	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	6966	+ vop2_set_dsc_clk(crtc, 0);
	6967	+ vop2_set_dsc_clk(crtc, 1);
	6968	+ } else {
	6969	+ vop2_set_dsc_clk(crtc, dsc_id);
	6970	+ }
	6971	+ }
	6972	+
	6973	+ return ret;
	6974	+}
	6975	+
	6976	+static int vop2_calc_dsc_clk(struct drm_crtc *crtc)
	6977	+{
	6978	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6979	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6980	+ struct vop2 *vop2 = vp->vop2;
	6981	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	6982	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	6983	+ u8 k = 1;
	6984	+
	6985	+ if (!vop2->data->nr_dscs) {
	6986	+ DRM_WARN("Unsupported DSC\n");
	6987	+
	6988	+ return 0;
	6989	+ }
	6990	+
	6991	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	6992	+ k = 2;
	6993	+
	6994	+ vcstate->dsc_txp_clk_rate = v_pixclk;
	6995	+ do_div(vcstate->dsc_txp_clk_rate, (vcstate->dsc_pixel_num * k));
	6996	+
	6997	+ vcstate->dsc_pxl_clk_rate = v_pixclk;
	6998	+ do_div(vcstate->dsc_pxl_clk_rate, (vcstate->dsc_slice_num * k));
	6999	+
	7000	+ /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel)
	7001	+ * cds_dat_width = 96;
	7002	+ * bits_per_pixel = [8-12];
	7003	+ * As cds clk is div from txp clk and only support 1/2/4 div,
	7004	+ * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4,
	7005	+ * otherwise dsc_cds = crtc_clock / 8;
	7006	+ */
	7007	+ vcstate->dsc_cds_clk_rate = v_pixclk / (vcstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8);
	7008	+
	7009	+ return 0;
	7010	+}
	7011	+
	7012	+static int vop2_calc_cru_cfg(struct drm_crtc *crtc, int conn_id,
	7013	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	7014	+{
	7015	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7016	+ struct vop2 *vop2 = vp->vop2;
	7017	+ const struct vop2_connector_if_data *if_data;
	7018	+ struct vop2_clk if_clk_src, if_clk_parent;
	7019	+ char clk_name[32];
	7020	+ int ret;
	7021	+
	7022	+ if (vop2->version != VOP_VERSION_RK3588)
	7023	+ return 0;
	7024	+
	7025	+ if_data = vop2_find_connector_if_data(vop2, conn_id);
	7026	+ if_clk_src = vop2_clk_get(vop2, if_data->clk_src_name);
	7027	+ snprintf(clk_name, sizeof(clk_name), "%s%d", if_data->clk_parent_name, vp->id);
	7028	+ if_clk_parent = vop2_clk_get(vop2, clk_name);
	7029	+ *if_pixclk = vop2_clk_get(vop2, if_data->pixclk_name);
	7030	+ *if_dclk = vop2_clk_get(vop2, if_data->dclk_name);
	7031	+ if (!(*if_pixclk) \|\| !if_clk_parent) {
	7032	+ DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n");
	7033	+ return -ENODEV;
	7034	+ }
	7035	+
	7036	+ ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk);
	7037	+ if (ret < 0) {
	7038	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	7039	+ __clk_get_name(if_clk_parent->hw.clk),
	7040	+ __clk_get_name(if_clk_src->hw.clk), ret);
	7041	+ return ret;
	7042	+ }
	7043	+
	7044	+ /* HDMI and eDP use independent if_pixclk and if_dclk, and others if_pixclk = if_dclk */
	7045	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id))
	7046	+ ret = vop2_calc_if_clk(crtc, if_data, if_pixclk, if_dclk, conn_id);
	7047	+ else
	7048	+ ret = vop2_calc_if_clk(crtc, if_data, *if_pixclk, NULL, conn_id);
	7049	+
	7050	+ return ret;
	7051	+}
	7052	+
	7053	+static void vop2_crtc_load_pps(struct drm_crtc *crtc, u8 dsc_id)
	7054	+{
	7055	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7056	+ struct vop2 *vop2 = vp->vop2;
	7057	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7058	+
	7059	+ struct drm_dsc_picture_parameter_set *pps = &vcstate->pps;
	7060	+ struct drm_dsc_picture_parameter_set config_pps;
	7061	+ int i = 0;
	7062	+ u32 pps_val = (u32 )&config_pps;
	7063	+ u32 offset;
	7064	+ struct vop2_dsc *dsc;
	7065	+
	7066	+ dsc = &vop2->dscs[dsc_id];
	7067	+ offset = dsc->regs->dsc_pps0_3.offset;
	7068	+
	7069	+ memcpy(&config_pps, pps, sizeof(config_pps));
	7070	+
	7071	+ if ((config_pps.pps_3 & 0xf) > dsc->max_linebuf_depth) {
	7072	+ config_pps.pps_3 &= 0xf0;
	7073	+ config_pps.pps_3 \|= dsc->max_linebuf_depth;
	7074	+ DRM_WARN("DSC%d max_linebuf_depth is: %d, current set value is: %d\n",
	7075	+ dsc_id, dsc->max_linebuf_depth, config_pps.pps_3 & 0xf);
	7076	+ }
	7077	+
	7078	+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
	7079	+ config_pps.rc_range_parameters[i] =
	7080	+ (pps->rc_range_parameters[i] >> 3 & 0x1f) \|
	7081	+ ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) \|
	7082	+ ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) \|
	7083	+ ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10);
	7084	+ }
	7085	+
	7086	+ for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++)
	7087	+ vop2_writel(vop2, offset + i * 4, *pps_val++);
	7088	+}
	7089	+
	7090	+static void vop2_crtc_enable_dsc(struct drm_crtc crtc, struct drm_crtc_state old_state, u8 dsc_id)
	7091	+{
	7092	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7093	+ struct vop2 *vop2 = vp->vop2;
	7094	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7095	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7096	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
	7097	+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	7098	+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
	7099	+ u16 htotal = adjusted_mode->crtc_htotal;
	7100	+ u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
	7101	+ u16 vdisplay = adjusted_mode->crtc_vdisplay;
	7102	+ u16 vtotal = adjusted_mode->crtc_vtotal;
	7103	+ u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
	7104	+ u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
	7105	+ u16 vact_end = vact_st + vdisplay;
	7106	+ u8 dsc_interface_mode = 0;
	7107	+ struct vop2_dsc *dsc;
	7108	+ struct vop2_clk dsc_cds_clk, dsc_pxl_clk, *dsc_txp_clk;
	7109	+ const struct vop2_data *vop2_data = vop2->data;
	7110	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	7111	+ bool mipi_ds_mode = false;
	7112	+ uint32_t *reg_base = vop2->regs;
	7113	+ u32 offset = 0;
	7114	+
	7115	+ if (!vop2->data->nr_dscs) {
	7116	+ DRM_WARN("Unsupported DSC\n");
	7117	+
	7118	+ return;
	7119	+ }
	7120	+
	7121	+ if (vcstate->dsc_slice_num > dsc_data->max_slice_num)
	7122	+ DRM_ERROR("DSC%d supported max slice is: %d, current is: %d\n",
	7123	+ dsc_data->id, dsc_data->max_slice_num, vcstate->dsc_slice_num);
	7124	+
	7125	+ dsc = &vop2->dscs[dsc_id];
	7126	+ if (dsc->pd) {
	7127	+ dsc->pd->vp_mask = BIT(vp->id);
	7128	+ vop2_power_domain_get(dsc->pd);
	7129	+ }
	7130	+
	7131	+ VOP_MODULE_SET(vop2, dsc, scan_timing_para_imd_en, 1);
	7132	+ VOP_MODULE_SET(vop2, dsc, dsc_port_sel, vp->id);
	7133	+ if (vcstate->output_if & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1)) {
	7134	+ dsc_interface_mode = VOP_DSC_IF_HDMI;
	7135	+ } else {
	7136	+ mipi_ds_mode = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE);
	7137	+ if (mipi_ds_mode)
	7138	+ dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE;
	7139	+ else
	7140	+ dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE;
	7141	+ }
	7142	+
	7143	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7144	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 0);
	7145	+ else
	7146	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 1);
	7147	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	7148	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	7149	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_name);
	7150	+
	7151	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, dsc_interface_mode);
	7152	+ VOP_MODULE_SET(vop2, dsc, dsc_pixel_num, vcstate->dsc_pixel_num >> 1);
	7153	+ VOP_MODULE_SET(vop2, dsc, dsc_txp_clk_div, dsc_txp_clk->div_val);
	7154	+ VOP_MODULE_SET(vop2, dsc, dsc_pxl_clk_div, dsc_pxl_clk->div_val);
	7155	+ VOP_MODULE_SET(vop2, dsc, dsc_cds_clk_div, dsc_cds_clk->div_val);
	7156	+ VOP_MODULE_SET(vop2, dsc, dsc_scan_en, !mipi_ds_mode);
	7157	+ VOP_MODULE_SET(vop2, dsc, dsc_halt_en, mipi_ds_mode);
	7158	+
	7159	+ if (!mipi_ds_mode) {
	7160	+ u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end;
	7161	+ u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16;
	7162	+ u64 dsc_cds_rate = vcstate->dsc_cds_clk_rate;
	7163	+ u32 v_pixclk_mhz = adjusted_mode->crtc_clock / 1000; /* video timing pixclk */
	7164	+ u32 dly_num, dsc_cds_rate_mhz, val = 0;
	7165	+ struct vop2_clk *dclk_core;
	7166	+ char clk_name[32];
	7167	+ int k = 1;
	7168	+
	7169	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7170	+ k = 2;
	7171	+
	7172	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7173	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7174	+
	7175	+ if (target_bpp >> 4 < dsc->min_bits_per_pixel)
	7176	+ DRM_ERROR("Unsupported bpp less than: %d\n", dsc->min_bits_per_pixel);
	7177	+
	7178	+ /*
	7179	+ * dly_num = delay_line_num * T(one-line) / T (dsc_cds)
	7180	+ * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz
	7181	+ * T (dsc_cds) = 1 / dsc_cds_rate_mhz
	7182	+ *
	7183	+ * HDMI:
	7184	+ * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay
	7185	+ * delay_line_num = 4 - BPP / 8
	7186	+ * = (64 - target_bpp / 8) / 16
	7187	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7188	+ *
	7189	+ * MIPI DSI[4320 and 9216 is buffer size for DSC]:
	7190	+ * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size;
	7191	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7192	+ * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size;
	7193	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7194	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num
	7195	+ */
	7196	+ do_div(dsc_cds_rate, 1000000); /* hz to Mhz */
	7197	+ dsc_cds_rate_mhz = dsc_cds_rate;
	7198	+ dsc_hsync = hsync_len / 2;
	7199	+ if (dsc_interface_mode == VOP_DSC_IF_HDMI) {
	7200	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7201	+ } else {
	7202	+ int dsc_buf_size = dsc->id == 0 ? 4320 * 8 : 9216 * 2;
	7203	+ int delay_line_num = dsc_buf_size / vcstate->dsc_slice_num / be16_to_cpu(vcstate->pps.chunk_size);
	7204	+
	7205	+ delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7206	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num;
	7207	+
	7208	+ /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */
	7209	+ if (dsc_hsync < 8)
	7210	+ dsc_hsync = 8;
	7211	+ }
	7212	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_mode, 0);
	7213	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_num, dly_num);
	7214	+ /*
	7215	+ * htotal / dclk_core = dsc_htotal /cds_clk
	7216	+ *
	7217	+ * dclk_core = DCLK / (1 << dclk_core->div_val)
	7218	+ * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val)
	7219	+ * txp_clk = DCLK / (1 << dsc_txp_clk->div_val)
	7220	+ *
	7221	+ * dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7222	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val))
	7223	+ */
	7224	+ dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7225	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val));
	7226	+ val = dsc_htotal << 16 \| dsc_hsync;
	7227	+ VOP_MODULE_SET(vop2, dsc, dsc_htotal_pw, val);
	7228	+
	7229	+ dsc_hact_st = hact_st / 2;
	7230	+ dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st;
	7231	+ val = dsc_hact_end << 16 \| dsc_hact_st;
	7232	+ VOP_MODULE_SET(vop2, dsc, dsc_hact_st_end, val);
	7233	+
	7234	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, vtotal);
	7235	+ VOP_MODULE_SET(vop2, dsc, dsc_vs_end, vsync_len);
	7236	+ VOP_MODULE_SET(vop2, dsc, dsc_vact_st_end, vact_end << 16 \| vact_st);
	7237	+ }
	7238	+
	7239	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 1);
	7240	+ udelay(10);
	7241	+ /* read current dsc core register and backup to regsbak */
	7242	+ offset = dsc->regs->dsc_en.offset;
	7243	+ vop2->regsbak[offset >> 2] = reg_base[offset >> 2];
	7244	+
	7245	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 1);
	7246	+ vop2_crtc_load_pps(crtc, dsc_id);
	7247	+
	7248	+ VOP_MODULE_SET(vop2, dsc, dsc_rbit, 1);
	7249	+ VOP_MODULE_SET(vop2, dsc, dsc_rbyt, 0);
	7250	+ VOP_MODULE_SET(vop2, dsc, dsc_flal, 1);
	7251	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	7252	+ VOP_MODULE_SET(vop2, dsc, dsc_epb, 0);
	7253	+ VOP_MODULE_SET(vop2, dsc, dsc_epl, 1);
	7254	+ VOP_MODULE_SET(vop2, dsc, dsc_nslc, ilog2(vcstate->dsc_slice_num));
	7255	+ VOP_MODULE_SET(vop2, dsc, dsc_sbo, 1);
	7256	+ VOP_MODULE_SET(vop2, dsc, dsc_ifep, dsc_sink_cap->version_minor == 2 ? 1 : 0);
	7257	+ VOP_MODULE_SET(vop2, dsc, dsc_pps_upd, 1);
	7258	+
	7259	+ DRM_DEV_INFO(vop2->dev, "DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n",
	7260	+ dsc->id,
	7261	+ vcstate->dsc_txp_clk_rate, dsc_txp_clk->div_val,
	7262	+ vcstate->dsc_pxl_clk_rate, dsc_pxl_clk->div_val,
	7263	+ vcstate->dsc_cds_clk_rate, dsc_cds_clk->div_val);
	7264	+
	7265	+ dsc->attach_vp_id = vp->id;
	7266	+ dsc->enabled = true;
	7267	+}
	7268	+
	7269	+static void vop2_setup_dual_channel_if(struct drm_crtc *crtc)
	7270	+{
	7271	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7272	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7273	+ struct vop2 *vop2 = vp->vop2;
	7274	+
	7275	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 1);
	7276	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
	7277	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 1);
	7278	+
	7279	+ if (vcstate->output_if & VOP_OUTPUT_IF_DP1)
	7280	+ VOP_CTRL_SET(vop2, dp_dual_en, 1);
	7281	+ else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1)
	7282	+ VOP_CTRL_SET(vop2, edp_dual_en, 1);
	7283	+ else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)
	7284	+ VOP_CTRL_SET(vop2, hdmi_dual_en, 1);
	7285	+ else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1)
	7286	+ VOP_CTRL_SET(vop2, mipi_dual_en, 1);
	7287	+}
	7288	+
	7289	+/*
	7290	+ * MIPI port mux on rk3588:
	7291	+ * 0: Video Port2
	7292	+ * 1: Video Port3
	7293	+ * 3: Video Port 1(MIPI1 only)
	7294	+ */
	7295	+static int vop2_get_mipi_port_mux(struct vop2 *vop2, int vp_id)
	7296	+{
	7297	+ if (vop2->version == VOP_VERSION_RK3588) {
	7298	+ if (vp_id == 1)
	7299	+ return 3;
	7300	+ else if (vp_id == 3)
	7301	+ return 1;
	7302	+ else
	7303	+ return 0;
	7304	+ } else {
	7305	+ return vp_id;
	7306	+ }
	7307	+}
	7308	+
	7309	+static u32 vop2_get_hdmi_pol(struct vop2 *vop2, u32 flags)
	7310	+{
	7311	+ u32 val;
	7312	+
	7313	+ if (vop2->version == VOP_VERSION_RK3588) {
	7314	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0;
	7315	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0;
	7316	+ } else {
	7317	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
	7318	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
	7319	+ }
	7320	+
	7321	+ return val;
	7322	+}
	7323	+
	7324	+static void vop2_post_color_swap(struct drm_crtc *crtc)
	7325	+{
	7326	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7327	+ struct vop2 *vop2 = vp->vop2;
	7328	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7329	+ u32 output_if = vcstate->output_if;
	7330	+ u32 data_swap = 0;
	7331	+
	7332	+ if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode) \|\|
	7333	+ vop3_output_rb_swap(vcstate->bus_format, vcstate->output_mode))
	7334	+ data_swap = DSP_RB_SWAP;
	7335	+
	7336	+ if (vop2->version == VOP_VERSION_RK3588 &&
	7337	+ (output_if_is_hdmi(output_if) \|\| output_if_is_dp(output_if)) &&
	7338	+ (vcstate->bus_format == MEDIA_BUS_FMT_YUV8_1X24 \|\|
	7339	+ vcstate->bus_format == MEDIA_BUS_FMT_YUV10_1X30))
	7340	+ data_swap \|= DSP_RG_SWAP;
	7341	+
	7342	+ VOP_MODULE_SET(vop2, vp, dsp_data_swap, data_swap);
	7343	+}
	7344	+
	7345	+/*
	7346	+ * For vop3 video port0, if hdr_vivid is not enable, the pipe delay time as follow:
	7347	+ * win_dly + config_win_dly + layer_mix_dly + sdr2hdr_dly + * hdr_mix_dly = config_bg_dly
	7348	+ *
	7349	+ * if hdr_vivid is enable, the hdr layer's pipe delay time as follow:
	7350	+ * win_dly + config_win_dly +hdrvivid_dly + hdr_mix_dly = config_bg_dly
	7351	+ *
	7352	+ * If hdrvivid and sdr2hdr bot enable, the time arrivr hdr_mix should be the same:
	7353	+ * win_dly + config_win_dly0 + hdrvivid_dly = win_dly + config_win_dly1 + laer_mix_dly +
	7354	+ * sdr2hdr_dly
	7355	+ *
	7356	+ * For vop3 video port1, the pipe delay time as follow:
	7357	+ * win_dly + config_win_dly + layer_mix_dly = config_bg_dly
	7358	+ *
	7359	+ * Here, win_dly, layer_mix_dly, sdr2hdr_dly, hdr_mix_dly, hdrvivid_dly is the hardware
	7360	+ * delay cycles. Config_win_dly and config_bg_dly is the register value that we can config.
	7361	+ * Different hdr vivid mode have different hdrvivid_dly. For sdr2hdr_dly, only sde2hdr
	7362	+ * enable, it will delay, otherwise, the sdr2hdr_dly is 0.
	7363	+ *
	7364	+ * For default, the config_win_dly will be 0, it just user to make the pipe to arrive
	7365	+ * hdr_mix at the same time.
	7366	+ */
	7367	+static void vop3_setup_pipe_dly(struct vop2_video_port vp, const struct vop2_zpos vop2_zpos)
	7368	+{
	7369	+ struct vop2 *vop2 = vp->vop2;
	7370	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	7371	+ const struct vop2_zpos *zpos;
	7372	+ struct drm_plane *plane;
	7373	+ struct vop2_plane_state *vpstate;
	7374	+ struct vop2_win *win;
	7375	+ const struct vop2_data *vop2_data = vop2->data;
	7376	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	7377	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7378	+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	7379	+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
	7380	+ int bg_dly = 0x0;
	7381	+ int dly = 0x0;
	7382	+ int hdr_win_dly;
	7383	+ int sdr_win_dly;
	7384	+ int sdr2hdr_dly;
	7385	+ int pre_scan_dly;
	7386	+ int i;
	7387	+
	7388	+ /**
	7389	+ * config bg dly, select the max delay num of hdrvivid and sdr2hdr module
	7390	+ * as the increase value of bg delay num. If hdrvivid and sdr2hdr is not
	7391	+ * work, the default bg_dly is 0x10. and the default win delay num is 0.
	7392	+ */
	7393	+ if ((vp->hdr_en \|\| vp->sdr2hdr_en) &&
	7394	+ (vp->hdrvivid_mode >= 0 && vp->hdrvivid_mode <= SDR2HLG)) {
	7395	+ /* set sdr2hdr_dly to 0 if sdr2hdr is disable */
	7396	+ sdr2hdr_dly = vp->sdr2hdr_en ? vp_data->sdr2hdr_dly : 0;
	7397	+
	7398	+ /* set the max delay pipe's config_win_dly as 0 */
	7399	+ if (vp_data->hdrvivid_dly[vp->hdrvivid_mode] >=
	7400	+ sdr2hdr_dly + vp_data->layer_mix_dly) {
	7401	+ bg_dly = vp_data->win_dly + vp_data->hdrvivid_dly[vp->hdrvivid_mode] +
	7402	+ vp_data->hdr_mix_dly;
	7403	+ hdr_win_dly = 0;
	7404	+ sdr_win_dly = vp_data->hdrvivid_dly[vp->hdrvivid_mode] -
	7405	+ vp_data->layer_mix_dly - sdr2hdr_dly;
	7406	+ } else {
	7407	+ bg_dly = vp_data->win_dly + vp_data->layer_mix_dly + sdr2hdr_dly +
	7408	+ vp_data->hdr_mix_dly;
	7409	+ hdr_win_dly = sdr2hdr_dly + vp_data->layer_mix_dly -
	7410	+ vp_data->hdrvivid_dly[vp->hdrvivid_mode];
	7411	+ sdr_win_dly = 0;
	7412	+ }
	7413	+ } else {
	7414	+ bg_dly = vp_data->win_dly + vp_data->layer_mix_dly + vp_data->hdr_mix_dly;
	7415	+ sdr_win_dly = 0;
	7416	+ }
	7417	+
	7418	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	7419	+ pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	7420	+ VOP_MODULE_SET(vop2, vp, bg_dly, bg_dly);
	7421	+ VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
	7422	+
	7423	+ /**
	7424	+ * config win dly
	7425	+ */
	7426	+ if (!vop2_zpos)
	7427	+ return;
	7428	+
	7429	+ for (i = 0; i < vp->nr_layers; i++) {
	7430	+ zpos = &vop2_zpos[i];
	7431	+ win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
	7432	+ plane = &win->base;
	7433	+ vpstate = to_vop2_plane_state(plane->state);
	7434	+
	7435	+ if ((vp->hdr_en \|\| vp->sdr2hdr_en) &&
	7436	+ (vp->hdrvivid_mode >= 0 && vp->hdrvivid_mode <= SDR2HLG)) {
	7437	+ dly = vpstate->hdr_in ? hdr_win_dly : sdr_win_dly;
	7438	+ }
	7439	+ if (vop2_cluster_window(win))
	7440	+ dly \|= dly << 8;
	7441	+
	7442	+ VOP_CTRL_SET(vop2, win_dly[win->phys_id], dly);
	7443	+ }
	7444	+}
	7445	+
	7446	+static int vop2_get_vrefresh(struct vop2_video_port vp, const struct drm_display_mode mode)
	7447	+{
	7448	+ if (vp->mcu_timing.mcu_pix_total)
	7449	+ return drm_mode_vrefresh(mode) / vp->mcu_timing.mcu_pix_total;
	7450	+ else
	7451	+ return drm_mode_vrefresh(mode);
	7452	+}
	7453	+
4883	7454	static void vop2_crtc_atomic_enable(struct drm_crtc crtc, struct drm_crtc_state old_state)
4884	7455	{
4885	7456	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7457	+ struct vop2_video_port *splice_vp;
4886	7458	struct vop2 *vop2 = vp->vop2;
4887	7459	const struct vop2_data *vop2_data = vop2->data;
4888	7460	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4889	7461	const struct vop_intr *intr = vp_data->intr;
4890	7462	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4891	7463	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7464	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
4892	7465	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
4893	7466	u16 hdisplay = adjusted_mode->crtc_hdisplay;
4894	7467	u16 htotal = adjusted_mode->crtc_htotal;
..	..	@@ -4900,18 +7473,60 @@
4900	7473	u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
4901	7474	u16 vact_end = vact_st + vdisplay;
4902	7475	bool interlaced = !!(adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
4903		- uint8_t out_mode;
4904	7476	bool dclk_inv, yc_swap = false;
4905	7477	int act_end;
4906	7478	uint32_t val;
	7479	+ char clk_name[32];
	7480	+ struct vop2_clk *if_pixclk = NULL;
	7481	+ struct vop2_clk *if_dclk = NULL;
	7482	+ struct vop2_clk dclk, dclk_out, *dclk_core;
	7483	+ int splice_en = 0;
	7484	+ int port_mux;
	7485	+ int ret;
	7486	+
	7487	+ if (old_state && old_state->self_refresh_active) {
	7488	+ drm_crtc_vblank_on(crtc);
	7489	+ if (vop2->aclk_rate_reset)
	7490	+ clk_set_rate(vop2->aclk, vop2->aclk_rate);
	7491	+ vop2->aclk_rate_reset = false;
	7492	+
	7493	+ return;
	7494	+ }
4907	7495
4908	7496	vop2->active_vp_mask \|= BIT(vp->id);
4909	7497	vop2_set_system_status(vop2);
4910	7498
4911	7499	vop2_lock(vop2);
4912		- DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
4913		- hdisplay, vdisplay, interlaced ? "i" : "p",
4914		- adjusted_mode->vrefresh, vcstate->output_type, vp->id);
	7500	+ DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x) for vp%d dclk: %d\n",
	7501	+ hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p",
	7502	+ vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if,
	7503	+ vp->id, adjusted_mode->crtc_clock * 1000);
	7504	+
	7505	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	7506	+ vcstate->splice_mode = true;
	7507	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	7508	+ splice_vp->splice_mode_right = true;
	7509	+ splice_vp->left_vp = vp;
	7510	+ splice_en = 1;
	7511	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	7512	+ }
	7513	+
	7514	+ if (vcstate->dsc_enable) {
	7515	+ int k = 1;
	7516	+
	7517	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7518	+ k = 2;
	7519	+
	7520	+ vcstate->dsc_id = vcstate->output_if & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	7521	+ vcstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k;
	7522	+ vcstate->dsc_pixel_num = vcstate->dsc_slice_num > 4 ? 4 : vcstate->dsc_slice_num;
	7523	+
	7524	+ vop2_calc_dsc_clk(crtc);
	7525	+ DRM_DEV_INFO(vop2->dev, "Enable DSC%d slice:%dx%d, slice num:%d\n",
	7526	+ vcstate->dsc_id, dsc_sink_cap->slice_width,
	7527	+ dsc_sink_cap->slice_height, vcstate->dsc_slice_num);
	7528	+ }
	7529	+
4915	7530	vop2_initial(crtc);
4916	7531	vcstate->vdisplay = vdisplay;
4917	7532	vcstate->mode_update = vop2_crtc_mode_update(crtc);
..	..	@@ -4922,25 +7537,51 @@
4922	7537	val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
4923	7538	val \|= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
4924	7539
	7540	+ vp->output_if = vcstate->output_if;
	7541	+
4925	7542	if (vcstate->output_if & VOP_OUTPUT_IF_RGB) {
	7543	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7544	+ if (ret < 0)
	7545	+ goto out;
	7546	+
4926	7547	VOP_CTRL_SET(vop2, rgb_en, 1);
4927	7548	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4928		- VOP_GRF_SET(vop2, grf_dclk_inv, dclk_inv);
	7549	+ VOP_CTRL_SET(vop2, rgb_pin_pol, val);
	7550	+ VOP_GRF_SET(vop2, sys_grf, grf_dclk_inv, dclk_inv);
4929	7551	}
4930	7552
4931	7553	if (vcstate->output_if & VOP_OUTPUT_IF_BT1120) {
4932		- VOP_CTRL_SET(vop2, rgb_en, 1);
4933		- VOP_CTRL_SET(vop2, bt1120_en, 1);
	7554	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7555	+ if (ret < 0)
	7556	+ goto out;
	7557	+
	7558	+ if (vop2->version == VOP_VERSION_RK3588) {
	7559	+ VOP_CTRL_SET(vop2, bt1120_en, 3);
	7560	+ } else {
	7561	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7562	+ VOP_CTRL_SET(vop2, bt1120_en, 1);
	7563	+ }
4934	7564	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4935		- VOP_GRF_SET(vop2, grf_bt1120_clk_inv, !dclk_inv);
	7565	+ VOP_GRF_SET(vop2, sys_grf, grf_bt1120_clk_inv, !dclk_inv);
	7566	+ VOP_CTRL_SET(vop2, bt1120_dclk_pol, !dclk_inv);
4936	7567	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
4937	7568	VOP_CTRL_SET(vop2, bt1120_yc_swap, yc_swap);
4938	7569	}
4939	7570
4940	7571	if (vcstate->output_if & VOP_OUTPUT_IF_BT656) {
4941		- VOP_CTRL_SET(vop2, bt656_en, 1);
	7572	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7573	+ if (ret < 0)
	7574	+ goto out;
	7575	+
	7576	+ if (vop2->version == VOP_VERSION_RK3588) {
	7577	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7578	+ } else {
	7579	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7580	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7581	+ }
4942	7582	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
4943		- VOP_GRF_SET(vop2, grf_bt656_clk_inv, !dclk_inv);
	7583	+ VOP_GRF_SET(vop2, sys_grf, grf_bt656_clk_inv, !dclk_inv);
	7584	+ VOP_CTRL_SET(vop2, bt656_dclk_pol, !dclk_inv);
4944	7585	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
4945	7586	VOP_CTRL_SET(vop2, bt656_yc_swap, yc_swap);
4946	7587	}
..	..	@@ -4969,8 +7610,18 @@
4969	7610	}
4970	7611
4971	7612	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI0) {
	7613	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI0, &if_pixclk, &if_dclk);
	7614	+ if (ret < 0)
	7615	+ goto out;
	7616	+ if (if_pixclk)
	7617	+ VOP_CTRL_SET(vop2, mipi0_pixclk_div, if_pixclk->div_val);
	7618	+
	7619	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7620	+ VOP_CTRL_SET(vop2, mipi0_ds_mode, 1);
	7621	+
	7622	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
4972	7623	VOP_CTRL_SET(vop2, mipi0_en, 1);
4973		- VOP_CTRL_SET(vop2, mipi0_mux, vp_data->id);
	7624	+ VOP_CTRL_SET(vop2, mipi0_mux, port_mux);
4974	7625	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
4975	7626	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
4976	7627	if (vcstate->hold_mode) {
..	..	@@ -4980,8 +7631,19 @@
4980	7631	}
4981	7632
4982	7633	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1) {
	7634	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI1, &if_pixclk, &if_dclk);
	7635	+ if (ret < 0)
	7636	+ goto out;
	7637	+ if (if_pixclk)
	7638	+ VOP_CTRL_SET(vop2, mipi1_pixclk_div, if_pixclk->div_val);
	7639	+
	7640	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7641	+ VOP_CTRL_SET(vop2, mipi1_ds_mode, 1);
	7642	+
	7643	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
	7644	+
4983	7645	VOP_CTRL_SET(vop2, mipi1_en, 1);
4984		- VOP_CTRL_SET(vop2, mipi1_mux, vp_data->id);
	7646	+ VOP_CTRL_SET(vop2, mipi1_mux, port_mux);
4985	7647	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
4986	7648	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
4987	7649	if (vcstate->hold_mode) {
..	..	@@ -4990,41 +7652,78 @@
4990	7652	}
4991	7653	}
4992	7654
4993		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
4994		- VOP_MODULE_SET(vop2, vp, mipi_dual_en, 1);
4995		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
4996		- VOP_MODULE_SET(vop2, vp, mipi_dual_channel_swap, 1);
4997		- }
	7655	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7656	+ vop2_setup_dual_channel_if(crtc);
4998	7657
4999	7658	if (vcstate->output_if & VOP_OUTPUT_IF_eDP0) {
	7659	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP0, &if_pixclk, &if_dclk);
	7660	+ if (ret < 0)
	7661	+ goto out;
	7662	+ if (if_pixclk && if_dclk) {
	7663	+ VOP_CTRL_SET(vop2, edp0_pixclk_div, if_pixclk->div_val);
	7664	+ VOP_CTRL_SET(vop2, edp0_dclk_div, if_dclk->div_val);
	7665	+ }
	7666	+
5000	7667	VOP_CTRL_SET(vop2, edp0_en, 1);
5001	7668	VOP_CTRL_SET(vop2, edp0_mux, vp_data->id);
5002	7669	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5003	7670	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7671	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 1);
5004	7672	}
5005	7673
5006	7674	if (vcstate->output_if & VOP_OUTPUT_IF_eDP1) {
	7675	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP1, &if_pixclk, &if_dclk);
	7676	+ if (ret < 0)
	7677	+ goto out;
	7678	+ if (if_pixclk && if_dclk) {
	7679	+ VOP_CTRL_SET(vop2, edp1_pixclk_div, if_pixclk->div_val);
	7680	+ VOP_CTRL_SET(vop2, edp1_dclk_div, if_dclk->div_val);
	7681	+ }
	7682	+
5007	7683	VOP_CTRL_SET(vop2, edp1_en, 1);
5008	7684	VOP_CTRL_SET(vop2, edp1_mux, vp_data->id);
5009	7685	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5010	7686	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7687	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 1);
5011	7688	}
5012	7689
5013	7690	if (vcstate->output_if & VOP_OUTPUT_IF_DP0) {
	7691	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7692	+ if (ret < 0)
	7693	+ goto out;
5014	7694	VOP_CTRL_SET(vop2, dp0_en, 1);
5015	7695	VOP_CTRL_SET(vop2, dp0_mux, vp_data->id);
5016		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5017		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7696	+ VOP_CTRL_SET(vop2, dp0_dclk_pol, 0);
	7697	+ VOP_CTRL_SET(vop2, dp0_pin_pol, val);
5018	7698	}
5019	7699
5020	7700	if (vcstate->output_if & VOP_OUTPUT_IF_DP1) {
	7701	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7702	+ if (ret < 0)
	7703	+ goto out;
	7704	+
5021	7705	VOP_CTRL_SET(vop2, dp1_en, 1);
5022	7706	VOP_CTRL_SET(vop2, dp1_mux, vp_data->id);
5023		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5024		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7707	+ VOP_CTRL_SET(vop2, dp1_dclk_pol, 0);
	7708	+ VOP_CTRL_SET(vop2, dp1_pin_pol, val);
5025	7709	}
5026	7710
5027	7711	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI0) {
	7712	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI0, &if_pixclk, &if_dclk);
	7713	+ if (ret < 0)
	7714	+ goto out;
	7715	+ if (if_pixclk && if_dclk) {
	7716	+ VOP_CTRL_SET(vop2, hdmi0_pixclk_div, if_pixclk->div_val);
	7717	+ VOP_CTRL_SET(vop2, hdmi0_dclk_div, if_dclk->div_val);
	7718	+ }
	7719	+
	7720	+ if (vcstate->dsc_enable)
	7721	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 1);
	7722	+
	7723	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	7724	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 1);
	7725	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi0_pin_pol, val);
	7726	+
5028	7727	VOP_CTRL_SET(vop2, hdmi0_en, 1);
5029	7728	VOP_CTRL_SET(vop2, hdmi0_mux, vp_data->id);
5030	7729	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
..	..	@@ -5032,26 +7731,29 @@
5032	7731	}
5033	7732
5034	7733	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1) {
	7734	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI1, &if_pixclk, &if_dclk);
	7735	+ if (ret < 0)
	7736	+ goto out;
	7737	+
	7738	+ if (if_pixclk && if_dclk) {
	7739	+ VOP_CTRL_SET(vop2, hdmi1_pixclk_div, if_pixclk->div_val);
	7740	+ VOP_CTRL_SET(vop2, hdmi1_dclk_div, if_dclk->div_val);
	7741	+ }
	7742	+
	7743	+ if (vcstate->dsc_enable)
	7744	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 1);
	7745	+
	7746	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	7747	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 1);
	7748	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi1_pin_pol, val);
	7749	+
5035	7750	VOP_CTRL_SET(vop2, hdmi1_en, 1);
5036	7751	VOP_CTRL_SET(vop2, hdmi1_mux, vp_data->id);
5037	7752	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
5038	7753	VOP_CTRL_SET(vop2, hdmi_dclk_pol, 1);
5039	7754	}
5040	7755
5041		- if ((vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
5042		- !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) \|\|
5043		- vcstate->output_if & VOP_OUTPUT_IF_BT656)
5044		- out_mode = ROCKCHIP_OUT_MODE_P888;
5045		- else
5046		- out_mode = vcstate->output_mode;
5047		- VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
5048		-
5049		- if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
5050		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, DSP_RB_SWAP);
5051		- else
5052		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, 0);
5053		-
5054		- vop2_dither_setup(crtc);
	7756	+ VOP_MODULE_SET(vop2, vp, splice_en, splice_en);
5055	7757
5056	7758	VOP_MODULE_SET(vop2, vp, htotal_pw, (htotal << 16) \| hsync_len);
5057	7759	val = hact_st << 16;
..	..	@@ -5089,7 +7791,13 @@
5089	7791	VOP_INTR_SET(vop2, intr, line_flag_num[0], act_end);
5090	7792	VOP_INTR_SET(vop2, intr, line_flag_num[1], act_end);
5091	7793
5092		- VOP_MODULE_SET(vop2, vp, vtotal_pw, vtotal << 16 \| vsync_len);
	7794	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, vtotal);
	7795	+ VOP_MODULE_SET(vop2, vp, dsp_vs_end, vsync_len);
	7796	+ /**
	7797	+ * when display interface support vrr, config vtotal valid immediately
	7798	+ */
	7799	+ if (vcstate->max_refresh_rate && vcstate->min_refresh_rate)
	7800	+ VOP_MODULE_SET(vop2, vp, sw_dsp_vtotal_imd, 1);
5093	7801
5094	7802	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
5095	7803	vcstate->output_if & VOP_OUTPUT_IF_BT656)
..	..	@@ -5105,9 +7813,70 @@
5105	7813	VOP_MODULE_SET(vop2, vp, dclk_div2_phase_lock, 0);
5106	7814	}
5107	7815
5108		- clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	7816	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	7817	+ dclk_out = vop2_clk_get(vop2, clk_name);
	7818	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7819	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7820	+ if (dclk_out && dclk_core) {
	7821	+ DRM_DEV_INFO(vop2->dev, "%s div: %d %s div: %d\n",
	7822	+ __clk_get_name(dclk_out->hw.clk), dclk_out->div_val,
	7823	+ __clk_get_name(dclk_core->hw.clk), dclk_core->div_val);
	7824	+ VOP_MODULE_SET(vop2, vp, dclk_src_sel, 0);
	7825	+ VOP_MODULE_SET(vop2, vp, dclk_out_div, dclk_out->div_val);
	7826	+ VOP_MODULE_SET(vop2, vp, dclk_core_div, dclk_core->div_val);
	7827	+ }
5109	7828
5110		- vop2_post_config(crtc);
	7829	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	7830	+ dclk = vop2_clk_get(vop2, clk_name);
	7831	+ if (dclk) {
	7832	+ /*
	7833	+ * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available,
	7834	+ * otherwise use system cru as dclk source.
	7835	+ */
	7836	+ ret = vop2_clk_set_parent_extend(vp, vcstate, true);
	7837	+ if (ret < 0)
	7838	+ goto out;
	7839	+
	7840	+ clk_set_rate(vp->dclk, dclk->rate);
	7841	+ DRM_DEV_INFO(vop2->dev, "set %s to %ld, get %ld\n",
	7842	+ __clk_get_name(vp->dclk), dclk->rate, clk_get_rate(vp->dclk));
	7843	+ } else {
	7844	+ /*
	7845	+ * For RK3528, the path of CVBS output is like:
	7846	+ * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
	7847	+ * The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs.
	7848	+ */
	7849	+ if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656)
	7850	+ clk_set_rate(vp->dclk, 4 * adjusted_mode->crtc_clock * 1000);
	7851	+ else
	7852	+ clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	7853	+ }
	7854	+
	7855	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	7856	+ vop2_post_config(crtc);
	7857	+
	7858	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 1);
	7859	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 1);
	7860	+ if (vcstate->dsc_enable) {
	7861	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	7862	+ vop2_crtc_enable_dsc(crtc, old_state, 0);
	7863	+ vop2_crtc_enable_dsc(crtc, old_state, 1);
	7864	+ } else {
	7865	+ vop2_crtc_enable_dsc(crtc, old_state, vcstate->dsc_id);
	7866	+ }
	7867	+ }
	7868	+ /* For RK3588, the reset value of background is 0xa0080200,
	7869	+ * which will enable background and output a grey image. But
	7870	+ * the reset value is just valid in first frame and disable
	7871	+ * in follow frames. If the panel backlight is valid before
	7872	+ * follow frames. The screen may flick a grey image. To avoid
	7873	+ * this phenomenon appear, setting black background after
	7874	+ * reset vop
	7875	+ */
	7876	+ if (vop2->version == VOP_VERSION_RK3588)
	7877	+ VOP_MODULE_SET(vop2, vp, dsp_background, 0x80000000);
	7878	+ if (is_vop3(vop2))
	7879	+ vop3_setup_pipe_dly(vp, NULL);
5111	7880
5112	7881	vop2_cfg_done(crtc);
5113	7882
..	..	@@ -5128,14 +7897,22 @@
5128	7897	*/
5129	7898	VOP_MODULE_SET(vop2, vp, standby, 0);
5130	7899
5131		- drm_crtc_vblank_on(crtc);
	7900	+ if (vp->mcu_timing.mcu_pix_total) {
	7901	+ vop3_set_out_mode(crtc, vcstate->output_mode);
	7902	+ vop3_mcu_mode_setup(crtc);
	7903	+ }
5132	7904
	7905	+ if (!vp->loader_protect)
	7906	+ vop2_clk_reset(vp->dclk_rst);
	7907	+ if (vcstate->dsc_enable)
	7908	+ rk3588_vop2_dsc_cfg_done(crtc);
	7909	+ drm_crtc_vblank_on(crtc);
5133	7910	/*
5134	7911	* restore the lut table.
5135	7912	*/
5136	7913	if (vp->gamma_lut_active)
5137	7914	vop2_crtc_load_lut(crtc);
5138		-
	7915	+out:
5139	7916	vop2_unlock(vop2);
5140	7917	}
5141	7918
..	..	@@ -5153,7 +7930,261 @@
5153	7930	static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
5154	7931	struct drm_crtc_state *crtc_state)
5155	7932	{
	7933	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7934	+ struct vop2_video_port *splice_vp;
	7935	+ struct vop2 *vop2 = vp->vop2;
	7936	+ const struct vop2_data *vop2_data = vop2->data;
	7937	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	7938	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7939	+ struct rockchip_crtc_state *new_vcstate = to_rockchip_crtc_state(crtc_state);
	7940	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7941	+
	7942	+ if (vop2_has_feature(vop2, VOP_FEATURE_SPLICE)) {
	7943	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	7944	+ vcstate->splice_mode = true;
	7945	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	7946	+ splice_vp->splice_mode_right = true;
	7947	+ splice_vp->left_vp = vp;
	7948	+ }
	7949	+ }
	7950	+
	7951	+ if ((vcstate->request_refresh_rate != new_vcstate->request_refresh_rate) \|\|
	7952	+ crtc_state->active_changed \|\| crtc_state->mode_changed)
	7953	+ vp->refresh_rate_change = true;
	7954	+ else
	7955	+ vp->refresh_rate_change = false;
	7956	+
5156	7957	return 0;
	7958	+}
	7959	+
	7960	+static void vop3_disable_dynamic_hdr(struct vop2_video_port *vp, uint8_t win_phys_id)
	7961	+{
	7962	+ struct vop2 *vop2 = vp->vop2;
	7963	+ struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
	7964	+ struct drm_plane *plane = &win->base;
	7965	+ struct drm_plane_state *pstate = plane->state;
	7966	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	7967	+
	7968	+ VOP_MODULE_SET(vop2, vp, hdr10_en, 0);
	7969	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, 0);
	7970	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_bypass_en, 0);
	7971	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 0);
	7972	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_en, 0);
	7973	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_path_en, 0);
	7974	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_auto_gating_en, 1);
	7975	+
	7976	+ vp->hdr_en = false;
	7977	+ vp->hdr_in = false;
	7978	+ vp->hdr_out = false;
	7979	+ vp->sdr2hdr_en = false;
	7980	+ vpstate->hdr_in = false;
	7981	+ vpstate->hdr2sdr_en = false;
	7982	+}
	7983	+
	7984	+static void vop3_setup_hdrvivid(struct vop2_video_port *vp, uint8_t win_phys_id)
	7985	+{
	7986	+ struct vop2 *vop2 = vp->vop2;
	7987	+ struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
	7988	+ struct drm_plane *plane = &win->base;
	7989	+ struct drm_plane_state *pstate = plane->state;
	7990	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	7991	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
	7992	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	7993	+ unsigned long win_mask = vp->win_mask;
	7994	+ int phys_id;
	7995	+ struct hdrvivid_regs *hdrvivid_data;
	7996	+ struct hdr_extend *hdr_data;
	7997	+ struct rockchip_gem_object *lut_gem_obj;
	7998	+ bool have_sdr_layer = false;
	7999	+ uint32_t hdr_mode;
	8000	+ int i;
	8001	+ u32 *tone_lut_kvaddr;
	8002	+ dma_addr_t tone_lut_mst;
	8003	+
	8004	+ vp->hdr_en = false;
	8005	+ vp->hdr_in = false;
	8006	+ vp->hdr_out = false;
	8007	+ vp->sdr2hdr_en = false;
	8008	+ vpstate->hdr_in = false;
	8009	+ vpstate->hdr2sdr_en = false;
	8010	+
	8011	+ hdr_data = (struct hdr_extend *)vcstate->hdr_ext_data->data;
	8012	+ hdrvivid_data = &hdr_data->hdrvivid_data;
	8013	+
	8014	+ hdr_mode = hdrvivid_data->hdr_mode;
	8015	+
	8016	+ if (hdr_mode > SDR2HLG && hdr_mode != SDR2HDR10_USERSPACE &&
	8017	+ hdr_mode != SDR2HLG_USERSPACE) {
	8018	+ DRM_ERROR("Invalid HDR mode:%d, beyond the mode range\n", hdr_mode);
	8019	+ return;
	8020	+ }
	8021	+
	8022	+ /* adjust userspace hdr mode value to kernel value */
	8023	+ if (hdr_mode == SDR2HDR10_USERSPACE)
	8024	+ hdr_mode = SDR2HDR10;
	8025	+ if (hdr_mode == SDR2HLG_USERSPACE)
	8026	+ hdr_mode = SDR2HLG;
	8027	+
	8028	+ if (hdr_mode <= HDR102SDR && vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 && vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
	8029	+ DRM_ERROR("Invalid HDR mode:%d, mismatch plane eotf:%d\n", hdr_mode,
	8030	+ vpstate->eotf);
	8031	+ return;
	8032	+ }
	8033	+
	8034	+ vp->hdrvivid_mode = hdr_mode;
	8035	+ vcstate->yuv_overlay = false;
	8036	+
	8037	+ if (hdr_mode <= HDR102SDR) {
	8038	+ vp->hdr_en = true;
	8039	+ vp->hdr_in = true;
	8040	+ vpstate->hdr_in = true;
	8041	+ } else {
	8042	+ vp->sdr2hdr_en = true;
	8043	+ }
	8044	+
	8045	+ /*
	8046	+ * To confirm whether need to enable sdr2hdr.
	8047	+ */
	8048	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	8049	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	8050	+ plane = &win->base;
	8051	+ pstate = plane->state;
	8052	+ vpstate = to_vop2_plane_state(pstate);
	8053	+
	8054	+ /* skip inactive plane */
	8055	+ if (!vop2_plane_active(pstate))
	8056	+ continue;
	8057	+
	8058	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 &&
	8059	+ vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
	8060	+ have_sdr_layer = true;
	8061	+ break;
	8062	+ }
	8063	+ }
	8064	+
	8065	+ if (hdr_mode == PQHDR2SDR_WITH_DYNAMIC \|\| hdr_mode == HLG2SDR_WITH_DYNAMIC \|\|
	8066	+ hdr_mode == HLG2SDR_WITHOUT_DYNAMIC \|\| hdr_mode == HDR102SDR) {
	8067	+ vpstate->hdr2sdr_en = true;
	8068	+ } else {
	8069	+ vp->hdr_out = true;
	8070	+ if (have_sdr_layer)
	8071	+ vp->sdr2hdr_en = true;
	8072	+ }
	8073	+
	8074	+ /**
	8075	+ * Config hdr ctrl registers
	8076	+ */
	8077	+ vop2_writel(vop2, RK3528_SDR2HDR_CTRL, hdrvivid_data->sdr2hdr_ctrl);
	8078	+ vop2_writel(vop2, RK3528_HDRVIVID_CTRL, hdrvivid_data->hdrvivid_ctrl);
	8079	+
	8080	+ VOP_MODULE_SET(vop2, vp, hdr10_en, vp->hdr_en);
	8081	+ if (vp->hdr_en) {
	8082	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, (hdr_mode == HDR_BYPASS) ? 0 : 1);
	8083	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_path_mode,
	8084	+ (hdr_mode == HDR102SDR) ? PQHDR2SDR_WITH_DYNAMIC : hdr_mode);
	8085	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_bypass_en, (hdr_mode == HDR_BYPASS) ? 1 : 0);
	8086	+ } else {
	8087	+ VOP_MODULE_SET(vop2, vp, hdr_vivid_en, 0);
	8088	+ }
	8089	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_en, vp->sdr2hdr_en);
	8090	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_path_en, vp->sdr2hdr_en);
	8091	+ VOP_MODULE_SET(vop2, vp, sdr2hdr_auto_gating_en, vp->sdr2hdr_en ? 0 : 1);
	8092	+
	8093	+ vop2_writel(vop2, RK3528_SDR_CFG_COE0, hdrvivid_data->sdr2hdr_coe0);
	8094	+ vop2_writel(vop2, RK3528_SDR_CFG_COE1, hdrvivid_data->sdr2hdr_coe1);
	8095	+ vop2_writel(vop2, RK3528_SDR_CSC_COE00_01, hdrvivid_data->sdr2hdr_csc_coe00_01);
	8096	+ vop2_writel(vop2, RK3528_SDR_CSC_COE02_10, hdrvivid_data->sdr2hdr_csc_coe02_10);
	8097	+ vop2_writel(vop2, RK3528_SDR_CSC_COE11_12, hdrvivid_data->sdr2hdr_csc_coe11_12);
	8098	+ vop2_writel(vop2, RK3528_SDR_CSC_COE20_21, hdrvivid_data->sdr2hdr_csc_coe20_21);
	8099	+ vop2_writel(vop2, RK3528_SDR_CSC_COE22, hdrvivid_data->sdr2hdr_csc_coe22);
	8100	+
	8101	+ vop2_writel(vop2, RK3528_HDR_PQ_GAMMA, hdrvivid_data->hdr_pq_gamma);
	8102	+ vop2_writel(vop2, RK3528_HLG_RFIX_SCALEFAC, hdrvivid_data->hlg_rfix_scalefac);
	8103	+ vop2_writel(vop2, RK3528_HLG_MAXLUMA, hdrvivid_data->hlg_maxluma);
	8104	+ vop2_writel(vop2, RK3528_HLG_R_TM_LIN2NON, hdrvivid_data->hlg_r_tm_lin2non);
	8105	+
	8106	+ vop2_writel(vop2, RK3528_HDR_CSC_COE00_01, hdrvivid_data->hdr_csc_coe00_01);
	8107	+ vop2_writel(vop2, RK3528_HDR_CSC_COE02_10, hdrvivid_data->hdr_csc_coe02_10);
	8108	+ vop2_writel(vop2, RK3528_HDR_CSC_COE11_12, hdrvivid_data->hdr_csc_coe11_12);
	8109	+ vop2_writel(vop2, RK3528_HDR_CSC_COE20_21, hdrvivid_data->hdr_csc_coe20_21);
	8110	+ vop2_writel(vop2, RK3528_HDR_CSC_COE22, hdrvivid_data->hdr_csc_coe22);
	8111	+
	8112	+ if (!vp->hdr_lut_gem_obj) {
	8113	+ lut_gem_obj = rockchip_gem_create_object(vop2->drm_dev,
	8114	+ RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH * 4, true, 0);
	8115	+ if (IS_ERR(lut_gem_obj)) {
	8116	+ DRM_ERROR("create hdr lut obj failed\n");
	8117	+ return;
	8118	+ }
	8119	+ vp->hdr_lut_gem_obj = lut_gem_obj;
	8120	+ }
	8121	+
	8122	+ tone_lut_kvaddr = (u32 *)vp->hdr_lut_gem_obj->kvaddr;
	8123	+ tone_lut_mst = vp->hdr_lut_gem_obj->dma_addr;
	8124	+
	8125	+ for (i = 0; i < RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH; i++)
	8126	+ *tone_lut_kvaddr++ = hdrvivid_data->tone_sca_axi_tab[i];
	8127	+
	8128	+ VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid - vp->id);
	8129	+ VOP_MODULE_SET(vop2, vp, hdr_lut_mode, 1);
	8130	+ VOP_MODULE_SET(vop2, vp, hdr_lut_mst, tone_lut_mst);
	8131	+ VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 1);
	8132	+ VOP_CTRL_SET(vop2, lut_dma_en, 1);
	8133	+
	8134	+ for (i = 0; i < RK_HDRVIVID_GAMMA_CURVE_LENGTH; i++)
	8135	+ vop2_writel(vop2, RK3528_HDRGAMMA_CURVE + i * 4, hdrvivid_data->hdrgamma_curve[i]);
	8136	+
	8137	+ for (i = 0; i < RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH; i++)
	8138	+ vop2_writel(vop2, RK3528_HDRGAMMA_MDFVALUE + i * 4,
	8139	+ hdrvivid_data->hdrgamma_mdfvalue[i]);
	8140	+
	8141	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_CURVE_LENGTH; i++)
	8142	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_CURVE + i * 4,
	8143	+ hdrvivid_data->sdrinvgamma_curve[i]);
	8144	+
	8145	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH; i++)
	8146	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_STARTIDX + i * 4,
	8147	+ hdrvivid_data->sdrinvgamma_startidx[i]);
	8148	+
	8149	+ for (i = 0; i < RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH; i++)
	8150	+ vop2_writel(vop2, RK3528_SDRINVGAMMA_CHANGEIDX + i * 4,
	8151	+ hdrvivid_data->sdrinvgamma_changeidx[i]);
	8152	+
	8153	+ for (i = 0; i < RK_SDR2HDR_SMGAIN_LENGTH; i++)
	8154	+ vop2_writel(vop2, RK3528_SDR_SMGAIN + i * 4, hdrvivid_data->sdr_smgain[i]);
	8155	+}
	8156	+
	8157	+static void vop3_setup_dynamic_hdr(struct vop2_video_port *vp, uint8_t win_phys_id)
	8158	+{
	8159	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
	8160	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8161	+ struct hdr_extend *hdr_data;
	8162	+ uint32_t hdr_format;
	8163	+
	8164	+ /* If hdr extend data is null, exit hdr mode */
	8165	+ if (!vcstate->hdr_ext_data) {
	8166	+ vop3_disable_dynamic_hdr(vp, win_phys_id);
	8167	+ return;
	8168	+ }
	8169	+
	8170	+ hdr_data = (struct hdr_extend *)vcstate->hdr_ext_data->data;
	8171	+ hdr_format = hdr_data->hdr_type;
	8172	+
	8173	+ switch (hdr_format) {
	8174	+ case HDR_NONE:
	8175	+ case HDR_HDR10:
	8176	+ case HDR_HLGSTATIC:
	8177	+ case HDR_HDRVIVID:
	8178	+ /*
	8179	+ * hdr module support hdr10, hlg, vividhdr
	8180	+ * sdr2hdr module support hdrnone for sdr2hdr
	8181	+ */
	8182	+ vop3_setup_hdrvivid(vp, win_phys_id);
	8183	+ break;
	8184	+ default:
	8185	+ DRM_DEBUG("unsupprot hdr format:%u\n", hdr_format);
	8186	+ break;
	8187	+ }
5157	8188	}
5158	8189
5159	8190	static void vop2_setup_hdr10(struct vop2_video_port *vp, uint8_t win_phys_id)
..	..	@@ -5161,13 +8192,13 @@
5161	8192	struct vop2 *vop2 = vp->vop2;
5162	8193	struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
5163	8194	struct drm_plane *plane = &win->base;
5164		- struct drm_plane_state *pstate = plane->state;
5165		- struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
5166		- struct drm_crtc_state *cstate = vp->crtc.state;
5167		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8195	+ struct drm_plane_state *pstate;
	8196	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
5168	8197	const struct vop2_data *vop2_data = vop2->data;
5169	8198	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5170	8199	const struct vop_hdr_table *hdr_table = vp_data->hdr_table;
	8200	+ struct rockchip_crtc_state *vcstate;
	8201	+ struct vop2_plane_state *vpstate;
5171	8202	uint32_t lut_mode = VOP2_HDR_LUT_MODE_AHB;
5172	8203	uint32_t sdr2hdr_r2r_mode = 0;
5173	8204	bool hdr_en = 0;
..	..	@@ -5187,14 +8218,27 @@
5187	8218	return;
5188	8219
5189	8220	/*
	8221	+ * right vp share the same crtc/plane state in splice mode
	8222	+ */
	8223	+ if (vp->splice_mode_right) {
	8224	+ vcstate = to_rockchip_crtc_state(vp->left_vp->rockchip_crtc.crtc.state);
	8225	+ pstate = win->left_win->base.state;
	8226	+ } else {
	8227	+ vcstate = to_rockchip_crtc_state(cstate);
	8228	+ pstate = plane->state;
	8229	+ }
	8230	+
	8231	+ vpstate = to_vop2_plane_state(pstate);
	8232	+
	8233	+ /*
5190	8234	* HDR video plane input
5191	8235	*/
5192		- if (vpstate->eotf == SMPTE_ST2084)
	8236	+ if (vpstate->eotf == HDMI_EOTF_SMPTE_ST2084)
5193	8237	hdr_en = 1;
5194	8238
5195	8239	vp->hdr_en = hdr_en;
5196	8240	vp->hdr_in = hdr_en;
5197		- vp->hdr_out = (vcstate->eotf == SMPTE_ST2084) ? true : false;
	8241	+ vp->hdr_out = (vcstate->eotf == HDMI_EOTF_SMPTE_ST2084) ? true : false;
5198	8242
5199	8243	/*
5200	8244	* only laryer0 support hdr2sdr
..	..	@@ -5212,15 +8256,21 @@
5212	8256	*/
5213	8257	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
5214	8258	win = vop2_find_win_by_phys_id(vop2, phys_id);
5215		- plane = &win->base;
5216		- pstate = plane->state;
5217		- vpstate = to_vop2_plane_state(pstate);
	8259	+ if (vp->splice_mode_right) {
	8260	+ if (win->left_win)
	8261	+ pstate = win->left_win->base.state;
	8262	+ else
	8263	+ pstate = NULL; /* this win is not activated */
	8264	+ } else {
	8265	+ pstate = win->base.state;
	8266	+ }
5218	8267
5219		- /* skip inactive plane */
	8268	+ vpstate = pstate ? to_vop2_plane_state(pstate) : NULL;
	8269	+
5220	8270	if (!vop2_plane_active(pstate))
5221	8271	continue;
5222	8272
5223		- if (vpstate->eotf != SMPTE_ST2084) {
	8273	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084) {
5224	8274	have_sdr_layer = true;
5225	8275	break;
5226	8276	}
..	..	@@ -5367,7 +8417,15 @@
5367	8417
5368	8418	if (!sub_win) {
5369	8419	/* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
5370		- plane = &main_win->base;
	8420	+
	8421	+ /*
	8422	+ * right cluster share the same plane state in splice mode
	8423	+ */
	8424	+ if (cluster->splice_mode)
	8425	+ plane = &main_win->left_win->base;
	8426	+ else
	8427	+ plane = &main_win->base;
	8428	+
5371	8429	top_win_vpstate = NULL;
5372	8430	bottom_win_vpstate = to_vop2_plane_state(plane->state);
5373	8431	src_glb_alpha_val = 0;
..	..	@@ -5426,25 +8484,35 @@
5426	8484	uint32_t dst_color_ctrl_offset = vop2->data->ctrl->dst_color_ctrl.offset;
5427	8485	uint32_t src_alpha_ctrl_offset = vop2->data->ctrl->src_alpha_ctrl.offset;
5428	8486	uint32_t dst_alpha_ctrl_offset = vop2->data->ctrl->dst_alpha_ctrl.offset;
	8487	+ unsigned long win_mask = vp->win_mask;
5429	8488	const struct vop2_zpos *zpos;
5430		- struct drm_framebuffer *fb;
	8489	+ struct vop2_plane_state *vpstate;
5431	8490	struct vop2_alpha_config alpha_config;
5432	8491	struct vop2_alpha alpha;
5433	8492	struct vop2_win *win;
5434		- struct drm_plane *plane;
5435		- struct vop2_plane_state *vpstate;
	8493	+ struct drm_plane_state *pstate;
	8494	+ struct drm_framebuffer *fb;
5436	8495	int pixel_alpha_en;
5437		- int premulti_en;
	8496	+ int premulti_en = 1;
5438	8497	int mixer_id;
	8498	+ int phys_id;
5439	8499	uint32_t offset;
5440	8500	int i;
5441	8501	bool bottom_layer_alpha_en = false;
5442	8502	u32 dst_global_alpha = 0xff;
5443	8503
5444		- drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
5445		- struct vop2_win *win = to_vop2_win(plane);
	8504	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	8505	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	8506	+ if (win->splice_mode_right)
	8507	+ pstate = win->left_win->base.state;
	8508	+ else
	8509	+ pstate = win->base.state;
5446	8510
5447		- vpstate = to_vop2_plane_state(plane->state);
	8511	+ vpstate = to_vop2_plane_state(pstate);
	8512	+
	8513	+ if (!vop2_plane_active(pstate))
	8514	+ continue;
	8515	+
5448	8516	if (vpstate->zpos == 0 && vpstate->global_alpha != 0xff &&
5449	8517	!vop2_cluster_window(win)) {
5450	8518	/*
..	..	@@ -5454,19 +8522,33 @@
5454	8522	*/
5455	8523	bottom_layer_alpha_en = true;
5456	8524	dst_global_alpha = vpstate->global_alpha;
	8525	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8526	+ premulti_en = 1;
	8527	+ else
	8528	+ premulti_en = 0;
	8529	+
5457	8530	break;
5458	8531	}
5459	8532	}
5460	8533
5461	8534	mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
	8535	+
	8536	+ if (vop2->version == VOP_VERSION_RK3588 &&
	8537	+ vp->hdr10_at_splice_mode && vp->id == 0)
	8538	+ mixer_id++;/* fixed path for rk3588: layer1 -> hdr10_1 */
	8539	+
5462	8540	alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
5463	8541	for (i = 1; i < vp->nr_layers; i++) {
5464	8542	zpos = &vop2_zpos[i];
5465	8543	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
5466		- plane = &win->base;
5467		- vpstate = to_vop2_plane_state(plane->state);
5468		- fb = plane->state->fb;
5469		- if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8544	+ if (win->splice_mode_right)
	8545	+ pstate = win->left_win->base.state;
	8546	+ else
	8547	+ pstate = win->base.state;
	8548	+
	8549	+ vpstate = to_vop2_plane_state(pstate);
	8550	+ fb = pstate->fb;
	8551	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
5470	8552	premulti_en = 1;
5471	8553	else
5472	8554	premulti_en = 0;
..	..	@@ -5496,29 +8578,27 @@
5496	8578	vop2_writel(vop2, dst_color_ctrl_offset + offset, alpha.dst_color_ctrl.val);
5497	8579	vop2_writel(vop2, src_alpha_ctrl_offset + offset, alpha.src_alpha_ctrl.val);
5498	8580	vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
	8581	+ }
5499	8582
5500		- if (i == 1) {
5501		- if (bottom_layer_alpha_en \|\| vp->hdr_en) {
5502		- /* Transfer pixel alpha to hdr mix */
5503		- alpha_config.src_premulti_en = premulti_en;
5504		- alpha_config.dst_premulti_en = true;
5505		- alpha_config.src_pixel_alpha_en = true;
5506		- alpha_config.src_glb_alpha_value = 0xff;
5507		- alpha_config.dst_glb_alpha_value = 0xff;
5508		- vop2_parse_alpha(&alpha_config, &alpha);
	8583	+ if (bottom_layer_alpha_en \|\| vp->hdr_en) {
	8584	+ /* Transfer pixel alpha to hdr mix */
	8585	+ alpha_config.src_premulti_en = premulti_en;
	8586	+ alpha_config.dst_premulti_en = true;
	8587	+ alpha_config.src_pixel_alpha_en = true;
	8588	+ alpha_config.src_glb_alpha_value = 0xff;
	8589	+ alpha_config.dst_glb_alpha_value = 0xff;
	8590	+ vop2_parse_alpha(&alpha_config, &alpha);
5509	8591
5510		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
5511		- alpha.src_color_ctrl.val);
5512		- VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
5513		- alpha.dst_color_ctrl.val);
5514		- VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
5515		- alpha.src_alpha_ctrl.val);
5516		- VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
5517		- alpha.dst_alpha_ctrl.val);
5518		- } else {
5519		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5520		- }
5521		- }
	8592	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
	8593	+ alpha.src_color_ctrl.val);
	8594	+ VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
	8595	+ alpha.dst_color_ctrl.val);
	8596	+ VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
	8597	+ alpha.src_alpha_ctrl.val);
	8598	+ VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
	8599	+ alpha.dst_alpha_ctrl.val);
	8600	+ } else {
	8601	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5522	8602	}
5523	8603
5524	8604	/* Transfer pixel alpha value to next mix */
..	..	@@ -5648,7 +8728,7 @@
5648	8728	vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
5649	8729	}
5650	8730
5651		- if (vp_data->feature & VOP_FEATURE_HDR10) {
	8731	+ if (vp_data->feature & (VOP_FEATURE_HDR10 \| VOP_FEATURE_VIVID_HDR)) {
5652	8732	src_color_ctrl_offset = ovl_regs->hdr_mix_regs->src_color_ctrl.offset;
5653	8733	dst_color_ctrl_offset = ovl_regs->hdr_mix_regs->dst_color_ctrl.offset;
5654	8734	src_alpha_ctrl_offset = ovl_regs->hdr_mix_regs->src_alpha_ctrl.offset;
..	..	@@ -5679,21 +8759,6 @@
5679	8759	VOP_MODULE_SET(vop2, vp, bg_mix_ctrl, bg_alpha_ctrl.val);
5680	8760	}
5681	8761
5682		-static void vop2_setup_port_mux(struct vop2_video_port *vp, uint16_t port_mux_cfg)
5683		-{
5684		- struct vop2 *vop2 = vp->vop2;
5685		-
5686		- spin_lock(&vop2->reg_lock);
5687		- if (vop2->port_mux_cfg != port_mux_cfg) {
5688		- VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
5689		- vp->skip_vsync = true;
5690		- vop2_cfg_done(&vp->crtc);
5691		- vop2->port_mux_cfg = port_mux_cfg;
5692		- vop2_wait_for_port_mux_done(vop2);
5693		- }
5694		- spin_unlock(&vop2->reg_lock);
5695		-}
5696		-
5697	8762	static u32 vop2_layer_cfg_update(struct vop2_layer *layer, u32 old_layer_cfg, u8 win_layer_id)
5698	8763	{
5699	8764	const struct vop_reg *reg = &layer->regs->layer_sel;
..	..	@@ -5716,6 +8781,12 @@
5716	8781	for (i = 0; i < vop2_data->nr_vps - 1; i++) {
5717	8782	prev_vp = &vop2->vps[i];
5718	8783	used_layers += hweight32(prev_vp->win_mask);
	8784	+ if (vop2->version == VOP_VERSION_RK3588) {
	8785	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 0)
	8786	+ used_layers += 1;
	8787	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 1)
	8788	+ used_layers -= 1;
	8789	+ }
5719	8790	/*
5720	8791	* when a window move from vp0 to vp1, or vp0 to vp2,
5721	8792	* it should flow these steps:
..	..	@@ -5741,10 +8812,26 @@
5741	8812	prev_vp->bg_ovl_dly = (vop2_data->nr_mixers - port_mux) << 1;
5742	8813	}
5743	8814
5744		- if (vop2->data->nr_vps >= 1)
5745		- port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
	8815	+ port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
5746	8816
5747	8817	return port_mux_cfg;
	8818	+}
	8819	+
	8820	+static void vop2_setup_port_mux(struct vop2_video_port *vp)
	8821	+{
	8822	+ struct vop2 *vop2 = vp->vop2;
	8823	+ u16 port_mux_cfg;
	8824	+
	8825	+ port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
	8826	+ spin_lock(&vop2->reg_lock);
	8827	+ if (vop2->port_mux_cfg != port_mux_cfg) {
	8828	+ VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
	8829	+ vp->skip_vsync = true;
	8830	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	8831	+ vop2->port_mux_cfg = port_mux_cfg;
	8832	+ vop2_wait_for_port_mux_done(vop2);
	8833	+ }
	8834	+ spin_unlock(&vop2->reg_lock);
5748	8835	}
5749	8836
5750	8837	static void vop2_setup_layer_mixer_for_vp(struct vop2_video_port *vp,
..	..	@@ -5758,15 +8845,12 @@
5758	8845	struct vop2_win *win;
5759	8846	u8 used_layers = 0;
5760	8847	u8 layer_id, win_phys_id;
5761		- u16 port_mux_cfg;
5762	8848	u32 layer_cfg_reg_offset = layer->regs->layer_sel.offset;
5763	8849	u8 nr_layers = vp->nr_layers;
5764	8850	u32 old_layer_cfg = 0;
5765	8851	u32 new_layer_cfg = 0;
5766	8852	u32 atv_layer_cfg;
5767	8853	int i;
5768		-
5769		- port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
5770	8854
5771	8855	/*
5772	8856	* Win and layer must map one by one, if a win is selected
..	..	@@ -5782,6 +8866,10 @@
5782	8866
5783	8867	old_layer_cfg = vop2->regsbak[layer_cfg_reg_offset >> 2];
5784	8868	new_layer_cfg = old_layer_cfg;
	8869	+
	8870	+ if (vp->hdr10_at_splice_mode)
	8871	+ nr_layers *= 2;
	8872	+
5785	8873	for (i = 0; i < nr_layers; i++) {
5786	8874	layer = &vop2->layers[used_layers + i];
5787	8875	zpos = &vop2_zpos[i];
..	..	@@ -5795,21 +8883,21 @@
5795	8883	layer = &vop2->layers[layer_id];
5796	8884	win = vop2_find_win_by_phys_id(vop2, win_phys_id);
5797	8885	new_layer_cfg = vop2_layer_cfg_update(layer, new_layer_cfg, win->layer_sel_id[vp->id]);
5798		- win->layer_id = layer->id;
5799	8886	win->layer_id = layer_id;
5800	8887	layer->win_phys_id = win_phys_id;
5801	8888	}
5802	8889
5803	8890	atv_layer_cfg = vop2_read_layer_cfg(vop2);
5804		- if ((new_layer_cfg != old_layer_cfg) &&
5805		- (atv_layer_cfg != old_layer_cfg)) {
	8891	+ if (new_layer_cfg != old_layer_cfg &&
	8892	+ atv_layer_cfg != old_layer_cfg &&
	8893	+ !vp->splice_mode_right) {
5806	8894	dev_dbg(vop2->dev, "wait old_layer_sel: 0x%x\n", old_layer_cfg);
5807	8895	vop2_wait_for_layer_cfg_done(vop2, old_layer_cfg);
5808	8896	}
5809	8897	vop2_writel(vop2, RK3568_OVL_LAYER_SEL, new_layer_cfg);
5810		- VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
	8898	+ if (new_layer_cfg != old_layer_cfg)
	8899	+ VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
5811	8900	VOP_CTRL_SET(vop2, ovl_port_mux_cfg_done_imd, 0);
5812		- vop2_setup_port_mux(vp, port_mux_cfg);
5813	8901	}
5814	8902
5815	8903	static void vop3_setup_layer_sel_for_vp(struct vop2_video_port *vp,
..	..	@@ -5852,7 +8940,9 @@
5852	8940	struct vop2 *vop2 = vp->vop2;
5853	8941	const struct vop2_data *vop2_data = vop2->data;
5854	8942	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5855		- struct drm_crtc *crtc = &vp->crtc;
	8943	+ struct vop2_video_port *left_vp = vp->left_vp;
	8944	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	8945	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
5856	8946	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
5857	8947	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
5858	8948	u16 hdisplay = adjusted_mode->crtc_hdisplay;
..	..	@@ -5871,13 +8961,30 @@
5871	8961	}
5872	8962	}
5873	8963
5874		- if (!vp->hdr_in)
	8964	+ if (!vp->hdr_in \|\|
	8965	+ (vop2->version == VOP_VERSION_RK3588 && vp->hdr_out))
5875	8966	bg_dly -= vp->bg_ovl_dly;
5876	8967
5877		- pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
5878		- if (vop2->version >= VOP_VERSION_RK3588 && hsync_len < 8)
	8968	+ /*
	8969	+ * right vp share the same crtc state in splice mode
	8970	+ */
	8971	+ if (vp->splice_mode_right) {
	8972	+ vcstate = to_rockchip_crtc_state(left_vp->rockchip_crtc.crtc.state);
	8973	+ adjusted_mode = &left_vp->rockchip_crtc.crtc.state->adjusted_mode;
	8974	+ hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	8975	+ hdisplay = adjusted_mode->crtc_hdisplay;
	8976	+ }
	8977	+
	8978	+ if (vcstate->splice_mode)
	8979	+ pre_scan_dly = bg_dly + (hdisplay >> 2) - 1;
	8980	+ else
	8981	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	8982	+
	8983	+ if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8)
5879	8984	hsync_len = 8;
	8985	+
5880	8986	pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	8987	+
5881	8988	VOP_MODULE_SET(vop2, vp, bg_dly, bg_dly);
5882	8989	VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
5883	8990	}
..	..	@@ -5895,8 +9002,17 @@
5895	9002	for (i = 0; i < vp->nr_layers; i++) {
5896	9003	zpos = &vop2_zpos[i];
5897	9004	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
5898		- plane = &win->base;
5899		- vpstate = to_vop2_plane_state(plane->state);
	9005	+ /*
	9006	+ * right vp share the same plane state in splice mode
	9007	+ */
	9008	+ if (vp->splice_mode_right) {
	9009	+ plane = &win->left_win->base;
	9010	+ vpstate = to_vop2_plane_state(plane->state);
	9011	+ } else {
	9012	+ plane = &win->base;
	9013	+ vpstate = to_vop2_plane_state(plane->state);
	9014	+ }
	9015	+
5900	9016	if (vp->hdr_in && !vp->hdr_out && !vpstate->hdr_in) {
5901	9017	dly = win->dly[VOP2_DLY_MODE_HISO_S];
5902	9018	dly += vp->bg_ovl_dly;
..	..	@@ -5913,21 +9029,128 @@
5913	9029	}
5914	9030	}
5915	9031
	9032	+static void rk3588_vop2_setup_hdr10_splice_layer_mixer(struct drm_crtc *crtc,
	9033	+ struct vop2_zpos *vop2_zpos,
	9034	+ struct vop2_zpos *vop2_zpos_splice)
	9035	+{
	9036	+ int zpos_id, i;
	9037	+ struct vop2_zpos *vop2_zpos_splice_hdr;
	9038	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9039	+ struct vop2 *vop2 = vp->vop2;
	9040	+
	9041	+ vop2_zpos_splice_hdr = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9042	+ GFP_KERNEL);
	9043	+ if (!vop2_zpos_splice_hdr)
	9044	+ goto out;
	9045	+
	9046	+ zpos_id = 0;
	9047	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9048	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[0].win_phys_id;
	9049	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[0].plane;
	9050	+
	9051	+ zpos_id++;
	9052	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9053	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[0].win_phys_id;
	9054	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[0].plane;
	9055	+
	9056	+ for (i = 1; i < vp->nr_layers; i++) {
	9057	+ zpos_id++;
	9058	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9059	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[i].win_phys_id;
	9060	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[i].plane;
	9061	+ }
	9062	+
	9063	+ for (i = 1; i < vp->nr_layers; i++) {
	9064	+ zpos_id++;
	9065	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9066	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[i].win_phys_id;
	9067	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[i].plane;
	9068	+ }
	9069	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos_splice_hdr);
	9070	+
	9071	+out:
	9072	+ kfree(vop2_zpos_splice_hdr);
	9073	+}
	9074	+
	9075	+static void vop2_crtc_update_vrr(struct drm_crtc *crtc)
	9076	+{
	9077	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9078	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9079	+ struct vop2 *vop2 = vp->vop2;
	9080	+ struct drm_display_mode *adjust_mode = &crtc->state->adjusted_mode;
	9081	+
	9082	+ unsigned int vrefresh;
	9083	+ unsigned int new_vtotal, vfp, new_vfp;
	9084	+
	9085	+ if (!vp->refresh_rate_change)
	9086	+ return;
	9087	+
	9088	+ if (!vcstate->min_refresh_rate \|\| !vcstate->max_refresh_rate)
	9089	+ return;
	9090	+
	9091	+ if (vcstate->request_refresh_rate < vcstate->min_refresh_rate \|\|
	9092	+ vcstate->request_refresh_rate > vcstate->max_refresh_rate) {
	9093	+ DRM_ERROR("invalid rate:%d\n", vcstate->request_refresh_rate);
	9094	+ return;
	9095	+ }
	9096	+
	9097	+ vrefresh = drm_mode_vrefresh(adjust_mode);
	9098	+
	9099	+ /* calculate new vfp for new refresh rate */
	9100	+ new_vtotal = adjust_mode->vtotal * vrefresh / vcstate->request_refresh_rate;
	9101	+ vfp = adjust_mode->vsync_start - adjust_mode->vdisplay;
	9102	+ new_vfp = vfp + new_vtotal - adjust_mode->vtotal;
	9103	+
	9104	+ /* config vop2 vtotal register */
	9105	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, new_vtotal);
	9106	+
	9107	+ /* config dsc vtotal register */
	9108	+ if (vcstate->dsc_enable) {
	9109	+ struct vop2_dsc *dsc;
	9110	+
	9111	+ dsc = &vop2->dscs[vcstate->dsc_id];
	9112	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9113	+
	9114	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	9115	+ dsc = &vop2->dscs[vcstate->dsc_id ? 0 : 1];
	9116	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9117	+ }
	9118	+ }
	9119	+
	9120	+ /* config all connectors attach to this crtc */
	9121	+ rockchip_connector_update_vfp_for_vrr(crtc, adjust_mode, new_vfp);
	9122	+}
	9123	+
5916	9124	static void vop2_crtc_atomic_begin(struct drm_crtc crtc, struct drm_crtc_state old_crtc_state)
5917	9125	{
5918	9126	struct vop2_video_port *vp = to_vop2_video_port(crtc);
5919	9127	struct vop2 *vop2 = vp->vop2;
	9128	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9129	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
5920	9130	struct drm_plane *plane;
5921	9131	struct vop2_plane_state *vpstate;
5922	9132	struct vop2_zpos *vop2_zpos;
	9133	+ struct vop2_zpos *vop2_zpos_splice;
5923	9134	struct vop2_cluster cluster;
5924	9135	uint8_t nr_layers = 0;
	9136	+ uint8_t splice_nr_layers = 0;
	9137	+ bool hdr10_in = false;
	9138	+ bool hdr10_at_splice_mode = false;
5925	9139	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
5926	9140
5927	9141	vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
5928	9142	vop2_zpos = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos), GFP_KERNEL);
5929	9143	if (!vop2_zpos)
5930	9144	return;
	9145	+ if (vcstate->splice_mode) {
	9146	+ vop2_zpos_splice = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9147	+ GFP_KERNEL);
	9148	+ if (!vop2_zpos_splice)
	9149	+ goto out;
	9150	+ }
	9151	+
	9152	+ if (vop2->version == VOP_VERSION_RK3588)
	9153	+ vop2_crtc_update_vrr(crtc);
5931	9154
5932	9155	/* Process cluster sub windows overlay. */
5933	9156	drm_atomic_crtc_for_each_plane(plane, crtc) {
..	..	@@ -5937,9 +9160,13 @@
5937	9160	win->two_win_mode = false;
5938	9161	if (!(win->feature & WIN_FEATURE_CLUSTER_SUB))
5939	9162	continue;
	9163	+ if (vcstate->splice_mode)
	9164	+ DRM_ERROR("vp%d %s not supported two win mode at splice mode\n",
	9165	+ vp->id, win->name);
5940	9166	main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
5941	9167	cluster.main = main_win;
5942	9168	cluster.sub = win;
	9169	+ cluster.splice_mode = false;
5943	9170	win->two_win_mode = true;
5944	9171	main_win->two_win_mode = true;
5945	9172	vop2_setup_cluster_alpha(vop2, &cluster);
..	..	@@ -5951,6 +9178,7 @@
5951	9178
5952	9179	drm_atomic_crtc_for_each_plane(plane, crtc) {
5953	9180	struct vop2_win *win = to_vop2_win(plane);
	9181	+ struct vop2_win *splice_win;
5954	9182	struct vop2_video_port *old_vp;
5955	9183	uint8_t old_vp_id;
5956	9184
..	..	@@ -5970,38 +9198,102 @@
5970	9198	vop2_zpos[nr_layers].win_phys_id = win->phys_id;
5971	9199	vop2_zpos[nr_layers].zpos = vpstate->zpos;
5972	9200	vop2_zpos[nr_layers].plane = plane;
	9201	+
	9202	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "%s active zpos:%d for vp%d from vp%d\n",
	9203	+ win->name, vpstate->zpos, vp->id, old_vp->id);
	9204	+ /* left and right win may have different number */
	9205	+ if (vcstate->splice_mode) {
	9206	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	9207	+ splice_win->splice_mode_right = true;
	9208	+ splice_win->left_win = win;
	9209	+ win->splice_win = splice_win;
	9210	+
	9211	+ old_vp_id = ffs(splice_win->vp_mask);
	9212	+ old_vp_id = (old_vp_id == 0) ? 0 : old_vp_id - 1;
	9213	+ old_vp = &vop2->vps[old_vp_id];
	9214	+ old_vp->win_mask &= ~BIT(splice_win->phys_id);
	9215	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	9216	+ splice_win->vp_mask = BIT(splice_vp->id);
	9217	+ hdr10_in \|= vpstate->eotf == HDMI_EOTF_SMPTE_ST2084 ? true : false;
	9218	+ vop2_zpos_splice[splice_nr_layers].win_phys_id = splice_win->phys_id;
	9219	+ vop2_zpos_splice[splice_nr_layers].zpos = vpstate->zpos;
	9220	+ vop2_zpos_splice[splice_nr_layers].plane = &splice_win->base;
	9221	+ splice_nr_layers++;
	9222	+ DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
	9223	+ splice_win->name, vpstate->zpos, splice_vp->id, old_vp->id);
	9224	+ }
5973	9225	nr_layers++;
5974		- DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
5975		- win->name, vpstate->zpos, vp->id, old_vp->id);
5976	9226	}
5977	9227
5978		- DRM_DEV_DEBUG(vop2->dev, "vp%d: %d windows, active layers %d\n",
5979		- vp->id, hweight32(vp->win_mask), nr_layers);
	9228	+ if (vcstate->splice_mode) {
	9229	+ if (hdr10_in)
	9230	+ hdr10_at_splice_mode = true;
	9231	+
	9232	+ splice_vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9233	+ }
	9234	+ vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9235	+
	9236	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "vp%d: %d windows, active layers %d\n",
	9237	+ vp->id, hweight32(vp->win_mask), nr_layers);
5980	9238	if (nr_layers) {
5981	9239	vp->nr_layers = nr_layers;
5982	9240
5983	9241	sort(vop2_zpos, nr_layers, sizeof(vop2_zpos[0]), vop2_zpos_cmp, NULL);
5984	9242
5985		- if (is_vop3(vop2))
5986		- vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
5987		- else
5988		- vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
5989		- vop2_setup_hdr10(vp, vop2_zpos[0].win_phys_id);
5990		- if (is_vop3(vop2))
	9243	+ if (!vp->hdr10_at_splice_mode) {
	9244	+ if (is_vop3(vop2)) {
	9245	+ vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
	9246	+ } else {
	9247	+ vop2_setup_port_mux(vp);
	9248	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
	9249	+ }
	9250	+ }
	9251	+
	9252	+ if (is_vop3(vop2)) {
	9253	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	9254	+ vop3_setup_dynamic_hdr(vp, vop2_zpos[0].win_phys_id);
5991	9255	vop3_setup_alpha(vp, vop2_zpos);
5992		- else
	9256	+ vop3_setup_pipe_dly(vp, vop2_zpos);
	9257	+ } else {
	9258	+ vop2_setup_hdr10(vp, vop2_zpos[0].win_phys_id);
5993	9259	vop2_setup_alpha(vp, vop2_zpos);
5994		- vop2_setup_dly_for_vp(vp);
5995		- vop2_setup_dly_for_window(vp, vop2_zpos);
	9260	+ vop2_setup_dly_for_vp(vp);
	9261	+ vop2_setup_dly_for_window(vp, vop2_zpos);
	9262	+ }
	9263	+
	9264	+ if (vcstate->splice_mode) {/* Fixme for VOP3 8K */
	9265	+ splice_vp->nr_layers = splice_nr_layers;
	9266	+
	9267	+ sort(vop2_zpos_splice, splice_nr_layers, sizeof(vop2_zpos_splice[0]),
	9268	+ vop2_zpos_cmp, NULL);
	9269	+
	9270	+ vop2_setup_port_mux(splice_vp);
	9271	+ if (!vp->hdr10_at_splice_mode)
	9272	+ vop2_setup_layer_mixer_for_vp(splice_vp, vop2_zpos_splice);
	9273	+ vop2_setup_hdr10(splice_vp, vop2_zpos_splice[0].win_phys_id);
	9274	+ vop2_setup_alpha(splice_vp, vop2_zpos_splice);
	9275	+ vop2_setup_dly_for_vp(splice_vp);
	9276	+ vop2_setup_dly_for_window(splice_vp, vop2_zpos_splice);
	9277	+
	9278	+ if (vop2->version == VOP_VERSION_RK3588 &&
	9279	+ vp->hdr10_at_splice_mode)
	9280	+ rk3588_vop2_setup_hdr10_splice_layer_mixer(crtc, vop2_zpos, vop2_zpos_splice);
	9281	+ }
5996	9282	} else {
5997		- if (!is_vop3(vop2))
	9283	+ if (!is_vop3(vop2)) {
5998	9284	vop2_calc_bg_ovl_and_port_mux(vp);
5999		- vop2_setup_dly_for_vp(vp);
	9285	+ vop2_setup_dly_for_vp(vp);
	9286	+ if (vcstate->splice_mode)
	9287	+ vop2_setup_dly_for_vp(splice_vp);
	9288	+ } else {
	9289	+ vop3_setup_pipe_dly(vp, NULL);
	9290	+ }
6000	9291	}
6001	9292
6002	9293	/* The pre alpha overlay of Cluster still need process in one win mode. */
6003	9294	drm_atomic_crtc_for_each_plane(plane, crtc) {
6004	9295	struct vop2_win *win = to_vop2_win(plane);
	9296	+ struct vop2_win *splice_win;
6005	9297
6006	9298	if (!(win->feature & WIN_FEATURE_CLUSTER_MAIN))
6007	9299	continue;
..	..	@@ -6009,9 +9301,19 @@
6009	9301	continue;
6010	9302	cluster.main = win;
6011	9303	cluster.sub = NULL;
	9304	+ cluster.splice_mode = false;
6012	9305	vop2_setup_cluster_alpha(vop2, &cluster);
	9306	+ if (vcstate->splice_mode) {
	9307	+ splice_win = win->splice_win;
	9308	+ cluster.main = splice_win;
	9309	+ cluster.splice_mode = true;
	9310	+ vop2_setup_cluster_alpha(vop2, &cluster);
	9311	+ }
6013	9312	}
6014	9313
	9314	+ if (vcstate->splice_mode)
	9315	+ kfree(vop2_zpos_splice);
	9316	+out:
6015	9317	kfree(vop2_zpos);
6016	9318	}
6017	9319
..	..	@@ -6122,6 +9424,155 @@
6122	9424	bcsh_state.cos_hue = cos_hue;
6123	9425
6124	9426	vop2_bcsh_reg_update(vcstate, vp, &bcsh_state);
	9427	+ if (vcstate->splice_mode) {
	9428	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9429	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	9430	+
	9431	+ vop2_bcsh_reg_update(vcstate, splice_vp, &bcsh_state);
	9432	+ }
	9433	+}
	9434	+
	9435	+static void vop3_post_csc_config(struct drm_crtc crtc, struct post_acm acm, struct post_csc *csc)
	9436	+{
	9437	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9438	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9439	+ struct vop2 *vop2 = vp->vop2;
	9440	+ struct post_csc_coef csc_coef;
	9441	+ bool acm_enable;
	9442	+ bool is_input_yuv = false;
	9443	+ bool is_output_yuv = false;
	9444	+ bool post_r2y_en = false;
	9445	+ bool post_csc_en = false;
	9446	+ int range_type;
	9447	+
	9448	+ if (!acm)
	9449	+ acm_enable = false;
	9450	+ else
	9451	+ acm_enable = acm->acm_enable;
	9452	+
	9453	+ if (acm_enable) {
	9454	+ if (!vcstate->yuv_overlay)
	9455	+ post_r2y_en = true;
	9456	+
	9457	+ /* do y2r in csc module */
	9458	+ if (!is_yuv_output(vcstate->bus_format))
	9459	+ post_csc_en = true;
	9460	+ } else {
	9461	+ if (!vcstate->yuv_overlay && is_yuv_output(vcstate->bus_format))
	9462	+ post_r2y_en = true;
	9463	+
	9464	+ /* do y2r in csc module */
	9465	+ if (vcstate->yuv_overlay && !is_yuv_output(vcstate->bus_format))
	9466	+ post_csc_en = true;
	9467	+ }
	9468	+
	9469	+ if (csc && csc->csc_enable)
	9470	+ post_csc_en = true;
	9471	+
	9472	+ if (vcstate->yuv_overlay \|\| post_r2y_en)
	9473	+ is_input_yuv = true;
	9474	+
	9475	+ if (is_yuv_output(vcstate->bus_format))
	9476	+ is_output_yuv = true;
	9477	+
	9478	+ vcstate->post_csc_mode = vop2_convert_csc_mode(vcstate->color_space, CSC_13BIT_DEPTH);
	9479	+
	9480	+ if (post_csc_en) {
	9481	+ rockchip_calc_post_csc(csc, &csc_coef, vcstate->post_csc_mode, is_input_yuv,
	9482	+ is_output_yuv);
	9483	+
	9484	+ VOP_MODULE_SET(vop2, vp, csc_coe00, csc_coef.csc_coef00);
	9485	+ VOP_MODULE_SET(vop2, vp, csc_coe01, csc_coef.csc_coef01);
	9486	+ VOP_MODULE_SET(vop2, vp, csc_coe02, csc_coef.csc_coef02);
	9487	+ VOP_MODULE_SET(vop2, vp, csc_coe10, csc_coef.csc_coef10);
	9488	+ VOP_MODULE_SET(vop2, vp, csc_coe11, csc_coef.csc_coef11);
	9489	+ VOP_MODULE_SET(vop2, vp, csc_coe12, csc_coef.csc_coef12);
	9490	+ VOP_MODULE_SET(vop2, vp, csc_coe20, csc_coef.csc_coef20);
	9491	+ VOP_MODULE_SET(vop2, vp, csc_coe21, csc_coef.csc_coef21);
	9492	+ VOP_MODULE_SET(vop2, vp, csc_coe22, csc_coef.csc_coef22);
	9493	+ VOP_MODULE_SET(vop2, vp, csc_offset0, csc_coef.csc_dc0);
	9494	+ VOP_MODULE_SET(vop2, vp, csc_offset1, csc_coef.csc_dc1);
	9495	+ VOP_MODULE_SET(vop2, vp, csc_offset2, csc_coef.csc_dc2);
	9496	+
	9497	+ range_type = csc_coef.range_type ? 0 : 1;
	9498	+ range_type <<= is_input_yuv ? 0 : 1;
	9499	+ VOP_MODULE_SET(vop2, vp, csc_mode, range_type);
	9500	+ }
	9501	+
	9502	+ VOP_MODULE_SET(vop2, vp, acm_r2y_en, post_r2y_en ? 1 : 0);
	9503	+ VOP_MODULE_SET(vop2, vp, csc_en, post_csc_en ? 1 : 0);
	9504	+ VOP_MODULE_SET(vop2, vp, acm_r2y_mode, vcstate->post_csc_mode);
	9505	+}
	9506	+
	9507	+static void vop3_post_acm_config(struct drm_crtc crtc, struct post_acm acm)
	9508	+{
	9509	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9510	+ struct vop2 *vop2 = vp->vop2;
	9511	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	9512	+ s16 *lut_y;
	9513	+ s16 *lut_h;
	9514	+ s16 *lut_s;
	9515	+ u32 value;
	9516	+ int i;
	9517	+
	9518	+ if (!acm) {
	9519	+ writel(0x2, vop2->acm_regs + RK3528_ACM_CTRL);
	9520	+ VOP_MODULE_SET(vop2, vp, acm_bypass_en, 1);
	9521	+ return;
	9522	+ }
	9523	+
	9524	+ writel(1, vop2->acm_regs + RK3528_ACM_FETCH_START);
	9525	+
	9526	+ value = (acm->acm_enable & 0x1) + ((adjusted_mode->hdisplay & 0xfff) << 8) +
	9527	+ ((adjusted_mode->vdisplay & 0xfff) << 20);
	9528	+ writel(value, vop2->acm_regs + RK3528_ACM_CTRL);
	9529	+ VOP_MODULE_SET(vop2, vp, acm_bypass_en, acm->acm_enable ? 0 : 1);
	9530	+
	9531	+ value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
	9532	+ ((acm->s_gain << 20) & 0x3ff00000);
	9533	+ writel(value, vop2->acm_regs + RK3528_ACM_DELTA_RANGE);
	9534	+
	9535	+ lut_y = &acm->gain_lut_hy[0];
	9536	+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
	9537	+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
	9538	+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
	9539	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	9540	+ ((lut_s[i] << 16) & 0xff0000);
	9541	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
	9542	+ }
	9543	+
	9544	+ lut_y = &acm->gain_lut_hs[0];
	9545	+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
	9546	+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
	9547	+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
	9548	+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
	9549	+ ((lut_s[i] << 16) & 0xff0000);
	9550	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
	9551	+ }
	9552	+
	9553	+ lut_y = &acm->delta_lut_h[0];
	9554	+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
	9555	+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
	9556	+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
	9557	+ value = (lut_y[i] & 0x3ff) + ((lut_h[i] << 12) & 0xff000) +
	9558	+ ((lut_s[i] << 20) & 0x3ff00000);
	9559	+ writel(value, vop2->acm_regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
	9560	+ }
	9561	+
	9562	+ writel(1, vop2->acm_regs + RK3528_ACM_FETCH_DONE);
	9563	+}
	9564	+
	9565	+static void vop3_post_config(struct drm_crtc *crtc)
	9566	+{
	9567	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9568	+ struct post_acm *acm;
	9569	+ struct post_csc *csc;
	9570	+
	9571	+ acm = vcstate->acm_lut_data ? (struct post_acm *)vcstate->acm_lut_data->data : NULL;
	9572	+ vop3_post_acm_config(crtc, acm);
	9573	+
	9574	+ csc = vcstate->post_csc_data ? (struct post_csc *)vcstate->post_csc_data->data : NULL;
	9575	+ vop3_post_csc_config(crtc, acm, csc);
6125	9576	}
6126	9577
6127	9578	static void vop2_cfg_update(struct drm_crtc *crtc,
..	..	@@ -6130,10 +9581,26 @@
6130	9581	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6131	9582	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6132	9583	struct vop2 *vop2 = vp->vop2;
	9584	+ const struct vop2_data *vop2_data = vop2->data;
	9585	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	9586	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
6133	9587	uint32_t val;
6134	9588	uint32_t r, g, b;
	9589	+ uint8_t out_mode;
6135	9590
6136	9591	spin_lock(&vop2->reg_lock);
	9592	+
	9593	+ if ((vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
	9594	+ !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT)) \|\|
	9595	+ vcstate->output_if & VOP_OUTPUT_IF_BT656)
	9596	+ out_mode = ROCKCHIP_OUT_MODE_P888;
	9597	+ else
	9598	+ out_mode = vcstate->output_mode;
	9599	+ VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
	9600	+
	9601	+ vop2_post_color_swap(crtc);
	9602	+
	9603	+ vop2_dither_setup(crtc);
6137	9604
6138	9605	VOP_MODULE_SET(vop2, vp, overlay_mode, vcstate->yuv_overlay);
6139	9606
..	..	@@ -6156,12 +9623,86 @@
6156	9623	}
6157	9624
6158	9625	VOP_MODULE_SET(vop2, vp, dsp_background, val);
	9626	+ if (vcstate->splice_mode) {
	9627	+ VOP_MODULE_SET(vop2, splice_vp, overlay_mode, vcstate->yuv_overlay);
	9628	+ VOP_MODULE_SET(vop2, splice_vp, dsp_background, val);
	9629	+ }
6159	9630
6160	9631	vop2_tv_config_update(crtc, old_crtc_state);
6161	9632
6162		- vop2_post_config(crtc);
	9633	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	9634	+ vop2_post_config(crtc);
	9635	+
	9636	+ if (vp_data->feature & (VOP_FEATURE_POST_ACM \| VOP_FEATURE_POST_CSC))
	9637	+ vop3_post_config(crtc);
6163	9638
6164	9639	spin_unlock(&vop2->reg_lock);
	9640	+}
	9641	+
	9642	+static void vop2_sleep_scan_line_time(struct vop2_video_port *vp, int scan_line)
	9643	+{
	9644	+ struct vop2 *vop2 = vp->vop2;
	9645	+ struct drm_display_mode *mode = &vp->rockchip_crtc.crtc.state->adjusted_mode;
	9646	+
	9647	+ if (scan_line <= 0)
	9648	+ return;
	9649	+
	9650	+ if (IS_ENABLED(CONFIG_HIGH_RES_TIMERS) &&
	9651	+ (!IS_ENABLED(CONFIG_NO_GKI) \|\| (hrtimer_resolution != LOW_RES_NSEC))) {
	9652	+ u16 htotal = VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16;
	9653	+ u32 linedur_ns = div_u64((u64) htotal * 1000000, mode->crtc_clock);
	9654	+ u64 sleep_time = linedur_ns * scan_line;
	9655	+
	9656	+ sleep_time = div_u64((sleep_time + 1000), 1000);
	9657	+ if (sleep_time > 200)
	9658	+ usleep_range(sleep_time, sleep_time);
	9659	+ }
	9660	+}
	9661	+
	9662	+/*
	9663	+ * return scan timing from FS to the assigned wait line
	9664	+ */
	9665	+static void vop2_wait_for_scan_timing_max_to_assigned_line(struct vop2_video_port *vp,
	9666	+ u32 current_line,
	9667	+ u32 wait_line)
	9668	+
	9669	+{
	9670	+ struct vop2 *vop2 = vp->vop2;
	9671	+ u32 vcnt;
	9672	+ int ret;
	9673	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	9674	+ int delta_line = vtotal - current_line;
	9675	+
	9676	+ vop2_sleep_scan_line_time(vp, delta_line);
	9677	+ if (vop2_read_vcnt(vp) < wait_line)
	9678	+ return;
	9679	+
	9680	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt < wait_line, 0, 50 * 1000);
	9681	+ if (ret)
	9682	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from FS to the assigned wait line: %d, vcnt:%d, ret:%d\n",
	9683	+ wait_line, vcnt, ret);
	9684	+}
	9685	+
	9686	+/*
	9687	+ * return scan timing from the assigned wait line
	9688	+ */
	9689	+static void vop2_wait_for_scan_timing_from_the_assigned_line(struct vop2_video_port *vp,
	9690	+ u32 current_line,
	9691	+ u32 wait_line)
	9692	+{
	9693	+ struct vop2 *vop2 = vp->vop2;
	9694	+ u32 vcnt;
	9695	+ int ret;
	9696	+ int delta_line = wait_line - current_line;
	9697	+
	9698	+ vop2_sleep_scan_line_time(vp, delta_line);
	9699	+ if (vop2_read_vcnt(vp) > wait_line)
	9700	+ return;
	9701	+
	9702	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt > wait_line, 0, 50 * 1000);
	9703	+ if (ret)
	9704	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from the assigned wait line: %d, vcnt:%d, ret:%d\n",
	9705	+ wait_line, vcnt, ret);
6165	9706	}
6166	9707
6167	9708	static void vop2_crtc_atomic_flush(struct drm_crtc crtc, struct drm_crtc_state old_cstate)
..	..	@@ -6169,11 +9710,26 @@
6169	9710	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6170	9711	struct drm_atomic_state *old_state = old_cstate->state;
6171	9712	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6172		- struct drm_plane_state *old_pstate;
6173	9713	struct vop2 *vop2 = vp->vop2;
	9714	+ struct drm_plane_state *old_pstate;
6174	9715	struct drm_plane *plane;
6175	9716	unsigned long flags;
6176	9717	int i, ret;
	9718	+ struct vop2_wb *wb = &vop2->wb;
	9719	+ struct drm_writeback_connector *wb_conn = &wb->conn;
	9720	+ struct drm_connector_state *conn_state = wb_conn->base.state;
	9721	+
	9722	+ if (conn_state && conn_state->writeback_job && conn_state->writeback_job->fb) {
	9723	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	9724	+ u32 current_line = vop2_read_vcnt(vp);
	9725	+
	9726	+ if (current_line > vtotal * 7 >> 3)
	9727	+ vop2_wait_for_scan_timing_max_to_assigned_line(vp, current_line, vtotal * 7 >> 3);
	9728	+
	9729	+ current_line = vop2_read_vcnt(vp);
	9730	+ if (current_line < vtotal >> 3)
	9731	+ vop2_wait_for_scan_timing_from_the_assigned_line(vp, current_line, vtotal >> 3);
	9732	+ }
6177	9733
6178	9734	vop2_cfg_update(crtc, old_cstate);
6179	9735
..	..	@@ -6199,12 +9755,13 @@
6199	9755	vp->gamma_lut = crtc->state->gamma_lut->data;
6200	9756	vop2_crtc_atomic_gamma_set(crtc, crtc->state);
6201	9757	}
6202		-
	9758	+#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
6203	9759	if (crtc->state->cubic_lut \|\| vp->cubic_lut) {
6204	9760	if (crtc->state->cubic_lut)
6205	9761	vp->cubic_lut = crtc->state->cubic_lut->data;
6206	9762	vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state);
6207	9763	}
	9764	+#endif
6208	9765	} else {
6209	9766	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
6210	9767	}
..	..	@@ -6217,6 +9774,9 @@
6217	9774	spin_lock_irqsave(&vop2->irq_lock, flags);
6218	9775	vop2_wb_commit(crtc);
6219	9776	vop2_cfg_done(crtc);
	9777	+
	9778	+ if (vp->mcu_timing.mcu_pix_total)
	9779	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 0);
6220	9780
6221	9781	spin_unlock_irqrestore(&vop2->irq_lock, flags);
6222	9782
..	..	@@ -6258,6 +9818,7 @@
6258	9818	}
6259	9819
6260	9820	static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
	9821	+ .mode_valid = vop2_crtc_mode_valid,
6261	9822	.mode_fixup = vop2_crtc_mode_fixup,
6262	9823	.atomic_check = vop2_crtc_atomic_check,
6263	9824	.atomic_begin = vop2_crtc_atomic_begin,
..	..	@@ -6298,12 +9859,22 @@
6298	9859	struct rockchip_crtc_state vcstate, old_vcstate;
6299	9860	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6300	9861
	9862	+ if (WARN_ON(!crtc->state))
	9863	+ return NULL;
	9864	+
6301	9865	old_vcstate = to_rockchip_crtc_state(crtc->state);
6302	9866	vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL);
6303	9867	if (!vcstate)
6304	9868	return NULL;
6305	9869
6306	9870	vcstate->vp_id = vp->id;
	9871	+ if (vcstate->hdr_ext_data)
	9872	+ drm_property_blob_get(vcstate->hdr_ext_data);
	9873	+ if (vcstate->acm_lut_data)
	9874	+ drm_property_blob_get(vcstate->acm_lut_data);
	9875	+ if (vcstate->post_csc_data)
	9876	+ drm_property_blob_get(vcstate->post_csc_data);
	9877	+
6307	9878	__drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
6308	9879	return &vcstate->base;
6309	9880	}
..	..	@@ -6314,6 +9885,9 @@
6314	9885	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
6315	9886
6316	9887	__drm_atomic_helper_crtc_destroy_state(&vcstate->base);
	9888	+ drm_property_blob_put(vcstate->hdr_ext_data);
	9889	+ drm_property_blob_put(vcstate->acm_lut_data);
	9890	+ drm_property_blob_put(vcstate->post_csc_data);
6317	9891	kfree(vcstate);
6318	9892	}
6319	9893
..	..	@@ -6414,25 +9988,49 @@
6414	9988	return 0;
6415	9989	}
6416	9990
6417		- if (property == private->alpha_scale_prop) {
6418		- *val = (vop2->data->feature & VOP_FEATURE_ALPHA_SCALE) ? 1 : 0;
6419		- return 0;
6420		- }
6421		-
6422		- if (property == vop2->aclk_prop) {
	9991	+ if (property == private->aclk_prop) {
6423	9992	/* KHZ, keep align with mode->clock */
6424	9993	*val = clk_get_rate(vop2->aclk) / 1000;
6425	9994	return 0;
6426	9995	}
6427	9996
6428		-
6429		- if (property == vop2->bg_prop) {
	9997	+ if (property == private->bg_prop) {
6430	9998	*val = vcstate->background;
6431	9999	return 0;
6432	10000	}
6433	10001
6434		- if (property == vop2->line_flag_prop) {
	10002	+ if (property == private->line_flag_prop) {
6435	10003	*val = vcstate->line_flag;
	10004	+ return 0;
	10005	+ }
	10006	+
	10007	+ if (property == vp->variable_refresh_rate_prop) {
	10008	+ *val = vcstate->request_refresh_rate;
	10009	+ return 0;
	10010	+ }
	10011	+
	10012	+ if (property == vp->max_refresh_rate_prop) {
	10013	+ *val = vcstate->max_refresh_rate;
	10014	+ return 0;
	10015	+ }
	10016	+
	10017	+ if (property == vp->min_refresh_rate_prop) {
	10018	+ *val = vcstate->min_refresh_rate;
	10019	+ return 0;
	10020	+ }
	10021	+
	10022	+ if (property == vp->hdr_ext_data_prop) {
	10023	+ *val = vcstate->hdr_ext_data ? vcstate->hdr_ext_data->base.id : 0;
	10024	+ return 0;
	10025	+ }
	10026	+
	10027	+ if (property == vp->acm_lut_data_prop) {
	10028	+ *val = vcstate->acm_lut_data ? vcstate->acm_lut_data->base.id : 0;
	10029	+ return 0;
	10030	+ }
	10031	+
	10032	+ if (property == vp->post_csc_data_prop) {
	10033	+ *val = vcstate->post_csc_data ? vcstate->post_csc_data->base.id : 0;
6436	10034	return 0;
6437	10035	}
6438	10036
..	..	@@ -6441,16 +10039,52 @@
6441	10039	return -EINVAL;
6442	10040	}
6443	10041
	10042	+/* copied from drm_atomic.c */
	10043	+static int
	10044	+vop2_atomic_replace_property_blob_from_id(struct drm_device *dev,
	10045	+ struct drm_property_blob **blob,
	10046	+ uint64_t blob_id,
	10047	+ ssize_t expected_size,
	10048	+ ssize_t expected_elem_size,
	10049	+ bool *replaced)
	10050	+{
	10051	+ struct drm_property_blob *new_blob = NULL;
	10052	+
	10053	+ if (blob_id != 0) {
	10054	+ new_blob = drm_property_lookup_blob(dev, blob_id);
	10055	+ if (new_blob == NULL)
	10056	+ return -EINVAL;
	10057	+
	10058	+ if (expected_size > 0 &&
	10059	+ new_blob->length != expected_size) {
	10060	+ drm_property_blob_put(new_blob);
	10061	+ return -EINVAL;
	10062	+ }
	10063	+ if (expected_elem_size > 0 &&
	10064	+ new_blob->length % expected_elem_size != 0) {
	10065	+ drm_property_blob_put(new_blob);
	10066	+ return -EINVAL;
	10067	+ }
	10068	+ }
	10069	+
	10070	+ *replaced \|= drm_property_replace_blob(blob, new_blob);
	10071	+ drm_property_blob_put(new_blob);
	10072	+
	10073	+ return 0;
	10074	+}
	10075	+
6444	10076	static int vop2_crtc_atomic_set_property(struct drm_crtc *crtc,
6445	10077	struct drm_crtc_state *state,
6446	10078	struct drm_property *property,
6447	10079	uint64_t val)
6448	10080	{
6449	10081	struct drm_device *drm_dev = crtc->dev;
	10082	+ struct rockchip_drm_private *private = drm_dev->dev_private;
6450	10083	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
6451	10084	struct drm_mode_config *mode_config = &drm_dev->mode_config;
6452	10085	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6453		- struct vop2 *vop2 = vp->vop2;
	10086	+ bool replaced = false;
	10087	+ int ret;
6454	10088
6455	10089	if (property == mode_config->tv_left_margin_property) {
6456	10090	vcstate->left_margin = val;
..	..	@@ -6473,14 +10107,56 @@
6473	10107	}
6474	10108
6475	10109
6476		- if (property == vop2->bg_prop) {
	10110	+ if (property == private->bg_prop) {
6477	10111	vcstate->background = val;
6478	10112	return 0;
6479	10113	}
6480	10114
6481		- if (property == vop2->line_flag_prop) {
	10115	+ if (property == private->line_flag_prop) {
6482	10116	vcstate->line_flag = val;
6483	10117	return 0;
	10118	+ }
	10119	+
	10120	+ if (property == vp->variable_refresh_rate_prop) {
	10121	+ vcstate->request_refresh_rate = val;
	10122	+ return 0;
	10123	+ }
	10124	+
	10125	+ if (property == vp->max_refresh_rate_prop) {
	10126	+ vcstate->max_refresh_rate = val;
	10127	+ return 0;
	10128	+ }
	10129	+
	10130	+ if (property == vp->min_refresh_rate_prop) {
	10131	+ vcstate->min_refresh_rate = val;
	10132	+ return 0;
	10133	+ }
	10134	+
	10135	+ if (property == vp->hdr_ext_data_prop) {
	10136	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10137	+ &vcstate->hdr_ext_data,
	10138	+ val,
	10139	+ -1, -1,
	10140	+ &replaced);
	10141	+ return ret;
	10142	+ }
	10143	+
	10144	+ if (property == vp->acm_lut_data_prop) {
	10145	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10146	+ &vcstate->acm_lut_data,
	10147	+ val,
	10148	+ sizeof(struct post_acm), -1,
	10149	+ &replaced);
	10150	+ return ret;
	10151	+ }
	10152	+
	10153	+ if (property == vp->post_csc_data_prop) {
	10154	+ ret = vop2_atomic_replace_property_blob_from_id(drm_dev,
	10155	+ &vcstate->post_csc_data,
	10156	+ val,
	10157	+ sizeof(struct post_csc), -1,
	10158	+ &replaced);
	10159	+ return ret;
6484	10160	}
6485	10161
6486	10162	DRM_ERROR("failed to set vop2 crtc property %s\n", property->name);
..	..	@@ -6509,7 +10185,7 @@
6509	10185	struct vop2_video_port *vp = container_of(work, struct vop2_video_port, fb_unref_work);
6510	10186	struct drm_framebuffer *fb = val;
6511	10187
6512		- drm_crtc_vblank_put(&vp->crtc);
	10188	+ drm_crtc_vblank_put(&vp->rockchip_crtc.crtc);
6513	10189	if (!vp->vop2->skip_ref_fb)
6514	10190	drm_framebuffer_put(fb);
6515	10191	}
..	..	@@ -6580,6 +10256,7 @@
6580	10256	struct vop2_wb *wb = &vop2->wb;
6581	10257
6582	10258	VOP_MODULE_SET(vop2, wb, enable, 0);
	10259	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 0);
6583	10260	vop2_wb_cfg_done(vp);
6584	10261	}
6585	10262
..	..	@@ -6618,6 +10295,43 @@
6618	10295	}
6619	10296	}
6620	10297	spin_unlock_irqrestore(&wb->job_lock, flags);
	10298	+}
	10299	+
	10300	+static void vop2_dsc_isr(struct vop2 *vop2)
	10301	+{
	10302	+ const struct vop2_data *vop2_data = vop2->data;
	10303	+ struct vop2_dsc *dsc;
	10304	+ const struct dsc_error_info *dsc_error_ecw = vop2_data->dsc_error_ecw;
	10305	+ const struct dsc_error_info *dsc_error_buffer_flow = vop2_data->dsc_error_buffer_flow;
	10306	+ u32 dsc_error_status = 0, dsc_ecw = 0;
	10307	+ int i = 0, j = 0;
	10308	+
	10309	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	10310	+ dsc = &vop2->dscs[i];
	10311	+
	10312	+ if (!dsc->enabled)
	10313	+ continue;
	10314	+
	10315	+ dsc_error_status = VOP_MODULE_GET(vop2, dsc, dsc_error_status);
	10316	+ if (!dsc_error_status)
	10317	+ continue;
	10318	+ dsc_ecw = VOP_MODULE_GET(vop2, dsc, dsc_ecw);
	10319	+
	10320	+ for (j = 0; j < vop2_data->nr_dsc_ecw; j++) {
	10321	+ if (dsc_ecw == dsc_error_ecw[j].dsc_error_val) {
	10322	+ DRM_ERROR("dsc%d %s\n", dsc->id, dsc_error_ecw[j].dsc_error_info);
	10323	+ break;
	10324	+ }
	10325	+ }
	10326	+
	10327	+ if (dsc_ecw == 0x0120ffff) {
	10328	+ u32 offset = dsc->regs->dsc_status.offset;
	10329	+
	10330	+ for (j = 0; j < vop2_data->nr_dsc_buffer_flow; j++)
	10331	+ DRM_ERROR("dsc%d %s:0x%x\n", dsc->id, dsc_error_buffer_flow[j].dsc_error_info,
	10332	+ vop2_readl(vop2, offset + (j << 2)));
	10333	+ }
	10334	+ }
6621	10335	}
6622	10336
6623	10337	static irqreturn_t vop2_isr(int irq, void *data)
..	..	@@ -6674,7 +10388,7 @@
6674	10388
6675	10389	for (i = 0; i < vp_max; i++) {
6676	10390	vp = &vop2->vps[i];
6677		- crtc = &vp->crtc;
	10391	+ crtc = &vp->rockchip_crtc.crtc;
6678	10392	active_irqs = vp_irqs[i];
6679	10393	if (active_irqs & DSP_HOLD_VALID_INTR) {
6680	10394	complete(&vp->dsp_hold_completion);
..	..	@@ -6694,7 +10408,18 @@
6694	10408	ret = IRQ_HANDLED;
6695	10409	}
6696	10410
	10411	+ if (vop2->version == VOP_VERSION_RK3528 && vp->id == 1) {
	10412	+ if (active_irqs & POST_BUF_EMPTY_INTR)
	10413	+ atomic_inc(&vp->post_buf_empty_flag);
	10414	+
	10415	+ if (active_irqs & FS_FIELD_INTR &&
	10416	+ (atomic_read(&vp->post_buf_empty_flag) > 0 \|\|
	10417	+ vp->need_reset_p2i_flag == true))
	10418	+ queue_work(vop2->workqueue, &vop2->post_buf_empty_work);
	10419	+ }
	10420	+
6697	10421	if (active_irqs & FS_FIELD_INTR) {
	10422	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_VSYNC, "vsync_vp%d\n", vp->id);
6698	10423	vop2_wb_handler(vp);
6699	10424	if (likely(!vp->skip_vsync) \|\| (vp->layer_sel_update == false)) {
6700	10425	drm_crtc_handle_vblank(crtc);
..	..	@@ -6726,6 +10451,9 @@
6726	10451	if (active_irqs)
6727	10452	DRM_ERROR("Unknown axi_bus%d IRQs: %02x\n", i, active_irqs);
6728	10453	}
	10454	+
	10455	+ if (vop2->data->nr_dscs)
	10456	+ vop2_dsc_isr(vop2);
6729	10457
6730	10458	vop2_core_clks_disable(vop2);
6731	10459	out:
..	..	@@ -6784,6 +10512,51 @@
6784	10512	return 0;
6785	10513	}
6786	10514
	10515	+static bool vop3_ignore_plane(struct vop2 vop2, struct vop2_win win)
	10516	+{
	10517	+ if (!is_vop3(vop2))
	10518	+ return false;
	10519	+
	10520	+ if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE &&
	10521	+ win->phys_id != ROCKCHIP_VOP2_ESMART0)
	10522	+ return true;
	10523	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE &&
	10524	+ (win->phys_id == ROCKCHIP_VOP2_ESMART1 \|\| win->phys_id == ROCKCHIP_VOP2_ESMART3))
	10525	+ return true;
	10526	+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE &&
	10527	+ win->phys_id == ROCKCHIP_VOP2_ESMART1)
	10528	+ return true;
	10529	+ else
	10530	+ return false;
	10531	+}
	10532	+
	10533	+static u32 vop3_esmart_linebuffer_size(struct vop2 vop2, struct vop2_win win)
	10534	+{
	10535	+ if (!is_vop3(vop2) \|\| vop2_cluster_window(win))
	10536	+ return vop2->data->max_output.width;
	10537	+
	10538	+ if (vop2->esmart_lb_mode == VOP3_ESMART_2K_2K_2K_2K_MODE \|\|
	10539	+ (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE && win->phys_id != ROCKCHIP_VOP2_ESMART0))
	10540	+ return vop2->data->max_output.width / 2;
	10541	+ else
	10542	+ return vop2->data->max_output.width;
	10543	+}
	10544	+
	10545	+static void vop3_init_esmart_scale_engine(struct vop2 *vop2)
	10546	+{
	10547	+ u8 scale_engine_num = 0;
	10548	+ struct drm_plane *plane = NULL;
	10549	+
	10550	+ drm_for_each_plane(plane, vop2->drm_dev) {
	10551	+ struct vop2_win *win = to_vop2_win(plane);
	10552	+
	10553	+ if (win->parent \|\| vop2_cluster_window(win))
	10554	+ continue;
	10555	+
	10556	+ win->scale_engine_num = scale_engine_num++;
	10557	+ }
	10558	+}
	10559	+
6787	10560	static int vop2_plane_init(struct vop2 vop2, struct vop2_win win, unsigned long possible_crtcs)
6788	10561	{
6789	10562	struct rockchip_drm_private *private = vop2->drm_dev->dev_private;
..	..	@@ -6807,6 +10580,10 @@
6807	10580	if (win->feature & WIN_FEATURE_CLUSTER_SUB)
6808	10581	return -EACCES;
6809	10582	}
	10583	+
	10584	+ /* ignore some plane register according vop3 esmart lb mode */
	10585	+ if (vop3_ignore_plane(vop2, win))
	10586	+ return -EACCES;
6810	10587
6811	10588	ret = drm_universal_plane_init(vop2->drm_dev, &win->base, possible_crtcs,
6812	10589	&vop2_plane_funcs, win->formats, win->nformats,
..	..	@@ -6847,7 +10624,7 @@
6847	10624	"INPUT_WIDTH", 0, max_width);
6848	10625	win->input_height_prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE,
6849	10626	"INPUT_HEIGHT", 0, max_height);
6850		- max_width = vop2->data->max_output.width;
	10627	+ max_width = vop3_esmart_linebuffer_size(vop2, win);
6851	10628	max_height = vop2->data->max_output.height;
6852	10629	if (win->feature & WIN_FEATURE_CLUSTER_SUB)
6853	10630	max_width >>= 1;
..	..	@@ -6883,15 +10660,27 @@
6883	10660	return 0;
6884	10661	}
6885	10662
6886		-static struct drm_plane vop2_cursor_plane_init(struct vop2_video_port vp,
6887		- unsigned long possible_crtcs)
	10663	+static struct drm_plane vop2_cursor_plane_init(struct vop2_video_port vp)
6888	10664	{
6889	10665	struct vop2 *vop2 = vp->vop2;
6890	10666	struct drm_plane *cursor = NULL;
6891	10667	struct vop2_win *win;
	10668	+ unsigned long possible_crtcs = 0;
6892	10669
6893	10670	win = vop2_find_win_by_phys_id(vop2, vp->cursor_win_id);
6894	10671	if (win) {
	10672	+ if (vop2->disable_win_move) {
	10673	+ const struct vop2_data *vop2_data = vop2->data;
	10674	+ struct drm_crtc *crtc = vop2_find_crtc_by_plane_mask(vop2, win->phys_id);
	10675	+
	10676	+ if (crtc)
	10677	+ possible_crtcs = drm_crtc_mask(crtc);
	10678	+ else
	10679	+ possible_crtcs = (1 << vop2_data->nr_vps) - 1;
	10680	+ }
	10681	+
	10682	+ if (win->possible_crtcs)
	10683	+ possible_crtcs = win->possible_crtcs;
6895	10684	win->type = DRM_PLANE_TYPE_CURSOR;
6896	10685	win->zpos = vop2->registered_num_wins - 1;
6897	10686	if (!vop2_plane_init(vop2, win, possible_crtcs))
..	..	@@ -6917,7 +10706,7 @@
6917	10706
6918	10707	for (i = 0; i < vop2_data->nr_vps; i++) {
6919	10708	vp = &vop2->vps[i];
6920		- crtc = &vp->crtc;
	10709	+ crtc = &vp->rockchip_crtc.crtc;
6921	10710	if (!crtc->dev)
6922	10711	continue;
6923	10712	vp_data = &vop2_data->vp[vp->id];
..	..	@@ -6925,6 +10714,7 @@
6925	10714	if (!lut_len)
6926	10715	continue;
6927	10716	vp->gamma_lut_len = vp_data->gamma_lut_len;
	10717	+ vp->lut_dma_rid = vp_data->lut_dma_rid;
6928	10718	vp->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vp->lut),
6929	10719	GFP_KERNEL);
6930	10720	if (!vp->lut)
..	..	@@ -6951,27 +10741,6 @@
6951	10741	}
6952	10742
6953	10743	return 0;
6954		-}
6955		-
6956		-static void vop2_cubic_lut_init(struct vop2 *vop2)
6957		-{
6958		- const struct vop2_data *vop2_data = vop2->data;
6959		- const struct vop2_video_port_data *vp_data;
6960		- struct vop2_video_port *vp;
6961		- struct drm_crtc *crtc;
6962		- int i;
6963		-
6964		- for (i = 0; i < vop2_data->nr_vps; i++) {
6965		- vp = &vop2->vps[i];
6966		- crtc = &vp->crtc;
6967		- if (!crtc->dev)
6968		- continue;
6969		- vp_data = &vop2_data->vp[vp->id];
6970		- vp->cubic_lut_len = vp_data->cubic_lut_len;
6971		-
6972		- if (vp->cubic_lut_len)
6973		- drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
6974		- }
6975	10744	}
6976	10745
6977	10746	static int vop2_crtc_create_plane_mask_property(struct vop2 *vop2,
..	..	@@ -7009,6 +10778,139 @@
7009	10778	return 0;
7010	10779	}
7011	10780
	10781	+static int vop2_crtc_create_feature_property(struct vop2 vop2, struct drm_crtc crtc)
	10782	+{
	10783	+ const struct vop2_data *vop2_data = vop2->data;
	10784	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	10785	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	10786	+ struct drm_property *prop;
	10787	+ u64 feature = 0;
	10788	+
	10789	+ static const struct drm_prop_enum_list props[] = {
	10790	+ { ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE, "ALPHA_SCALE" },
	10791	+ { ROCKCHIP_DRM_CRTC_FEATURE_HDR10, "HDR10" },
	10792	+ { ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR, "NEXT_HDR" },
	10793	+ };
	10794	+
	10795	+ if (vp_data->feature & VOP_FEATURE_ALPHA_SCALE)
	10796	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE);
	10797	+ if (vp_data->feature & VOP_FEATURE_HDR10)
	10798	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_HDR10);
	10799	+ if (vp_data->feature & VOP_FEATURE_NEXT_HDR)
	10800	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR);
	10801	+
	10802	+ prop = drm_property_create_bitmask(vop2->drm_dev,
	10803	+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
	10804	+ props, ARRAY_SIZE(props),
	10805	+ 0xffffffff);
	10806	+ if (!prop) {
	10807	+ DRM_DEV_ERROR(vop2->dev, "create FEATURE prop for vp%d failed\n", vp->id);
	10808	+ return -ENOMEM;
	10809	+ }
	10810	+
	10811	+ vp->feature_prop = prop;
	10812	+ drm_object_attach_property(&crtc->base, vp->feature_prop, feature);
	10813	+
	10814	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_WIDTH",
	10815	+ 0, vop2->data->vp[vp->id].max_output.width);
	10816	+ if (!prop) {
	10817	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_WIDTH prop for vp%d failed\n", vp->id);
	10818	+ return -ENOMEM;
	10819	+ }
	10820	+ vp->output_width_prop = prop;
	10821	+ drm_object_attach_property(&crtc->base, vp->output_width_prop, 0);
	10822	+
	10823	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_DCLK",
	10824	+ 0, rockchip_drm_get_dclk_by_width(vop2->data->vp[vp->id].max_output.width) * 1000);
	10825	+ if (!prop) {
	10826	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_DCLK prop for vp%d failed\n", vp->id);
	10827	+ return -ENOMEM;
	10828	+ }
	10829	+ vp->output_dclk_prop = prop;
	10830	+ drm_object_attach_property(&crtc->base, vp->output_dclk_prop, 0);
	10831	+
	10832	+ return 0;
	10833	+}
	10834	+
	10835	+static int vop2_crtc_create_vrr_property(struct vop2 vop2, struct drm_crtc crtc)
	10836	+{
	10837	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	10838	+ struct drm_property *prop;
	10839	+
	10840	+ prop = drm_property_create_range(vop2->drm_dev, 0, "variable refresh rate", 0, 144);
	10841	+ if (!prop) {
	10842	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	10843	+ return -ENOMEM;
	10844	+ }
	10845	+ vp->variable_refresh_rate_prop = prop;
	10846	+ drm_object_attach_property(&crtc->base, vp->variable_refresh_rate_prop, 0);
	10847	+
	10848	+ prop = drm_property_create_range(vop2->drm_dev, 0, "max refresh rate", 0, 144);
	10849	+ if (!prop) {
	10850	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	10851	+ return -ENOMEM;
	10852	+ }
	10853	+ vp->max_refresh_rate_prop = prop;
	10854	+ drm_object_attach_property(&crtc->base, vp->max_refresh_rate_prop, 0);
	10855	+
	10856	+ prop = drm_property_create_range(vop2->drm_dev, 0, "min refresh rate", 0, 144);
	10857	+ if (!prop) {
	10858	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	10859	+ return -ENOMEM;
	10860	+ }
	10861	+ vp->min_refresh_rate_prop = prop;
	10862	+ drm_object_attach_property(&crtc->base, vp->min_refresh_rate_prop, 0);
	10863	+
	10864	+ return 0;
	10865	+}
	10866	+
	10867	+static int vop2_crtc_create_hdr_property(struct vop2 vop2, struct drm_crtc crtc)
	10868	+{
	10869	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	10870	+ struct drm_property *prop;
	10871	+
	10872	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "HDR_EXT_DATA", 0);
	10873	+ if (!prop) {
	10874	+ DRM_DEV_ERROR(vop2->dev, "create hdr ext data prop for vp%d failed\n", vp->id);
	10875	+ return -ENOMEM;
	10876	+ }
	10877	+ vp->hdr_ext_data_prop = prop;
	10878	+ drm_object_attach_property(&crtc->base, vp->hdr_ext_data_prop, 0);
	10879	+
	10880	+ return 0;
	10881	+}
	10882	+
	10883	+static int vop2_crtc_create_post_acm_property(struct vop2 vop2, struct drm_crtc crtc)
	10884	+{
	10885	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	10886	+ struct drm_property *prop;
	10887	+
	10888	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "ACM_LUT_DATA", 0);
	10889	+ if (!prop) {
	10890	+ DRM_DEV_ERROR(vop2->dev, "create acm lut data prop for vp%d failed\n", vp->id);
	10891	+ return -ENOMEM;
	10892	+ }
	10893	+ vp->acm_lut_data_prop = prop;
	10894	+ drm_object_attach_property(&crtc->base, vp->acm_lut_data_prop, 0);
	10895	+
	10896	+ return 0;
	10897	+}
	10898	+
	10899	+static int vop2_crtc_create_post_csc_property(struct vop2 vop2, struct drm_crtc crtc)
	10900	+{
	10901	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	10902	+ struct drm_property *prop;
	10903	+
	10904	+ prop = drm_property_create(vop2->drm_dev, DRM_MODE_PROP_BLOB, "POST_CSC_DATA", 0);
	10905	+ if (!prop) {
	10906	+ DRM_DEV_ERROR(vop2->dev, "create post csc data prop for vp%d failed\n", vp->id);
	10907	+ return -ENOMEM;
	10908	+ }
	10909	+ vp->post_csc_data_prop = prop;
	10910	+ drm_object_attach_property(&crtc->base, vp->post_csc_data_prop, 0);
	10911	+
	10912	+ return 0;
	10913	+}
7012	10914	#define RK3566_MIRROR_PLANE_MASK (BIT(ROCKCHIP_VOP2_CLUSTER1) \| BIT(ROCKCHIP_VOP2_ESMART1) \| \
7013	10915	BIT(ROCKCHIP_VOP2_SMART1))
7014	10916
..	..	@@ -7021,7 +10923,7 @@
7021	10923	const struct vop2_data *vop2_data = vop2->data;
7022	10924	struct drm_device *drm_dev = vop2->drm_dev;
7023	10925	struct device *dev = vop2->dev;
7024		- struct drm_plane *plane;
	10926	+ struct drm_plane *primary;
7025	10927	struct drm_plane *cursor = NULL;
7026	10928	struct drm_crtc *crtc;
7027	10929	struct device_node *port;
..	..	@@ -7032,12 +10934,13 @@
7032	10934	uint64_t soc_id;
7033	10935	uint32_t registered_num_crtcs = 0;
7034	10936	uint32_t plane_mask = 0;
7035		- char dclk_name[9];
	10937	+ char clk_name[16];
7036	10938	int i = 0, j = 0, k = 0;
7037	10939	int ret = 0;
7038	10940	bool be_used_for_primary_plane = false;
7039	10941	bool find_primary_plane = false;
7040	10942	bool bootloader_initialized = false;
	10943	+ struct rockchip_drm_private *private = drm_dev->dev_private;
7041	10944
7042	10945	/* all planes can attach to any crtc */
7043	10946	possible_crtcs = (1 << vop2_data->nr_vps) - 1;
..	..	@@ -7069,6 +10972,9 @@
7069	10972	vp->id = vp_data->id;
7070	10973	vp->regs = vp_data->regs;
7071	10974	vp->cursor_win_id = -1;
	10975	+ primary = NULL;
	10976	+ cursor = NULL;
	10977	+
7072	10978	if (vop2->disable_win_move)
7073	10979	possible_crtcs = BIT(registered_num_crtcs);
7074	10980
..	..	@@ -7084,14 +10990,27 @@
7084	10990	else
7085	10991	soc_id = vp_data->soc_id[0];
7086	10992
7087		- snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
7088		- vp->dclk = devm_clk_get(vop2->dev, dclk_name);
	10993	+ snprintf(clk_name, sizeof(clk_name), "dclk_vp%d", vp->id);
	10994	+ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, clk_name);
	10995	+ if (IS_ERR(vp->dclk_rst)) {
	10996	+ DRM_DEV_ERROR(vop2->dev, "failed to get dclk reset\n");
	10997	+ return PTR_ERR(vp->dclk_rst);
	10998	+ }
	10999	+
	11000	+ vp->dclk = devm_clk_get(vop2->dev, clk_name);
7089	11001	if (IS_ERR(vp->dclk)) {
7090		- DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", dclk_name);
	11002	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
7091	11003	return PTR_ERR(vp->dclk);
7092	11004	}
7093	11005
7094		- crtc = &vp->crtc;
	11006	+ snprintf(clk_name, sizeof(clk_name), "dclk_src_vp%d", vp->id);
	11007	+ vp->dclk_parent = devm_clk_get_optional(vop2->dev, clk_name);
	11008	+ if (IS_ERR(vp->dclk)) {
	11009	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
	11010	+ return PTR_ERR(vp->dclk);
	11011	+ }
	11012	+
	11013	+ crtc = &vp->rockchip_crtc.crtc;
7095	11014
7096	11015	port = of_graph_get_port_by_id(dev->of_node, i);
7097	11016	if (!port) {
..	..	@@ -7116,6 +11035,7 @@
7116	11035	win->type = DRM_PLANE_TYPE_PRIMARY;
7117	11036	}
7118	11037	} else {
	11038	+ j = 0;
7119	11039	while (j < vop2->registered_num_wins) {
7120	11040	be_used_for_primary_plane = false;
7121	11041	win = &vop2->win[j];
..	..	@@ -7157,24 +11077,43 @@
7157	11077	DRM_DEV_ERROR(vop2->dev, "failed to init primary plane\n");
7158	11078	break;
7159	11079	}
7160		- plane = &win->base;
	11080	+ primary = &win->base;
7161	11081	}
7162	11082
7163	11083	/* some times we want a cursor window for some vp */
	11084	+ if (vp->cursor_win_id < 0) {
	11085	+ bool be_used_for_cursor_plane = false;
	11086	+
	11087	+ j = 0;
	11088	+ while (j < vop2->registered_num_wins) {
	11089	+ win = &vop2->win[j++];
	11090	+
	11091	+ if (win->parent \|\| (win->feature & WIN_FEATURE_CLUSTER_SUB))
	11092	+ continue;
	11093	+
	11094	+ if (win->type != DRM_PLANE_TYPE_CURSOR)
	11095	+ continue;
	11096	+
	11097	+ for (k = 0; k < vop2_data->nr_vps; k++) {
	11098	+ if (vop2->vps[k].cursor_win_id == win->phys_id)
	11099	+ be_used_for_cursor_plane = true;
	11100	+ }
	11101	+ if (be_used_for_cursor_plane)
	11102	+ continue;
	11103	+ vp->cursor_win_id = win->phys_id;
	11104	+ }
	11105	+ }
	11106	+
7164	11107	if (vp->cursor_win_id >= 0) {
7165		- if (win->possible_crtcs)
7166		- possible_crtcs = win->possible_crtcs;
7167		- cursor = vop2_cursor_plane_init(vp, possible_crtcs);
	11108	+ cursor = vop2_cursor_plane_init(vp);
7168	11109	if (!cursor)
7169	11110	DRM_WARN("failed to init cursor plane for vp%d\n", vp->id);
7170	11111	else
7171	11112	DRM_DEV_INFO(vop2->dev, "%s as cursor plane for vp%d\n",
7172	11113	cursor->name, vp->id);
7173		- } else {
7174		- cursor = NULL;
7175	11114	}
7176	11115
7177		- ret = drm_crtc_init_with_planes(drm_dev, crtc, plane, cursor, &vop2_crtc_funcs,
	11116	+ ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor, &vop2_crtc_funcs,
7178	11117	"video_port%d", vp->id);
7179	11118	if (ret) {
7180	11119	DRM_DEV_ERROR(vop2->dev, "crtc init for video_port%d failed\n", i);
..	..	@@ -7189,20 +11128,39 @@
7189	11128	init_completion(&vp->line_flag_completion);
7190	11129	rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
7191	11130	soc_id = vop2_soc_id_fixup(soc_id);
7192		- drm_object_attach_property(&crtc->base, vop2->soc_id_prop, soc_id);
7193		- drm_object_attach_property(&crtc->base, vop2->vp_id_prop, vp->id);
7194		- drm_object_attach_property(&crtc->base, vop2->aclk_prop, 0);
7195		- drm_object_attach_property(&crtc->base, vop2->bg_prop, 0);
7196		- drm_object_attach_property(&crtc->base, vop2->line_flag_prop, 0);
7197		- drm_object_attach_property(&crtc->base,
7198		- drm_dev->mode_config.tv_left_margin_property, 100);
7199		- drm_object_attach_property(&crtc->base,
7200		- drm_dev->mode_config.tv_right_margin_property, 100);
7201		- drm_object_attach_property(&crtc->base,
7202		- drm_dev->mode_config.tv_top_margin_property, 100);
7203		- drm_object_attach_property(&crtc->base,
7204		- drm_dev->mode_config.tv_bottom_margin_property, 100);
7205		- vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
	11131	+ drm_object_attach_property(&crtc->base, private->soc_id_prop, soc_id);
	11132	+ drm_object_attach_property(&crtc->base, private->port_id_prop, vp->id);
	11133	+ drm_object_attach_property(&crtc->base, private->aclk_prop, 0);
	11134	+ drm_object_attach_property(&crtc->base, private->bg_prop, 0);
	11135	+ drm_object_attach_property(&crtc->base, private->line_flag_prop, 0);
	11136	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN) {
	11137	+ drm_object_attach_property(&crtc->base,
	11138	+ drm_dev->mode_config.tv_left_margin_property, 100);
	11139	+ drm_object_attach_property(&crtc->base,
	11140	+ drm_dev->mode_config.tv_right_margin_property, 100);
	11141	+ drm_object_attach_property(&crtc->base,
	11142	+ drm_dev->mode_config.tv_top_margin_property, 100);
	11143	+ drm_object_attach_property(&crtc->base,
	11144	+ drm_dev->mode_config.tv_bottom_margin_property, 100);
	11145	+ }
	11146	+ if (plane_mask)
	11147	+ vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
	11148	+ vop2_crtc_create_feature_property(vop2, crtc);
	11149	+ vop2_crtc_create_vrr_property(vop2, crtc);
	11150	+
	11151	+ ret = drm_self_refresh_helper_init(crtc);
	11152	+ if (ret)
	11153	+ DRM_DEV_DEBUG_KMS(vop2->dev,
	11154	+ "Failed to init %s with SR helpers %d, ignoring\n",
	11155	+ crtc->name, ret);
	11156	+
	11157	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
	11158	+ vop2_crtc_create_hdr_property(vop2, crtc);
	11159	+ if (vp_data->feature & VOP_FEATURE_POST_ACM)
	11160	+ vop2_crtc_create_post_acm_property(vop2, crtc);
	11161	+ if (vp_data->feature & VOP_FEATURE_POST_CSC)
	11162	+ vop2_crtc_create_post_csc_property(vop2, crtc);
	11163	+
7206	11164	registered_num_crtcs++;
7207	11165	}
7208	11166
..	..	@@ -7257,8 +11215,11 @@
7257	11215
7258	11216	ret = vop2_plane_init(vop2, win, possible_crtcs);
7259	11217	if (ret)
7260		- DRM_WARN("failed to init overlay plane %s, ret:%d\n", win->name, ret);
	11218	+ DRM_WARN("failed to init overlay plane %s\n", win->name);
7261	11219	}
	11220	+
	11221	+ if (is_vop3(vop2))
	11222	+ vop3_init_esmart_scale_engine(vop2);
7262	11223
7263	11224	return registered_num_crtcs;
7264	11225	}
..	..	@@ -7266,6 +11227,10 @@
7266	11227	static void vop2_destroy_crtc(struct drm_crtc *crtc)
7267	11228	{
7268	11229	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	11230	+
	11231	+ drm_self_refresh_helper_cleanup(crtc);
	11232	+ if (vp->hdr_lut_gem_obj)
	11233	+ rockchip_gem_free_object(&vp->hdr_lut_gem_obj->base);
7269	11234
7270	11235	of_node_put(crtc->port);
7271	11236
..	..	@@ -7277,6 +11242,59 @@
7277	11242	drm_flip_work_cleanup(&vp->fb_unref_work);
7278	11243	}
7279	11244
	11245	+static int vop2_pd_data_init(struct vop2 *vop2)
	11246	+{
	11247	+ const struct vop2_data *vop2_data = vop2->data;
	11248	+ const struct vop2_power_domain_data *pd_data;
	11249	+ struct vop2_power_domain *pd;
	11250	+ int i;
	11251	+
	11252	+ INIT_LIST_HEAD(&vop2->pd_list_head);
	11253	+
	11254	+ for (i = 0; i < vop2_data->nr_pds; i++) {
	11255	+ pd_data = &vop2_data->pd[i];
	11256	+ pd = devm_kzalloc(vop2->dev, sizeof(*pd), GFP_KERNEL);
	11257	+ if (!pd)
	11258	+ return -ENOMEM;
	11259	+ pd->vop2 = vop2;
	11260	+ pd->data = pd_data;
	11261	+ pd->vp_mask = 0;
	11262	+ spin_lock_init(&pd->lock);
	11263	+ list_add_tail(&pd->list, &vop2->pd_list_head);
	11264	+ INIT_DELAYED_WORK(&pd->power_off_work, vop2_power_domain_off_work);
	11265	+ if (pd_data->parent_id) {
	11266	+ pd->parent = vop2_find_pd_by_id(vop2, pd_data->parent_id);
	11267	+ if (!pd->parent) {
	11268	+ DRM_DEV_ERROR(vop2->dev, "no parent pd find for pd%d\n", pd->data->id);
	11269	+ return -EINVAL;
	11270	+ }
	11271	+ }
	11272	+ }
	11273	+
	11274	+ return 0;
	11275	+}
	11276	+
	11277	+static void vop2_dsc_data_init(struct vop2 *vop2)
	11278	+{
	11279	+ const struct vop2_data *vop2_data = vop2->data;
	11280	+ const struct vop2_dsc_data *dsc_data;
	11281	+ struct vop2_dsc *dsc;
	11282	+ int i;
	11283	+
	11284	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	11285	+ dsc = &vop2->dscs[i];
	11286	+ dsc_data = &vop2_data->dsc[i];
	11287	+ dsc->id = dsc_data->id;
	11288	+ dsc->max_slice_num = dsc_data->max_slice_num;
	11289	+ dsc->max_linebuf_depth = dsc_data->max_linebuf_depth;
	11290	+ dsc->min_bits_per_pixel = dsc_data->min_bits_per_pixel;
	11291	+ dsc->regs = dsc_data->regs;
	11292	+ dsc->attach_vp_id = -1;
	11293	+ if (dsc_data->pd_id)
	11294	+ dsc->pd = vop2_find_pd_by_id(vop2, dsc_data->pd_id);
	11295	+ }
	11296	+}
	11297	+
7280	11298	static int vop2_win_init(struct vop2 *vop2)
7281	11299	{
7282	11300	const struct vop2_data *vop2_data = vop2->data;
..	..	@@ -7284,7 +11302,6 @@
7284	11302	struct drm_prop_enum_list *plane_name_list;
7285	11303	struct vop2_win *win;
7286	11304	struct vop2_layer *layer;
7287		- struct drm_property *prop;
7288	11305	char name[DRM_PROP_NAME_LEN];
7289	11306	unsigned int num_wins = 0;
7290	11307	uint8_t plane_id = 0;
..	..	@@ -7313,6 +11330,7 @@
7313	11330	win->dly = win_data->dly;
7314	11331	win->feature = win_data->feature;
7315	11332	win->phys_id = win_data->phys_id;
	11333	+ win->splice_win_id = win_data->splice_win_id;
7316	11334	win->layer_sel_id = win_data->layer_sel_id;
7317	11335	win->win_id = i;
7318	11336	win->plane_id = plane_id++;
..	..	@@ -7322,8 +11340,10 @@
7322	11340	win->axi_id = win_data->axi_id;
7323	11341	win->axi_yrgb_id = win_data->axi_yrgb_id;
7324	11342	win->axi_uv_id = win_data->axi_uv_id;
7325		- win->scale_engine_num = win_data->scale_engine_num;
7326	11343	win->possible_crtcs = win_data->possible_crtcs;
	11344	+
	11345	+ if (win_data->pd_id)
	11346	+ win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id);
7327	11347
7328	11348	num_wins++;
7329	11349
..	..	@@ -7351,6 +11371,7 @@
7351	11371	area->vsd_filter_mode = win_data->vsd_filter_mode;
7352	11372	area->hsd_pre_filter_mode = win_data->hsd_pre_filter_mode;
7353	11373	area->vsd_pre_filter_mode = win_data->vsd_pre_filter_mode;
	11374	+ area->possible_crtcs = win->possible_crtcs;
7354	11375
7355	11376	area->vop2 = vop2;
7356	11377	area->win_id = i;
..	..	@@ -7363,6 +11384,7 @@
7363	11384	num_wins++;
7364	11385	}
7365	11386	}
	11387	+
7366	11388	vop2->registered_num_wins = num_wins;
7367	11389
7368	11390	if (!is_vop3(vop2)) {
..	..	@@ -7390,28 +11412,136 @@
7390	11412
7391	11413	vop2->plane_name_list = plane_name_list;
7392	11414
7393		- prop = drm_property_create_object(vop2->drm_dev,
7394		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
7395		- "SOC_ID", DRM_MODE_OBJECT_CRTC);
7396		- vop2->soc_id_prop = prop;
	11415	+ return 0;
	11416	+}
7397	11417
7398		- prop = drm_property_create_object(vop2->drm_dev,
7399		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
7400		- "PORT_ID", DRM_MODE_OBJECT_CRTC);
7401		- vop2->vp_id_prop = prop;
	11418	+#include "rockchip_vop2_clk.c"
	11419	+static void post_buf_empty_work_event(struct work_struct *work)
	11420	+{
	11421	+ struct vop2 *vop2 = container_of(work, struct vop2, post_buf_empty_work);
	11422	+ struct rockchip_drm_private *private = vop2->drm_dev->dev_private;
	11423	+ struct vop2_video_port *vp = &vop2->vps[1];
7402	11424
7403		- vop2->aclk_prop = drm_property_create_range(vop2->drm_dev, 0, "ACLK", 0, UINT_MAX);
7404		- vop2->bg_prop = drm_property_create_range(vop2->drm_dev, 0, "BACKGROUND", 0, UINT_MAX);
	11425	+ /*
	11426	+ * For RK3528, VP1 only supports NTSC and PAL mode(both interlace). If
	11427	+ * POST_BUF_EMPTY_INTR comes, it is needed to reset the p2i_en bit, in
	11428	+ * order to update the line parity flag, which ensures the correct order
	11429	+ * of odd and even lines.
	11430	+ */
	11431	+ if (vop2->version == VOP_VERSION_RK3528) {
	11432	+ if (atomic_read(&vp->post_buf_empty_flag) > 0) {
	11433	+ atomic_set(&vp->post_buf_empty_flag, 0);
7405	11434
7406		- vop2->line_flag_prop = drm_property_create_range(vop2->drm_dev, 0, "LINE_FLAG1", 0, UINT_MAX);
	11435	+ mutex_lock(&private->ovl_lock);
	11436	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11437	+ VOP_MODULE_SET(vop2, vp, p2i_en, 0);
	11438	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	11439	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11440	+ mutex_unlock(&private->ovl_lock);
7407	11441
7408		- if (!vop2->soc_id_prop \|\| !vop2->vp_id_prop \|\| !vop2->aclk_prop \|\| !vop2->bg_prop \|\|
7409		- !vop2->line_flag_prop) {
7410		- DRM_DEV_ERROR(vop2->dev, "failed to create soc_id/vp_id/aclk property\n");
7411		- return -ENOMEM;
	11442	+ vp->need_reset_p2i_flag = true;
	11443	+ } else if (vp->need_reset_p2i_flag == true) {
	11444	+ mutex_lock(&private->ovl_lock);
	11445	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11446	+ VOP_MODULE_SET(vop2, vp, p2i_en, 1);
	11447	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	11448	+ vop2_wait_for_fs_by_done_bit_status(vp);
	11449	+ mutex_unlock(&private->ovl_lock);
	11450	+
	11451	+ vp->need_reset_p2i_flag = false;
	11452	+ }
	11453	+ }
	11454	+}
	11455	+
	11456	+static bool vop2_plane_mask_check(struct vop2 *vop2)
	11457	+{
	11458	+ const struct vop2_data *vop2_data = vop2->data;
	11459	+ u32 plane_mask = 0;
	11460	+ int i;
	11461	+
	11462	+ /*
	11463	+ * For RK3568 and RK3588, all windows need to be assigned to
	11464	+ * one of all vps, and two of vps can not share the same window.
	11465	+ */
	11466	+ if (vop2->version != VOP_VERSION_RK3568 && vop2->version != VOP_VERSION_RK3588)
	11467	+ return true;
	11468	+
	11469	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	11470	+ if (plane_mask & vop2->vps[i].plane_mask) {
	11471	+ DRM_WARN("the same window can't be assigned to two vp\n");
	11472	+ return false;
	11473	+ }
	11474	+ plane_mask \|= vop2->vps[i].plane_mask;
7412	11475	}
7413	11476
7414		- return 0;
	11477	+ if (hweight32(plane_mask) != vop2_data->nr_layers \|\|
	11478	+ plane_mask != vop2_data->plane_mask_base) {
	11479	+ DRM_WARN("all windows should be assigned, full plane mask: 0x%x, current plane mask: 0x%x\n",
	11480	+ vop2_data->plane_mask_base, plane_mask);
	11481	+ return false;
	11482	+ }
	11483	+
	11484	+ return true;
	11485	+}
	11486	+
	11487	+static uint32_t vop2_vp_plane_mask_to_bitmap(const struct vop2_vp_plane_mask *vp_plane_mask)
	11488	+{
	11489	+ int layer_phy_id = 0;
	11490	+ int plane_mask = 0;
	11491	+ int i;
	11492	+
	11493	+ for (i = 0; i < vp_plane_mask->attached_layers_nr; i++) {
	11494	+ layer_phy_id = vp_plane_mask->attached_layers[i];
	11495	+ plane_mask \|= BIT(layer_phy_id);
	11496	+ }
	11497	+
	11498	+ return plane_mask;
	11499	+}
	11500	+
	11501	+static bool vop2_get_vp_of_status(struct device_node *vp_node)
	11502	+{
	11503	+ struct device_node *vp_sub_node;
	11504	+ struct device_node *remote_node;
	11505	+ bool vp_enable = false;
	11506	+
	11507	+ for_each_child_of_node(vp_node, vp_sub_node) {
	11508	+ remote_node = of_graph_get_remote_endpoint(vp_sub_node);
	11509	+ vp_enable \|= of_device_is_available(remote_node);
	11510	+ }
	11511	+
	11512	+ return vp_enable;
	11513	+}
	11514	+
	11515	+static void vop2_plane_mask_assign(struct vop2 vop2, struct device_node vop_out_node)
	11516	+{
	11517	+ const struct vop2_data *vop2_data = vop2->data;
	11518	+ const struct vop2_vp_plane_mask *plane_mask;
	11519	+ struct device_node *child;
	11520	+ int active_vp_num = 0;
	11521	+ int vp_id;
	11522	+ int i = 0;
	11523	+
	11524	+ for_each_child_of_node(vop_out_node, child) {
	11525	+ if (vop2_get_vp_of_status(child))
	11526	+ active_vp_num++;
	11527	+ }
	11528	+
	11529	+ if (vop2_soc_is_rk3566() && active_vp_num > 2)
	11530	+ DRM_WARN("RK3566 only support 2 vps\n");
	11531	+ plane_mask = vop2_data->plane_mask;
	11532	+ plane_mask += (active_vp_num - 1) * ROCKCHIP_MAX_CRTC;
	11533	+
	11534	+ for_each_child_of_node(vop_out_node, child) {
	11535	+ of_property_read_u32(child, "reg", &vp_id);
	11536	+ if (vop2_get_vp_of_status(child)) {
	11537	+ vop2->vps[vp_id].plane_mask = vop2_vp_plane_mask_to_bitmap(&plane_mask[i]);
	11538	+ vop2->vps[vp_id].primary_plane_phy_id = plane_mask[i].primary_plane_id;
	11539	+ i++;
	11540	+ } else {
	11541	+ vop2->vps[vp_id].plane_mask = 0;
	11542	+ vop2->vps[vp_id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
	11543	+ }
	11544	+ }
7415	11545	}
7416	11546
7417	11547	static int vop2_bind(struct device dev, struct device master, void *data)
..	..	@@ -7426,6 +11556,7 @@
7426	11556	int num_wins = 0;
7427	11557	int registered_num_crtcs;
7428	11558	struct device_node *vop_out_node;
	11559	+ struct device_node *mcu_timing_node;
7429	11560
7430	11561	vop2_data = of_device_get_match_data(dev);
7431	11562	if (!vop2_data)
..	..	@@ -7454,6 +11585,26 @@
7454	11585	vop2->disable_afbc_win = of_property_read_bool(dev->of_node, "disable-afbc-win");
7455	11586	vop2->disable_win_move = of_property_read_bool(dev->of_node, "disable-win-move");
7456	11587	vop2->skip_ref_fb = of_property_read_bool(dev->of_node, "skip-ref-fb");
	11588	+
	11589	+ ret = vop2_pd_data_init(vop2);
	11590	+ if (ret)
	11591	+ return ret;
	11592	+ /*
	11593	+ * esmart lb mode default config at vop2_reg.c vop2_data.esmart_lb_mode,
	11594	+ * you can rewrite at dts vop node:
	11595	+ *
	11596	+ * VOP3_ESMART_8K_MODE = 0,
	11597	+ * VOP3_ESMART_4K_4K_MODE = 1,
	11598	+ * VOP3_ESMART_4K_2K_2K_MODE = 2,
	11599	+ * VOP3_ESMART_2K_2K_2K_2K_MODE = 3,
	11600	+ *
	11601	+ * &vop {
	11602	+ * esmart_lb_mode = /bits/ 8 <2>;
	11603	+ * };
	11604	+ */
	11605	+ ret = of_property_read_u8(dev->of_node, "esmart_lb_mode", &vop2->esmart_lb_mode);
	11606	+ if (ret < 0)
	11607	+ vop2->esmart_lb_mode = vop2->data->esmart_lb_mode;
7457	11608
7458	11609	ret = vop2_win_init(vop2);
7459	11610	if (ret)
..	..	@@ -7488,7 +11639,10 @@
7488	11639	return PTR_ERR(vop2->acm_regs);
7489	11640	}
7490	11641
7491		- vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11642	+ vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11643	+ vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");
	11644	+ vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");
	11645	+ vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
7492	11646
7493	11647	vop2->hclk = devm_clk_get(vop2->dev, "hclk_vop");
7494	11648	if (IS_ERR(vop2->hclk)) {
..	..	@@ -7499,6 +11653,24 @@
7499	11653	if (IS_ERR(vop2->aclk)) {
7500	11654	DRM_DEV_ERROR(vop2->dev, "failed to get aclk source\n");
7501	11655	return PTR_ERR(vop2->aclk);
	11656	+ }
	11657	+
	11658	+ vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");
	11659	+ if (IS_ERR(vop2->pclk)) {
	11660	+ DRM_DEV_ERROR(vop2->dev, "failed to get pclk source\n");
	11661	+ return PTR_ERR(vop2->pclk);
	11662	+ }
	11663	+
	11664	+ vop2->ahb_rst = devm_reset_control_get_optional(vop2->dev, "ahb");
	11665	+ if (IS_ERR(vop2->ahb_rst)) {
	11666	+ DRM_DEV_ERROR(vop2->dev, "failed to get ahb reset\n");
	11667	+ return PTR_ERR(vop2->ahb_rst);
	11668	+ }
	11669	+
	11670	+ vop2->axi_rst = devm_reset_control_get_optional(vop2->dev, "axi");
	11671	+ if (IS_ERR(vop2->axi_rst)) {
	11672	+ DRM_DEV_ERROR(vop2->dev, "failed to get axi reset\n");
	11673	+ return PTR_ERR(vop2->axi_rst);
7502	11674	}
7503	11675
7504	11676	vop2->irq = platform_get_irq(pdev, 0);
..	..	@@ -7515,6 +11687,7 @@
7515	11687	u32 plane_mask = 0;
7516	11688	u32 primary_plane_phy_id = 0;
7517	11689	u32 vp_id = 0;
	11690	+ u32 val = 0;
7518	11691
7519	11692	of_property_read_u32(child, "rockchip,plane-mask", &plane_mask);
7520	11693	of_property_read_u32(child, "rockchip,primary-plane", &primary_plane_phy_id);
..	..	@@ -7528,26 +11701,66 @@
7528	11701
7529	11702	vop2->vps[vp_id].xmirror_en = of_property_read_bool(child, "xmirror-enable");
7530	11703
	11704	+ ret = of_clk_set_defaults(child, false);
	11705	+ if (ret) {
	11706	+ DRM_DEV_ERROR(dev, "Failed to set clock defaults %d\n", ret);
	11707	+ return ret;
	11708	+ }
	11709	+
	11710	+ mcu_timing_node = of_get_child_by_name(child, "mcu-timing");
	11711	+ if (mcu_timing_node) {
	11712	+ if (!of_property_read_u32(mcu_timing_node, "mcu-pix-total", &val))
	11713	+ vop2->vps[vp_id].mcu_timing.mcu_pix_total = val;
	11714	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pst", &val))
	11715	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pst = val;
	11716	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pend", &val))
	11717	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pend = val;
	11718	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pst", &val))
	11719	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pst = val;
	11720	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pend", &val))
	11721	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pend = val;
	11722	+ if (!of_property_read_u32(mcu_timing_node, "mcu-hold-mode", &val))
	11723	+ vop2->vps[vp_id].mcu_timing.mcu_hold_mode = val;
	11724	+ }
	11725	+ }
	11726	+
	11727	+ if (!vop2_plane_mask_check(vop2)) {
	11728	+ DRM_WARN("use default plane mask\n");
	11729	+ vop2_plane_mask_assign(vop2, vop_out_node);
	11730	+ }
	11731	+
	11732	+ for (i = 0; i < vop2->data->nr_vps; i++) {
7531	11733	DRM_DEV_INFO(dev, "vp%d assign plane mask: 0x%x, primary plane phy id: %d\n",
7532		- vp_id, vop2->vps[vp_id].plane_mask,
7533		- vop2->vps[vp_id].primary_plane_phy_id);
	11734	+ i, vop2->vps[i].plane_mask,
	11735	+ vop2->vps[i].primary_plane_phy_id);
7534	11736	}
7535	11737	}
7536	11738
	11739	+ vop2_extend_clk_init(vop2);
7537	11740	spin_lock_init(&vop2->reg_lock);
7538	11741	spin_lock_init(&vop2->irq_lock);
7539	11742	mutex_init(&vop2->vop2_lock);
	11743	+
	11744	+ if (vop2->version == VOP_VERSION_RK3528) {
	11745	+ atomic_set(&vop2->vps[1].post_buf_empty_flag, 0);
	11746	+ vop2->workqueue = create_workqueue("post_buf_empty_wq");
	11747	+ INIT_WORK(&vop2->post_buf_empty_work, post_buf_empty_work_event);
	11748	+ }
7540	11749
7541	11750	ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
7542	11751	if (ret)
7543	11752	return ret;
7544	11753
	11754	+ vop2_dsc_data_init(vop2);
	11755	+
7545	11756	registered_num_crtcs = vop2_create_crtc(vop2);
7546	11757	if (registered_num_crtcs <= 0)
7547	11758	return -ENODEV;
	11759	+
7548	11760	ret = vop2_gamma_init(vop2);
7549	11761	if (ret)
7550	11762	return ret;
	11763	+ vop2_clk_init(vop2);
7551	11764	vop2_cubic_lut_init(vop2);
7552	11765	vop2_wb_connector_init(vop2, registered_num_crtcs);
7553	11766	pm_runtime_enable(&pdev->dev);