~hc/RK356X_SDK_RELEASE.git

..	..	@@ -4,12 +4,18 @@
4	4	* Author: Andy Yan <andy.yan@rock-chips.com>
5	5	*/
6	6	#include <drm/drm.h>
7		-#include <drm/drmP.h>
8	7	#include <drm/drm_atomic.h>
	8	+#include <drm/drm_atomic_uapi.h>
9	9	#include <drm/drm_crtc.h>
10	10	#include <drm/drm_crtc_helper.h>
	11	+#include <drm/drm_debugfs.h>
11	12	#include <drm/drm_flip_work.h>
	13	+#include <drm/drm_fourcc.h>
	14	+#include <drm/drm_gem_framebuffer_helper.h>
12	15	#include <drm/drm_plane_helper.h>
	16	+#include <drm/drm_probe_helper.h>
	17	+#include <drm/drm_self_refresh_helper.h>
	18	+
13	19	#include <drm/drm_writeback.h>
14	20	#ifdef CONFIG_DRM_ANALOGIX_DP
15	21	#include <drm/bridge/analogix_dp.h>
..	..	@@ -23,6 +29,8 @@
23	29	#include <linux/module.h>
24	30	#include <linux/platform_device.h>
25	31	#include <linux/clk.h>
	32	+#include <linux/clk-provider.h>
	33	+#include <linux/clk/clk-conf.h>
26	34	#include <linux/iopoll.h>
27	35	#include <linux/of.h>
28	36	#include <linux/of_device.h>
..	..	@@ -30,6 +38,7 @@
30	38	#include <linux/pm_runtime.h>
31	39	#include <linux/component.h>
32	40	#include <linux/regmap.h>
	41	+#include <linux/reset.h>
33	42	#include <linux/mfd/syscon.h>
34	43	#include <linux/delay.h>
35	44	#include <linux/swab.h>
..	..	@@ -41,12 +50,12 @@
41	50	#include <soc/rockchip/rockchip-system-status.h>
42	51	#include <uapi/linux/videodev2.h>
43	52
	53	+#include "../drm_crtc_internal.h"
44	54	#include "../drm_internal.h"
45	55
46	56	#include "rockchip_drm_drv.h"
47	57	#include "rockchip_drm_gem.h"
48	58	#include "rockchip_drm_fb.h"
49		-#include "rockchip_drm_psr.h"
50	59	#include "rockchip_drm_vop.h"
51	60	#include "rockchip_vop_reg.h"
52	61	#include "rockchip_post_csc.h"
..	..	@@ -117,27 +126,32 @@
117	126	#define VOP_WIN_GET(vop2, win, name) \
118	127	vop2_read_reg(vop2, win->offset, &VOP_WIN_NAME(win, name))
119	128
	129	+#define VOP_WIN_GET_REG_BAK(vop2, win, name) \
	130	+ vop2_read_reg_bak(vop2, win->offset, &VOP_WIN_NAME(win, name))
	131	+
120	132	#define VOP_WIN_NAME(win, name) \
121	133	(vop2_get_win_regs(win, &win->regs->name)->name)
122	134
123	135	#define VOP_WIN_TO_INDEX(vop2_win) \
124	136	((vop2_win) - (vop2_win)->vop2->win)
125	137
126		-#define VOP_GRF_SET(vop2, reg, v) \
	138	+#define VOP_GRF_SET(vop2, grf, reg, v) \
127	139	do { \
128		- if (vop2->data->grf_ctrl) { \
129		- vop2_grf_writel(vop2, vop2->data->grf_ctrl->reg, v); \
	140	+ if (vop2->data->grf) { \
	141	+ vop2_grf_writel(vop2->grf, vop2->data->grf->reg, v); \
130	142	} \
131	143	} while (0)
132	144
133		-#define to_vop2_video_port(c) container_of(c, struct vop2_video_port, crtc)
134	145	#define to_vop2_win(x) container_of(x, struct vop2_win, base)
135	146	#define to_vop2_plane_state(x) container_of(x, struct vop2_plane_state, base)
136	147	#define to_wb_state(x) container_of(x, struct vop2_wb_connector_state, base)
137		-
138		-#ifndef drm_is_afbc
139		-#define drm_is_afbc(modifier) (((modifier) >> 56) == DRM_FORMAT_MOD_VENDOR_ARM)
140		-#endif
	148	+#define output_if_is_hdmi(x) (x & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1))
	149	+#define output_if_is_dp(x) (x & (VOP_OUTPUT_IF_DP0 \| VOP_OUTPUT_IF_DP1))
	150	+#define output_if_is_edp(x) (x & (VOP_OUTPUT_IF_eDP0 \| VOP_OUTPUT_IF_eDP1))
	151	+#define output_if_is_mipi(x) (x & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_MIPI1))
	152	+#define output_if_is_lvds(x) (x & (VOP_OUTPUT_IF_LVDS0 \| VOP_OUTPUT_IF_LVDS1))
	153	+#define output_if_is_dpi(x) (x & (VOP_OUTPUT_IF_BT656 \| VOP_OUTPUT_IF_BT1120 \| \
	154	+ VOP_OUTPUT_IF_RGB))
141	155
142	156	/*
143	157	* max two jobs a time, one is running(writing back),
..	..	@@ -146,7 +160,11 @@
146	160	#define VOP2_WB_JOB_MAX 2
147	161	#define VOP2_SYS_AXI_BUS_NUM 2
148	162
149		-#define VOP2_CLUSTER_YUV444_10 0x12
	163	+#define VOP2_MAX_VP_OUTPUT_WIDTH 4096
	164	+/* KHZ */
	165	+#define VOP2_MAX_DCLK_RATE 600000
	166	+/* KHZ */
	167	+#define VOP2_COMMON_ACLK_RATE 500000
150	168
151	169	enum vop2_data_format {
152	170	VOP2_FMT_ARGB8888 = 0,
..	..	@@ -238,6 +256,36 @@
238	256	ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
239	257	};
240	258
	259	+struct vop2_power_domain {
	260	+ struct vop2_power_domain *parent;
	261	+ struct vop2 *vop2;
	262	+ /*
	263	+ * @lock: protect power up/down procedure.
	264	+ * power on take effect immediately,
	265	+ * power down take effect by vsync.
	266	+ * we must check power_domain_status register
	267	+ * to make sure the power domain is down before
	268	+ * send a power on request.
	269	+ *
	270	+ */
	271	+ spinlock_t lock;
	272	+ unsigned int ref_count;
	273	+ bool on;
	274	+ /* @vp_mask: Bit mask of video port of the power domain's
	275	+ * module attached to.
	276	+ * For example: PD_CLUSTER0 belongs to module Cluster0, it's
	277	+ * bitmask is the VP which Cluster0 attached to. PD_ESMART is
	278	+ * shared between Esmart1/2/3, it's bitmask will be all the VP
	279	+ * which Esmart1/2/3 attached to.
	280	+ * This is used to check if we can power off a PD by vsync.
	281	+ */
	282	+ uint8_t vp_mask;
	283	+
	284	+ const struct vop2_power_domain_data *data;
	285	+ struct list_head list;
	286	+ struct delayed_work power_off_work;
	287	+};
	288	+
241	289	struct vop2_zpos {
242	290	struct drm_plane *plane;
243	291	int win_phys_id;
..	..	@@ -321,7 +369,6 @@
321	369	int global_alpha;
322	370	int blend_mode;
323	371	uint64_t color_key;
324		- void *yrgb_kvaddr;
325	372	unsigned long offset;
326	373	int pdaf_data_type;
327	374	bool async_commit;
..	..	@@ -343,11 +390,37 @@
343	390	bool two_win_mode;
344	391
345	392	/**
	393	+ * ---------------------------
	394	+ * \| \| \|
	395	+ * \| Left \| Right \|
	396	+ * \| \| \|
	397	+ * \| Cluster0 \| Cluster1 \|
	398	+ * ---------------------------
	399	+ */
	400	+
	401	+ /*
	402	+ * @splice_mode_right: As right part of the screen in splice mode.
	403	+ */
	404	+ bool splice_mode_right;
	405	+
	406	+ /**
	407	+ * @splice_win: splice win which used to splice for a plane
	408	+ * hdisplay > 4096
	409	+ */
	410	+ struct vop2_win *splice_win;
	411	+ struct vop2_win *left_win;
	412	+
	413	+ uint8_t splice_win_id;
	414	+
	415	+ struct vop2_power_domain *pd;
	416	+
	417	+ /**
346	418	* @phys_id: physical id for cluster0/1, esmart0/1, smart0/1
347	419	* Will be used as a identification for some register
348	420	* configuration such as OVL_LAYER_SEL/OVL_PORT_SEL.
349	421	*/
350	422	uint8_t phys_id;
	423	+
351	424	/**
352	425	* @win_id: graphic window id, a cluster maybe split into two
353	426	* graphics windows.
..	..	@@ -415,6 +488,7 @@
415	488	};
416	489
417	490	struct vop2_cluster {
	491	+ bool splice_mode;
418	492	struct vop2_win *main;
419	493	struct vop2_win *sub;
420	494	};
..	..	@@ -456,6 +530,17 @@
456	530
457	531	};
458	532
	533	+struct vop2_dsc {
	534	+ uint8_t id;
	535	+ uint8_t max_slice_num;
	536	+ uint8_t max_linebuf_depth; /* used to generate the bitstream */
	537	+ uint8_t min_bits_per_pixel; /* bit num after encoder compress */
	538	+ bool enabled;
	539	+ char attach_vp_id;
	540	+ const struct vop2_dsc_regs *regs;
	541	+ struct vop2_power_domain *pd;
	542	+};
	543	+
459	544	enum vop2_wb_format {
460	545	VOP2_WB_ARGB8888,
461	546	VOP2_WB_BGR888,
..	..	@@ -476,9 +561,12 @@
476	561	};
477	562
478	563	struct vop2_video_port {
479		- struct drm_crtc crtc;
	564	+ struct rockchip_crtc rockchip_crtc;
	565	+ struct rockchip_mcu_timing mcu_timing;
480	566	struct vop2 *vop2;
	567	+ struct reset_control *dclk_rst;
481	568	struct clk *dclk;
	569	+ struct clk *dclk_parent;
482	570	uint8_t id;
483	571	bool layer_sel_update;
484	572	bool xmirror_en;
..	..	@@ -531,6 +619,26 @@
531	619	int hdr_en;
532	620
533	621	/**
	622	+ * -----------------
	623	+ * \| \| \|
	624	+ * \| Left \| Right \|
	625	+ * \| \| \|
	626	+ * \| VP0 \| VP1 \|
	627	+ * -----------------
	628	+ * @splice_mode_right: As right part of the screen in splice mode.
	629	+ */
	630	+ bool splice_mode_right;
	631	+
	632	+ /**
	633	+ * @hdr10_at_splice_mode: enable hdr10 at splice mode on rk3588.
	634	+ */
	635	+ bool hdr10_at_splice_mode;
	636	+ /**
	637	+ * @left_vp: VP as left part of the screen in splice mode.
	638	+ */
	639	+ struct vop2_video_port *left_vp;
	640	+
	641	+ /**
534	642	* @win_mask: Bitmask of wins attached to the video port;
535	643	*/
536	644	uint32_t win_mask;
..	..	@@ -540,6 +648,12 @@
540	648	uint8_t nr_layers;
541	649
542	650	int cursor_win_id;
	651	+ /**
	652	+ * @output_if: output connector attached to the video port,
	653	+ * this flag is maintained in vop driver, updated in crtc_atomic_enable,
	654	+ * cleared in crtc_atomic_disable;
	655	+ */
	656	+ u32 output_if;
543	657
544	658	/**
545	659	* @active_tv_state: TV connector related states
..	..	@@ -606,6 +720,25 @@
606	720	* @plane_mask_prop: plane mask interaction with userspace
607	721	*/
608	722	struct drm_property *plane_mask_prop;
	723	+ /**
	724	+ * @feature_prop: crtc feature interaction with userspace
	725	+ */
	726	+ struct drm_property *feature_prop;
	727	+
	728	+ /**
	729	+ * @variable_refresh_rate_prop: crtc variable refresh rate interaction with userspace
	730	+ */
	731	+ struct drm_property *variable_refresh_rate_prop;
	732	+
	733	+ /**
	734	+ * @max_refresh_rate_prop: crtc max refresh rate interaction with userspace
	735	+ */
	736	+ struct drm_property *max_refresh_rate_prop;
	737	+
	738	+ /**
	739	+ * @min_refresh_rate_prop: crtc min refresh rate interaction with userspace
	740	+ */
	741	+ struct drm_property *min_refresh_rate_prop;
609	742
610	743	/**
611	744	* @hdr_ext_data_prop: hdr extend data interaction with userspace
..	..	@@ -622,6 +755,14 @@
622	755	* @post_csc_data_prop: post csc data interaction with userspace
623	756	*/
624	757	struct drm_property *post_csc_data_prop;
	758	+ /**
	759	+ * @output_width_prop: vp max output width prop
	760	+ */
	761	+ struct drm_property *output_width_prop;
	762	+ /**
	763	+ * @output_dclk_prop: vp max output dclk prop
	764	+ */
	765	+ struct drm_property *output_dclk_prop;
625	766
626	767	/**
627	768	* @primary_plane_phy_id: vp primary plane phy id, the primary plane
..	..	@@ -629,23 +770,28 @@
629	770	*/
630	771	enum vop2_layer_phy_id primary_plane_phy_id;
631	772
632		- struct post_acm acm_info;
633		- struct post_csc csc_info;
	773	+ /**
	774	+ * @refresh_rate_change: indicate whether refresh rate change
	775	+ */
	776	+ bool refresh_rate_change;
	777	+};
	778	+
	779	+struct vop2_extend_pll {
	780	+ struct list_head list;
	781	+ struct clk *clk;
	782	+ char clk_name[32];
	783	+ u32 vp_mask;
634	784	};
635	785
636	786	struct vop2 {
637	787	u32 version;
638	788	struct device *dev;
639	789	struct drm_device *drm_dev;
	790	+ struct vop2_dsc dscs[ROCKCHIP_MAX_CRTC];
640	791	struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
641	792	struct vop2_wb wb;
642	793	struct dentry *debugfs;
643	794	struct drm_info_list *debugfs_files;
644		- struct drm_property *soc_id_prop;
645		- struct drm_property *vp_id_prop;
646		- struct drm_property *aclk_prop;
647		- struct drm_property *bg_prop;
648		- struct drm_property *line_flag_prop;
649	795	struct drm_prop_enum_list *plane_name_list;
650	796	bool is_iommu_enabled;
651	797	bool is_iommu_needed;
..	..	@@ -681,6 +827,9 @@
681	827
682	828	bool loader_protect;
683	829
	830	+ bool aclk_rate_reset;
	831	+ unsigned long aclk_rate;
	832	+
684	833	const struct vop2_data *data;
685	834	/* Number of win that registered as plane,
686	835	* maybe less than the total number of hardware
..	..	@@ -699,6 +848,10 @@
699	848	struct resource *res;
700	849	void __iomem *regs;
701	850	struct regmap *grf;
	851	+ struct regmap *sys_grf;
	852	+ struct regmap *vo0_grf;
	853	+ struct regmap *vo1_grf;
	854	+ struct regmap *sys_pmu;
702	855
703	856	/* physical map length of vop2 register */
704	857	uint32_t len;
..	..	@@ -721,6 +874,15 @@
721	874	unsigned int enable_count;
722	875	struct clk *hclk;
723	876	struct clk *aclk;
	877	+ struct clk *pclk;
	878	+ struct reset_control *ahb_rst;
	879	+ struct reset_control *axi_rst;
	880	+
	881	+ /* list_head of extend clk */
	882	+ struct list_head extend_clk_list_head;
	883	+ /* list_head of internal clk */
	884	+ struct list_head clk_list_head;
	885	+ struct list_head pd_list_head;
724	886	struct work_struct post_buf_empty_work;
725	887	struct workqueue_struct *workqueue;
726	888
..	..	@@ -728,6 +890,18 @@
728	890	/* must put at the end of the struct */
729	891	struct vop2_win win[];
730	892	};
	893	+
	894	+struct vop2_clk {
	895	+ struct vop2 *vop2;
	896	+ struct list_head list;
	897	+ unsigned long rate;
	898	+ struct clk_hw hw;
	899	+ struct clk_divider div;
	900	+ int div_val;
	901	+ u8 parent_index;
	902	+};
	903	+
	904	+#define to_vop2_clk(_hw) container_of(_hw, struct vop2_clk, hw)
731	905
732	906	/*
733	907	* bus-format types.
..	..	@@ -743,23 +917,32 @@
743	917	{ MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" },
744	918	{ MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" },
745	919	{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" },
746		- { MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA, "RGB666_1X7X3_JEIDA" },
747	920	{ MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" },
748	921	{ MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" },
749	922	{ MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" },
750	923	{ MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" },
751		- { MEDIA_BUS_FMT_SRGB888_3X8, "SRGB888_3X8" },
752		- { MEDIA_BUS_FMT_SRGB888_DUMMY_4X8, "SRGB888_DUMMY_4X8" },
	924	+ { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" },
	925	+ { MEDIA_BUS_FMT_RGB888_DUMMY_4X8, "RGB888_DUMMY_4X8" },
753	926	{ MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" },
754	927	{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" },
755	928	{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" },
756	929	{ MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" },
757	930	{ MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" },
758	931	{ MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" },
759		- { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1x30" },
	932	+ { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" },
	933	+ { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" },
760	934	};
761	935
762	936	static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list)
	937	+
	938	+static inline struct vop2_video_port to_vop2_video_port(struct drm_crtc crtc)
	939	+{
	940	+ struct rockchip_crtc *rockchip_crtc;
	941	+
	942	+ rockchip_crtc = container_of(crtc, struct rockchip_crtc, crtc);
	943	+
	944	+ return container_of(rockchip_crtc, struct vop2_video_port, rockchip_crtc);
	945	+}
763	946
764	947	static void vop2_lock(struct vop2 *vop2)
765	948	{
..	..	@@ -773,17 +956,26 @@
773	956	mutex_unlock(&vop2->vop2_lock);
774	957	}
775	958
776		-static inline void vop2_grf_writel(struct vop2 *vop2, struct vop_reg reg, u32 v)
	959	+static inline void vop2_grf_writel(struct regmap *regmap, struct vop_reg reg, u32 v)
777	960	{
778	961	u32 val = 0;
779	962
780		- if (IS_ERR_OR_NULL(vop2->grf))
	963	+ if (IS_ERR_OR_NULL(regmap))
781	964	return;
782	965
783	966	if (reg.mask) {
784	967	val = (v << reg.shift) \| (reg.mask << (reg.shift + 16));
785		- regmap_write(vop2->grf, reg.offset, val);
	968	+ regmap_write(regmap, reg.offset, val);
786	969	}
	970	+}
	971	+
	972	+static inline uint32_t vop2_grf_readl(struct regmap regmap, const struct vop_reg reg)
	973	+{
	974	+ uint32_t v;
	975	+
	976	+ regmap_read(regmap, reg->offset, &v);
	977	+
	978	+ return v;
787	979	}
788	980
789	981	static inline void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -801,6 +993,26 @@
801	993	const struct vop_reg *reg)
802	994	{
803	995	return (vop2_readl(vop2, base + reg->offset) >> reg->shift) & reg->mask;
	996	+}
	997	+
	998	+static inline uint32_t vop2_read_reg_bak(struct vop2 *vop2, uint32_t base,
	999	+ const struct vop_reg *reg)
	1000	+{
	1001	+ return (vop2->regsbak[(base + reg->offset) >> 2] >> reg->shift) & reg->mask;
	1002	+}
	1003	+
	1004	+static inline uint32_t vop2_read_grf_reg(struct regmap regmap, const struct vop_reg reg)
	1005	+{
	1006	+ return (vop2_grf_readl(regmap, reg) >> reg->shift) & reg->mask;
	1007	+}
	1008	+
	1009	+static inline void vop2_write_reg_uncached(struct vop2 vop2, const struct vop_reg reg, uint32_t v)
	1010	+{
	1011	+ uint32_t offset = reg->offset;
	1012	+ uint32_t cached_val = vop2->regsbak[offset >> 2];
	1013	+
	1014	+ v = (cached_val & ~(reg->mask << reg->shift)) \| ((v & reg->mask) << reg->shift);
	1015	+ writel(v, vop2->regs + offset);
804	1016	}
805	1017
806	1018	static inline void vop2_mask_write(struct vop2 *vop2, uint32_t offset,
..	..	@@ -881,7 +1093,7 @@
881	1093	}
882	1094	}
883	1095
884		-void vop2_standby(struct drm_crtc *crtc, bool standby)
	1096	+static void vop2_crtc_standby(struct drm_crtc *crtc, bool standby)
885	1097	{
886	1098	struct vop2_video_port *vp = to_vop2_video_port(crtc);
887	1099	struct vop2 *vop2 = vp->vop2;
..	..	@@ -893,7 +1105,6 @@
893	1105	VOP_MODULE_SET(vop2, vp, standby, 0);
894	1106	}
895	1107	}
896		-EXPORT_SYMBOL(vop2_standby);
897	1108
898	1109	static inline const struct vop2_win_regs vop2_get_win_regs(struct vop2_win win,
899	1110	const struct vop_reg *reg)
..	..	@@ -939,6 +1150,32 @@
939	1150	return NULL;
940	1151	}
941	1152
	1153	+static struct vop2_power_domain vop2_find_pd_by_id(struct vop2 vop2, uint8_t id)
	1154	+{
	1155	+ struct vop2_power_domain pd, n;
	1156	+
	1157	+ list_for_each_entry_safe(pd, n, &vop2->pd_list_head, list) {
	1158	+ if (pd->data->id == id)
	1159	+ return pd;
	1160	+ }
	1161	+
	1162	+ return NULL;
	1163	+}
	1164	+
	1165	+static const struct vop2_connector_if_data vop2_find_connector_if_data(struct vop2 vop2, int id)
	1166	+{
	1167	+ const struct vop2_connector_if_data *if_data;
	1168	+ int i;
	1169	+
	1170	+ for (i = 0; i < vop2->data->nr_conns; i++) {
	1171	+ if_data = &vop2->data->conn[i];
	1172	+ if (if_data->id == id)
	1173	+ return if_data;
	1174	+ }
	1175	+
	1176	+ return NULL;
	1177	+}
	1178	+
942	1179	static struct drm_crtc vop2_find_crtc_by_plane_mask(struct vop2 vop2, uint8_t phys_id)
943	1180	{
944	1181	struct vop2_video_port *vp;
..	..	@@ -947,10 +1184,28 @@
947	1184	for (i = 0; i < vop2->data->nr_vps; i++) {
948	1185	vp = &vop2->vps[i];
949	1186	if (vp->plane_mask & BIT(phys_id))
950		- return &vp->crtc;
	1187	+ return &vp->rockchip_crtc.crtc;
951	1188	}
952	1189
953	1190	return NULL;
	1191	+}
	1192	+
	1193	+static int vop2_clk_reset(struct reset_control *rstc)
	1194	+{
	1195	+ int ret;
	1196	+
	1197	+ if (!rstc)
	1198	+ return 0;
	1199	+
	1200	+ ret = reset_control_assert(rstc);
	1201	+ if (ret < 0)
	1202	+ DRM_WARN("failed to assert reset\n");
	1203	+ udelay(10);
	1204	+ ret = reset_control_deassert(rstc);
	1205	+ if (ret < 0)
	1206	+ DRM_WARN("failed to deassert reset\n");
	1207	+
	1208	+ return ret;
954	1209	}
955	1210
956	1211	static void vop2_load_hdr2sdr_table(struct vop2_video_port *vp)
..	..	@@ -1167,7 +1422,7 @@
1167	1422	done_bits &= ~BIT(vp->id);
1168	1423	vp_id = ffs(done_bits) - 1;
1169	1424	done_vp = &vop2->vps[vp_id];
1170		- adjusted_mode = &done_vp->crtc.state->adjusted_mode;
	1425	+ adjusted_mode = &done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1171	1426	vcnt = vop2_read_vcnt(done_vp);
1172	1427	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1173	1428	vcnt >>= 1;
..	..	@@ -1188,7 +1443,7 @@
1188	1443
1189	1444	first_vp_id = ffs(done_bits) - 1;
1190	1445	first_done_vp = &vop2->vps[first_vp_id];
1191		- first_mode = &first_done_vp->crtc.state->adjusted_mode;
	1446	+ first_mode = &first_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1192	1447	/* set last 1/8 frame time as safe section */
1193	1448	vrefresh = drm_mode_vrefresh(first_mode);
1194	1449	if (!vrefresh) {
..	..	@@ -1200,7 +1455,7 @@
1200	1455	done_bits &= ~BIT(first_vp_id);
1201	1456	second_vp_id = ffs(done_bits) - 1;
1202	1457	second_done_vp = &vop2->vps[second_vp_id];
1203		- second_mode = &second_done_vp->crtc.state->adjusted_mode;
	1458	+ second_mode = &second_done_vp->rockchip_crtc.crtc.state->adjusted_mode;
1204	1459	/* set last 1/8 frame time as safe section */
1205	1460	vrefresh = drm_mode_vrefresh(second_mode);
1206	1461	if (!vrefresh) {
..	..	@@ -1245,6 +1500,26 @@
1245	1500	return done_bits;
1246	1501	}
1247	1502
	1503	+static inline void rk3588_vop2_dsc_cfg_done(struct drm_crtc *crtc)
	1504	+{
	1505	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1506	+ struct vop2 *vop2 = vp->vop2;
	1507	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1508	+ struct vop2_dsc *dsc = &vop2->dscs[vcstate->dsc_id];
	1509	+
	1510	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	1511	+ dsc = &vop2->dscs[0];
	1512	+ if (vcstate->dsc_enable)
	1513	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1514	+ dsc = &vop2->dscs[1];
	1515	+ if (vcstate->dsc_enable)
	1516	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1517	+ } else {
	1518	+ if (vcstate->dsc_enable)
	1519	+ VOP_MODULE_SET(vop2, dsc, dsc_cfg_done, 1);
	1520	+ }
	1521	+}
	1522	+
1248	1523	static inline void rk3568_vop2_cfg_done(struct drm_crtc *crtc)
1249	1524	{
1250	1525	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -1279,6 +1554,9 @@
1279	1554	* This is rather low probability for miss some done bit.
1280	1555	*/
1281	1556	val \|= vop2_readl(vop2, RK3568_REG_CFG_DONE) & 0x7;
	1557	+
	1558	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
	1559	+
1282	1560	vop2_writel(vop2, 0, val);
1283	1561
1284	1562	/**
..	..	@@ -1295,10 +1573,16 @@
1295	1573	static inline void rk3588_vop2_cfg_done(struct drm_crtc *crtc)
1296	1574	{
1297	1575	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	1576	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	1577	+ const struct vop2_video_port_data *vp_data = &vp->vop2->data->vp[vp->id];
1298	1578	struct vop2 *vop2 = vp->vop2;
1299	1579	uint32_t val;
1300	1580
1301	1581	val = RK3568_VOP2_GLB_CFG_DONE_EN \| BIT(vp->id) \| (BIT(vp->id) << 16);
	1582	+ if (vcstate->splice_mode)
	1583	+ val \|= BIT(vp_data->splice_vp_id) \| (BIT(vp_data->splice_vp_id) << 16);
	1584	+
	1585	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_CFG_DONE, "cfg_done: 0x%x\n", val);
1302	1586
1303	1587	vop2_writel(vop2, 0, val);
1304	1588	}
..	..	@@ -1320,6 +1604,7 @@
1320	1604	} else {
1321	1605	vop2_writel(vop2, 0, val);
1322	1606	}
	1607	+
1323	1608	}
1324	1609
1325	1610	static inline void vop2_cfg_done(struct drm_crtc *crtc)
..	..	@@ -1331,6 +1616,178 @@
1331	1616	return rk3568_vop2_cfg_done(crtc);
1332	1617	else
1333	1618	return rk3588_vop2_cfg_done(crtc);
	1619	+}
	1620	+
	1621	+/*
	1622	+ * A PD can power off by vsync when it's module attached to
	1623	+ * a activated VP.
	1624	+ */
	1625	+static uint32_t vop2_power_domain_can_off_by_vsync(struct vop2_power_domain *pd)
	1626	+{
	1627	+ struct vop2 *vop2 = pd->vop2;
	1628	+
	1629	+ if (vop2->active_vp_mask & pd->vp_mask)
	1630	+ return true;
	1631	+ else
	1632	+ return false;
	1633	+}
	1634	+
	1635	+/*
	1636	+ * Read VOP internal power domain on/off status.
	1637	+ * We should query BISR_STS register in PMU for
	1638	+ * power up/down status when memory repair is enabled.
	1639	+ * Return value: 1 for power on, 0 for power off;
	1640	+ */
	1641	+static uint32_t vop2_power_domain_status(struct vop2_power_domain *pd)
	1642	+{
	1643	+ struct vop2 *vop2 = pd->vop2;
	1644	+
	1645	+ if (vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->bisr_en_status))
	1646	+ return vop2_read_grf_reg(vop2->sys_pmu, &pd->data->regs->pmu_status);
	1647	+ else
	1648	+ return vop2_read_reg(vop2, 0, &pd->data->regs->status) ? 0 : 1;
	1649	+}
	1650	+
	1651	+static void vop2_wait_power_domain_off(struct vop2_power_domain *pd)
	1652	+{
	1653	+ struct vop2 *vop2 = pd->vop2;
	1654	+ int val;
	1655	+ int ret;
	1656	+
	1657	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, !val, 0, 50 * 1000);
	1658	+
	1659	+ if (ret)
	1660	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d off timeout power_ctrl: 0x%x\n",
	1661	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1662	+}
	1663	+
	1664	+static void vop2_wait_power_domain_on(struct vop2_power_domain *pd)
	1665	+{
	1666	+ struct vop2 *vop2 = pd->vop2;
	1667	+ int val;
	1668	+ int ret;
	1669	+
	1670	+ ret = readx_poll_timeout_atomic(vop2_power_domain_status, pd, val, val, 0, 50 * 1000);
	1671	+ if (ret)
	1672	+ DRM_DEV_ERROR(vop2->dev, "wait pd%d on timeout power_ctrl: 0x%x\n",
	1673	+ ffs(pd->data->id) - 1, vop2_readl(vop2, 0x34));
	1674	+}
	1675	+
	1676	+/*
	1677	+ * Power domain on take effect immediately
	1678	+ */
	1679	+static void vop2_power_domain_on(struct vop2_power_domain *pd)
	1680	+{
	1681	+ struct vop2 *vop2 = pd->vop2;
	1682	+
	1683	+ if (!pd->on) {
	1684	+ dev_dbg(vop2->dev, "pd%d on\n", ffs(pd->data->id) - 1);
	1685	+ vop2_wait_power_domain_off(pd);
	1686	+ VOP_MODULE_SET(vop2, pd->data, pd, 0);
	1687	+ vop2_wait_power_domain_on(pd);
	1688	+ pd->on = true;
	1689	+ }
	1690	+}
	1691	+
	1692	+/*
	1693	+ * Power domain off take effect by vsync.
	1694	+ */
	1695	+static void vop2_power_domain_off(struct vop2_power_domain *pd)
	1696	+{
	1697	+ struct vop2 *vop2 = pd->vop2;
	1698	+
	1699	+ dev_dbg(vop2->dev, "pd%d off\n", ffs(pd->data->id) - 1);
	1700	+ pd->on = false;
	1701	+ VOP_MODULE_SET(vop2, pd->data, pd, 1);
	1702	+}
	1703	+
	1704	+static void vop2_power_domain_get(struct vop2_power_domain *pd)
	1705	+{
	1706	+ if (pd->parent)
	1707	+ vop2_power_domain_get(pd->parent);
	1708	+
	1709	+ spin_lock(&pd->lock);
	1710	+ if (pd->ref_count == 0) {
	1711	+ if (pd->vop2->data->delayed_pd)
	1712	+ cancel_delayed_work(&pd->power_off_work);
	1713	+ vop2_power_domain_on(pd);
	1714	+ }
	1715	+ pd->ref_count++;
	1716	+ spin_unlock(&pd->lock);
	1717	+}
	1718	+
	1719	+static void vop2_power_domain_put(struct vop2_power_domain *pd)
	1720	+{
	1721	+ spin_lock(&pd->lock);
	1722	+
	1723	+ /*
	1724	+ * For a nested power domain(PD_Cluster0 is the parent of PD_CLuster1/2/3)
	1725	+ * the parent power domain must be enabled before child power domain
	1726	+ * is on.
	1727	+ *
	1728	+ * So we may met this condition: Cluster0 is not on a activated VP,
	1729	+ * but PD_Cluster0 must enabled as one of the child PD_CLUSTER1/2/3 is enabled.
	1730	+ * when all child PD is disabled, we want disable the parent
	1731	+ * PD(PD_CLUSTER0), but as module CLUSTER0 is not attcthed on a activated VP,
	1732	+ * the turn off operation(which is take effect by vsync) will never take effect.
	1733	+ * so we will see a "wait pd0 off timeout" log when we turn on PD_CLUSTER0 next time.
	1734	+ *
	1735	+ * So we have a check here
	1736	+ */
	1737	+ if (--pd->ref_count == 0 && vop2_power_domain_can_off_by_vsync(pd)) {
	1738	+ if (pd->vop2->data->delayed_pd)
	1739	+ schedule_delayed_work(&pd->power_off_work, msecs_to_jiffies(2500));
	1740	+ else
	1741	+ vop2_power_domain_off(pd);
	1742	+ }
	1743	+
	1744	+ spin_unlock(&pd->lock);
	1745	+ if (pd->parent)
	1746	+ vop2_power_domain_put(pd->parent);
	1747	+}
	1748	+
	1749	+/*
	1750	+ * Called if the pd ref_count reach 0 after 2.5
	1751	+ * seconds.
	1752	+ */
	1753	+static void vop2_power_domain_off_work(struct work_struct *work)
	1754	+{
	1755	+ struct vop2_power_domain *pd;
	1756	+
	1757	+ pd = container_of(to_delayed_work(work), struct vop2_power_domain, power_off_work);
	1758	+
	1759	+ spin_lock(&pd->lock);
	1760	+ if (pd->ref_count == 0)
	1761	+ vop2_power_domain_off(pd);
	1762	+ spin_unlock(&pd->lock);
	1763	+}
	1764	+
	1765	+static void vop2_win_enable(struct vop2_win *win)
	1766	+{
	1767	+ /*
	1768	+ * a win such as cursor update by async:
	1769	+ * first frame enable win pd, enable win, return without wait vsync
	1770	+ * second frame come, but the first frame may still not enabled
	1771	+ * in this case, the win pd is turn on by fist frame, so we don't
	1772	+ * need get pd again.
	1773	+ *
	1774	+ * another case:
	1775	+ * first frame: disable win, disable pd, return without wait vsync
	1776	+ * second frame come very soon, the previous win disable may still not
	1777	+ * take effect, but the pd is disable in progress, we should do pd_get
	1778	+ * at this situation.
	1779	+ *
	1780	+ * check the backup register for previous enable operation.
	1781	+ */
	1782	+ if (!VOP_WIN_GET_REG_BAK(win->vop2, win, enable)) {
	1783	+ if (win->pd) {
	1784	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1785	+ return;
	1786	+
	1787	+ vop2_power_domain_get(win->pd);
	1788	+ win->pd->vp_mask \|= win->vp_mask;
	1789	+ }
	1790	+ }
1334	1791	}
1335	1792
1336	1793	static void vop2_win_multi_area_disable(struct vop2_win *parent)
..	..	@@ -1346,31 +1803,63 @@
1346	1803	}
1347	1804	}
1348	1805
1349		-static void vop2_win_disable(struct vop2_win *win)
	1806	+static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win)
1350	1807	{
1351	1808	struct vop2 *vop2 = win->vop2;
1352	1809
1353		- VOP_WIN_SET(vop2, win, enable, 0);
1354		- if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
1355		- struct vop2_win *sub_win;
1356		- int i = 0;
1357		-
1358		- for (i = 0; i < vop2->registered_num_wins; i++) {
1359		- sub_win = &vop2->win[i];
1360		-
1361		- if ((sub_win->phys_id == win->phys_id) &&
1362		- (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
1363		- VOP_WIN_SET(vop2, sub_win, enable, 0);
1364		- }
1365		-
1366		- VOP_CLUSTER_SET(vop2, win, enable, 0);
	1810	+ /* Disable the right splice win */
	1811	+ if (win->splice_win && !skip_splice_win) {
	1812	+ vop2_win_disable(win->splice_win, false);
	1813	+ win->splice_win = NULL;
1367	1814	}
1368	1815
1369		- /*
1370		- * disable all other multi area win if we want disable area0 here
1371		- */
1372		- if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
1373		- vop2_win_multi_area_disable(win);
	1816	+ if (VOP_WIN_GET(vop2, win, enable) \|\| VOP_WIN_GET_REG_BAK(vop2, win, enable)) {
	1817	+ VOP_WIN_SET(vop2, win, enable, 0);
	1818	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN) {
	1819	+ struct vop2_win *sub_win;
	1820	+ int i = 0;
	1821	+
	1822	+ for (i = 0; i < vop2->registered_num_wins; i++) {
	1823	+ sub_win = &vop2->win[i];
	1824	+
	1825	+ if ((sub_win->phys_id == win->phys_id) &&
	1826	+ (sub_win->feature & WIN_FEATURE_CLUSTER_SUB))
	1827	+ VOP_WIN_SET(vop2, sub_win, enable, 0);
	1828	+ }
	1829	+
	1830	+ VOP_CLUSTER_SET(vop2, win, enable, 0);
	1831	+ }
	1832	+
	1833	+ /*
	1834	+ * disable all other multi area win if we want disable area0 here
	1835	+ */
	1836	+ if (!win->parent && (win->feature & WIN_FEATURE_MULTI_AREA))
	1837	+ vop2_win_multi_area_disable(win);
	1838	+
	1839	+ if (win->pd) {
	1840	+
	1841	+ /*
	1842	+ * Don't dynamic turn on/off PD_ESMART.
	1843	+ * (1) There is a design issue for PD_EMSART when attached
	1844	+ * on VP1/2/3, we found it will trigger POST_BUF_EMPTY irq at vp0
	1845	+ * in splice mode.
	1846	+ * (2) PD_ESMART will be closed at esmart layers attathed on VPs
	1847	+ * config done + FS, but different VP FS time is different, this
	1848	+ * maybe lead to PD_ESMART closed at wrong time and display error.
	1849	+ * (3) PD_ESMART power up maybe have 4 us delay, this will lead to POST_BUF_EMPTY.
	1850	+ */
	1851	+ if (win->pd->data->id == VOP2_PD_ESMART)
	1852	+ return;
	1853	+
	1854	+ vop2_power_domain_put(win->pd);
	1855	+ win->pd->vp_mask &= ~win->vp_mask;
	1856	+ }
	1857	+ }
	1858	+
	1859	+ if (win->left_win && win->splice_mode_right) {
	1860	+ win->left_win = NULL;
	1861	+ win->splice_mode_right = false;
	1862	+ }
1374	1863	}
1375	1864
1376	1865	static inline void vop2_write_lut(struct vop2 *vop2, uint32_t offset, uint32_t v)
..	..	@@ -1386,6 +1875,11 @@
1386	1875	static enum vop2_data_format vop2_convert_format(uint32_t format)
1387	1876	{
1388	1877	switch (format) {
	1878	+ case DRM_FORMAT_XRGB2101010:
	1879	+ case DRM_FORMAT_ARGB2101010:
	1880	+ case DRM_FORMAT_XBGR2101010:
	1881	+ case DRM_FORMAT_ABGR2101010:
	1882	+ return VOP2_FMT_XRGB101010;
1389	1883	case DRM_FORMAT_XRGB8888:
1390	1884	case DRM_FORMAT_ARGB8888:
1391	1885	case DRM_FORMAT_XBGR8888:
..	..	@@ -1398,16 +1892,22 @@
1398	1892	case DRM_FORMAT_BGR565:
1399	1893	return VOP2_FMT_RGB565;
1400	1894	case DRM_FORMAT_NV12:
	1895	+ case DRM_FORMAT_NV21:
	1896	+ case DRM_FORMAT_YUV420_8BIT:
1401	1897	return VOP2_FMT_YUV420SP;
1402		- case DRM_FORMAT_NV12_10:
	1898	+ case DRM_FORMAT_NV15:
	1899	+ case DRM_FORMAT_YUV420_10BIT:
1403	1900	return VOP2_FMT_YUV420SP_10;
1404	1901	case DRM_FORMAT_NV16:
	1902	+ case DRM_FORMAT_NV61:
1405	1903	return VOP2_FMT_YUV422SP;
1406		- case DRM_FORMAT_NV16_10:
	1904	+ case DRM_FORMAT_NV20:
	1905	+ case DRM_FORMAT_Y210:
1407	1906	return VOP2_FMT_YUV422SP_10;
1408	1907	case DRM_FORMAT_NV24:
	1908	+ case DRM_FORMAT_NV42:
1409	1909	return VOP2_FMT_YUV444SP;
1410		- case DRM_FORMAT_NV24_10:
	1910	+ case DRM_FORMAT_NV30:
1411	1911	return VOP2_FMT_YUV444SP_10;
1412	1912	case DRM_FORMAT_YUYV:
1413	1913	case DRM_FORMAT_YVYU:
..	..	@@ -1424,6 +1924,11 @@
1424	1924	static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format)
1425	1925	{
1426	1926	switch (format) {
	1927	+ case DRM_FORMAT_XRGB2101010:
	1928	+ case DRM_FORMAT_ARGB2101010:
	1929	+ case DRM_FORMAT_XBGR2101010:
	1930	+ case DRM_FORMAT_ABGR2101010:
	1931	+ return VOP2_AFBC_FMT_ARGB2101010;
1427	1932	case DRM_FORMAT_XRGB8888:
1428	1933	case DRM_FORMAT_ARGB8888:
1429	1934	case DRM_FORMAT_XBGR8888:
..	..	@@ -1435,14 +1940,16 @@
1435	1940	case DRM_FORMAT_RGB565:
1436	1941	case DRM_FORMAT_BGR565:
1437	1942	return VOP2_AFBC_FMT_RGB565;
1438		- case DRM_FORMAT_NV12:
	1943	+ case DRM_FORMAT_YUV420_8BIT:
1439	1944	return VOP2_AFBC_FMT_YUV420;
1440		- case DRM_FORMAT_NV12_10:
	1945	+ case DRM_FORMAT_YUV420_10BIT:
1441	1946	return VOP2_AFBC_FMT_YUV420_10BIT;
1442		- case DRM_FORMAT_NV16:
	1947	+ case DRM_FORMAT_YVYU:
1443	1948	case DRM_FORMAT_YUYV:
	1949	+ case DRM_FORMAT_VYUY:
	1950	+ case DRM_FORMAT_UYVY:
1444	1951	return VOP2_AFBC_FMT_YUV422;
1445		- case DRM_FORMAT_NV16_10:
	1952	+ case DRM_FORMAT_Y210:
1446	1953	return VOP2_AFBC_FMT_YUV422_10BIT;
1447	1954
1448	1955	/* either of the below should not be reachable */
..	..	@@ -1466,11 +1973,11 @@
1466	1973	case DRM_FORMAT_NV24:
1467	1974	case DRM_FORMAT_NV42:
1468	1975	return VOP2_TILED_8X8_FMT_YUV444SP;
1469		- case DRM_FORMAT_NV12_10:
	1976	+ case DRM_FORMAT_NV15:
1470	1977	return VOP2_TILED_8X8_FMT_YUV420SP_10;
1471		- case DRM_FORMAT_NV16_10:
	1978	+ case DRM_FORMAT_NV20:
1472	1979	return VOP2_TILED_8X8_FMT_YUV422SP_10;
1473		- case DRM_FORMAT_NV24_10:
	1980	+ case DRM_FORMAT_NV30:
1474	1981	return VOP2_TILED_8X8_FMT_YUV444SP_10;
1475	1982	default:
1476	1983	DRM_WARN_ONCE("unsupported tiled format[%08x]\n", format);
..	..	@@ -1495,13 +2002,13 @@
1495	2002	case DRM_FORMAT_NV42:
1496	2003	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1497	2004	VOP3_TILED_8X8_FMT_YUV444SP : VOP3_TILED_4X4_FMT_YUV444SP;
1498		- case DRM_FORMAT_NV12_10:
	2005	+ case DRM_FORMAT_NV15:
1499	2006	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1500	2007	VOP3_TILED_8X8_FMT_YUV420SP_10 : VOP3_TILED_4X4_FMT_YUV420SP_10;
1501		- case DRM_FORMAT_NV16_10:
	2008	+ case DRM_FORMAT_NV20:
1502	2009	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1503	2010	VOP3_TILED_8X8_FMT_YUV422SP_10 : VOP3_TILED_4X4_FMT_YUV422SP_10;
1504		- case DRM_FORMAT_NV24_10:
	2011	+ case DRM_FORMAT_NV30:
1505	2012	return tile_mode == ROCKCHIP_TILED_BLOCK_SIZE_8x8 ?
1506	2013	VOP3_TILED_8X8_FMT_YUV444SP_10 : VOP3_TILED_4X4_FMT_YUV444SP_10;
1507	2014	default:
..	..	@@ -1540,6 +2047,8 @@
1540	2047	static bool vop2_win_rb_swap(uint32_t format)
1541	2048	{
1542	2049	switch (format) {
	2050	+ case DRM_FORMAT_XBGR2101010:
	2051	+ case DRM_FORMAT_ABGR2101010:
1543	2052	case DRM_FORMAT_XBGR8888:
1544	2053	case DRM_FORMAT_ABGR8888:
1545	2054	case DRM_FORMAT_BGR888:
..	..	@@ -1554,7 +2063,7 @@
1554	2063	{
1555	2064	switch (format) {
1556	2065	case DRM_FORMAT_NV24:
1557		- case DRM_FORMAT_NV24_10:
	2066	+ case DRM_FORMAT_NV30:
1558	2067	return true;
1559	2068	default:
1560	2069	return false;
..	..	@@ -1567,8 +2076,9 @@
1567	2076	case DRM_FORMAT_NV12:
1568	2077	case DRM_FORMAT_NV16:
1569	2078	case DRM_FORMAT_YUYV:
1570		- case DRM_FORMAT_NV12_10:
1571		- case DRM_FORMAT_NV16_10:
	2079	+ case DRM_FORMAT_Y210:
	2080	+ case DRM_FORMAT_YUV420_8BIT:
	2081	+ case DRM_FORMAT_YUV420_10BIT:
1572	2082	return true;
1573	2083	default:
1574	2084	return false;
..	..	@@ -1581,9 +2091,9 @@
1581	2091	case DRM_FORMAT_NV12:
1582	2092	case DRM_FORMAT_NV16:
1583	2093	case DRM_FORMAT_NV24:
1584		- case DRM_FORMAT_NV12_10:
1585		- case DRM_FORMAT_NV16_10:
1586		- case DRM_FORMAT_NV24_10:
	2094	+ case DRM_FORMAT_NV15:
	2095	+ case DRM_FORMAT_NV20:
	2096	+ case DRM_FORMAT_NV30:
1587	2097	case DRM_FORMAT_YUYV:
1588	2098	case DRM_FORMAT_UYVY:
1589	2099	return true;
..	..	@@ -1627,6 +2137,19 @@
1627	2137	return false;
1628	2138	}
1629	2139
	2140	+static bool vop3_output_rb_swap(uint32_t bus_format, uint32_t output_mode)
	2141	+{
	2142	+ /*
	2143	+ * The default component order of serial rgb3x8 formats
	2144	+ * is BGR. So it is needed to enable RB swap.
	2145	+ */
	2146	+ if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 \|\|
	2147	+ bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8)
	2148	+ return true;
	2149	+ else
	2150	+ return false;
	2151	+}
	2152	+
1630	2153	static bool vop2_output_yc_swap(uint32_t bus_format)
1631	2154	{
1632	2155	switch (bus_format) {
..	..	@@ -1645,6 +2168,7 @@
1645	2168	switch (bus_format) {
1646	2169	case MEDIA_BUS_FMT_YUV8_1X24:
1647	2170	case MEDIA_BUS_FMT_YUV10_1X30:
	2171	+ case MEDIA_BUS_FMT_YUYV10_1X20:
1648	2172	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1649	2173	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1650	2174	case MEDIA_BUS_FMT_YUYV8_2X8:
..	..	@@ -1740,6 +2264,15 @@
1740	2264	return (win->feature & WIN_FEATURE_CLUSTER_SUB);
1741	2265	}
1742	2266
	2267	+static inline bool vop2_has_feature(struct vop2 *vop2, uint64_t feature)
	2268	+{
	2269	+ return (vop2->data->feature & feature);
	2270	+}
	2271	+
	2272	+/*
	2273	+ * 0: Full mode, 16 lines for one tail
	2274	+ * 1: half block mode
	2275	+ */
1743	2276	static int vop2_afbc_half_block_enable(struct vop2_plane_state *vpstate)
1744	2277	{
1745	2278	if (vpstate->rotate_270_en \|\| vpstate->rotate_90_en)
..	..	@@ -1748,11 +2281,15 @@
1748	2281	return 1;
1749	2282	}
1750	2283
1751		-static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate)
	2284	+/*
	2285	+ * @xoffset: the src x offset of the right win in splice mode, other wise it
	2286	+ * must be zero.
	2287	+ */
	2288	+static uint32_t vop2_afbc_transform_offset(struct vop2_plane_state *vpstate, int xoffset)
1752	2289	{
1753	2290	struct drm_rect *src = &vpstate->src;
1754	2291	struct drm_framebuffer *fb = vpstate->base.fb;
1755		- uint32_t bpp = fb->format->bpp[0];
	2292	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
1756	2293	uint32_t vir_width = (fb->pitches[0] << 3) / (bpp ? bpp : 1);
1757	2294	uint32_t width = drm_rect_width(src) >> 16;
1758	2295	uint32_t height = drm_rect_height(src) >> 16;
..	..	@@ -1768,6 +2305,7 @@
1768	2305	uint8_t top_crop_line_num = 0;
1769	2306	uint8_t bottom_crop_line_num = 0;
1770	2307
	2308	+ act_xoffset += xoffset;
1771	2309	/* 16 pixel align */
1772	2310	if (height & 0xf)
1773	2311	align16_crop = 16 - (height & 0xf);
..	..	@@ -2011,12 +2549,12 @@
2011	2549	{
2012	2550	const struct vop2_data *vop2_data = vop2->data;
2013	2551	const struct vop2_win_data *win_data = &vop2_data->win[win->win_id];
2014		- const struct drm_format_info *info;
2015	2552	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
2016	2553	struct drm_framebuffer *fb = pstate->fb;
2017	2554	uint32_t pixel_format = fb->format->format;
2018		- int hsub = drm_format_horz_chroma_subsampling(pixel_format);
2019		- int vsub = drm_format_vert_chroma_subsampling(pixel_format);
	2555	+ const struct drm_format_info *info = drm_format_info(pixel_format);
	2556	+ uint8_t hsub = info->hsub;
	2557	+ uint8_t vsub = info->vsub;
2020	2558	uint16_t cbcr_src_w = src_w / hsub;
2021	2559	uint16_t cbcr_src_h = src_h / vsub;
2022	2560	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
..	..	@@ -2025,8 +2563,6 @@
2025	2563	uint8_t xgt2 = 0, xgt4 = 0;
2026	2564	uint8_t ygt2 = 0, ygt4 = 0;
2027	2565	uint32_t val;
2028		-
2029		- info = drm_format_info(pixel_format);
2030	2566
2031	2567	if (is_vop3(vop2)) {
2032	2568	if (src_w >= (4 * dst_w)) {
..	..	@@ -2246,7 +2782,7 @@
2246	2782	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
2247	2783	win = vop2_find_win_by_phys_id(vop2, phys_id);
2248	2784	need_wait_win_disabled \|= VOP_WIN_GET(vop2, win, enable);
2249		- vop2_win_disable(win);
	2785	+ vop2_win_disable(win, false);
2250	2786	}
2251	2787
2252	2788	if (need_wait_win_disabled) {
..	..	@@ -2295,7 +2831,7 @@
2295	2831	struct vop2_plane_state *vpstate)
2296	2832	{
2297	2833	struct drm_plane_state *pstate = &vpstate->base;
2298		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
	2834	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->rockchip_crtc.crtc.state);
2299	2835	int is_input_yuv = pstate->fb->format->is_yuv;
2300	2836	int is_output_yuv = vcstate->yuv_overlay;
2301	2837	int input_csc = vpstate->color_space;
..	..	@@ -2480,8 +3016,14 @@
2480	3016	if (ret < 0)
2481	3017	goto err_disable_hclk;
2482	3018
	3019	+ ret = clk_enable(vop2->pclk);
	3020	+ if (ret < 0)
	3021	+ goto err_disable_aclk;
	3022	+
2483	3023	return 0;
2484	3024
	3025	+err_disable_aclk:
	3026	+ clk_disable(vop2->aclk);
2485	3027	err_disable_hclk:
2486	3028	clk_disable(vop2->hclk);
2487	3029	return ret;
..	..	@@ -2489,6 +3031,7 @@
2489	3031
2490	3032	static void vop2_core_clks_disable(struct vop2 *vop2)
2491	3033	{
	3034	+ clk_disable(vop2->pclk);
2492	3035	clk_disable(vop2->aclk);
2493	3036	clk_disable(vop2->hclk);
2494	3037	}
..	..	@@ -2599,6 +3142,18 @@
2599	3142	return MODE_OK;
2600	3143	}
2601	3144
	3145	+static inline bool
	3146	+vop2_wb_connector_changed_only(struct drm_crtc_state cstate, struct drm_connector conn)
	3147	+{
	3148	+ struct drm_crtc_state *old_state;
	3149	+ u32 changed_connectors;
	3150	+
	3151	+ old_state = drm_atomic_get_old_crtc_state(cstate->state, cstate->crtc);
	3152	+ changed_connectors = cstate->connector_mask ^ old_state->connector_mask;
	3153	+
	3154	+ return BIT(drm_connector_index(conn)) == changed_connectors;
	3155	+}
	3156	+
2602	3157	static int vop2_wb_encoder_atomic_check(struct drm_encoder *encoder,
2603	3158	struct drm_crtc_state *cstate,
2604	3159	struct drm_connector_state *conn_state)
..	..	@@ -2607,7 +3162,18 @@
2607	3162	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
2608	3163	struct vop2_video_port *vp = to_vop2_video_port(cstate->crtc);
2609	3164	struct drm_framebuffer *fb;
	3165	+ struct drm_gem_object obj, uv_obj;
	3166	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
2610	3167
	3168	+ /*
	3169	+ * No need for a full modested when the only connector changed is the
	3170	+ * writeback connector.
	3171	+ */
	3172	+ if (cstate->connectors_changed &&
	3173	+ vop2_wb_connector_changed_only(cstate, conn_state->connector)) {
	3174	+ cstate->connectors_changed = false;
	3175	+ DRM_DEBUG("VP%d force change connectors_changed to false when only wb changed\n", vp->id);
	3176	+ }
2611	3177	if (!conn_state->writeback_job \|\| !conn_state->writeback_job->fb)
2612	3178	return 0;
2613	3179
..	..	@@ -2620,7 +3186,7 @@
2620	3186	}
2621	3187
2622	3188	if ((fb->width > cstate->mode.hdisplay) \|\|
2623		- ((fb->height != cstate->mode.vdisplay) &&
	3189	+ ((fb->height < cstate->mode.vdisplay) &&
2624	3190	(fb->height != (cstate->mode.vdisplay >> 1)))) {
2625	3191	DRM_DEBUG_KMS("Invalid framebuffer size %ux%u, Only support x scale down and 1/2 y scale down\n",
2626	3192	fb->width, fb->height);
..	..	@@ -2628,7 +3194,7 @@
2628	3194	}
2629	3195
2630	3196	wb_state->scale_x_factor = vop2_scale_factor(SCALE_DOWN, VOP2_SCALE_DOWN_BIL,
2631		- cstate->mode.hdisplay, fb->width);
	3197	+ cstate->mode.hdisplay, fb->width);
2632	3198	wb_state->scale_x_en = (fb->width < cstate->mode.hdisplay) ? 1 : 0;
2633	3199	wb_state->scale_y_en = (fb->height < cstate->mode.vdisplay) ? 1 : 0;
2634	3200
..	..	@@ -2643,15 +3209,15 @@
2643	3209	}
2644	3210
2645	3211	wb_state->vp_id = vp->id;
2646		- wb_state->yrgb_addr = rockchip_fb_get_dma_addr(fb, 0);
2647		- /*
2648		- * uv address must follow yrgb address without gap.
2649		- * the fb->offsets is include stride, so we should
2650		- * not use it.
2651		- */
	3212	+ obj = fb->obj[0];
	3213	+ rk_obj = to_rockchip_obj(obj);
	3214	+ wb_state->yrgb_addr = rk_obj->dma_addr + fb->offsets[0];
	3215	+
2652	3216	if (fb->format->is_yuv) {
2653		- wb_state->uv_addr = wb_state->yrgb_addr;
2654		- wb_state->uv_addr += DIV_ROUND_UP(fb->width * fb->format->bpp[0], 8) * fb->height;
	3217	+ uv_obj = fb->obj[1];
	3218	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	3219	+
	3220	+ wb_state->uv_addr = rk_uv_obj->dma_addr + fb->offsets[1];
2655	3221	}
2656	3222
2657	3223	return 0;
..	..	@@ -2741,10 +3307,12 @@
2741	3307	if (conn_state->writeback_job && conn_state->writeback_job->fb) {
2742	3308	struct drm_framebuffer *fb = conn_state->writeback_job->fb;
2743	3309
2744		- DRM_DEV_DEBUG(vop2->dev, "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
2745		- fb->width, fb->height, wb_state->format, fb->pitches[0], &wb_state->yrgb_addr);
	3310	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_WB,
	3311	+ "Enable wb %ux%u fmt: %u pitches: %d addr: %pad\n",
	3312	+ fb->width, fb->height, wb_state->format,
	3313	+ fb->pitches[0], &wb_state->yrgb_addr);
2746	3314
2747		- drm_writeback_queue_job(wb_conn, conn_state->writeback_job);
	3315	+ drm_writeback_queue_job(wb_conn, conn_state);
2748	3316	conn_state->writeback_job = NULL;
2749	3317
2750	3318	spin_lock_irqsave(&wb->job_lock, flags);
..	..	@@ -2773,6 +3341,7 @@
2773	3341	VOP_MODULE_SET(vop2, wb, r2y_en, r2y);
2774	3342	VOP_MODULE_SET(vop2, wb, enable, 1);
2775	3343	vop2_wb_irqs_enable(vop2);
	3344	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 1);
2776	3345	}
2777	3346	}
2778	3347
..	..	@@ -2797,6 +3366,7 @@
2797	3366
2798	3367	return;
2799	3368	}
	3369	+
2800	3370	spin_lock(&vop2->reg_lock);
2801	3371	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 0);
2802	3372	vop2_cfg_done(crtc);
..	..	@@ -2812,7 +3382,7 @@
2812	3382	spin_lock(&vop2->reg_lock);
2813	3383
2814	3384	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2815		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
	3385	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2816	3386	vop2_cfg_done(crtc);
2817	3387	vp->gamma_lut_active = true;
2818	3388
..	..	@@ -2833,7 +3403,7 @@
2833	3403	vop2_write_lut(vop2, i << 2, lut[i]);
2834	3404
2835	3405	VOP_MODULE_SET(vop2, vp, dsp_lut_en, 1);
2836		- VOP_MODULE_SET(vop2, vp, gamma_update_en, 1);
	3406	+ vop2_write_reg_uncached(vop2, &vp->regs->gamma_update_en, 1);
2837	3407	vp->gamma_lut_active = true;
2838	3408
2839	3409	spin_unlock(&vop2->reg_lock);
..	..	@@ -2853,7 +3423,13 @@
2853	3423	if (vop2->version == VOP_VERSION_RK3568) {
2854	3424	rk3568_crtc_load_lut(crtc);
2855	3425	} else {
2856		- rk3588_crtc_load_lut(crtc, vp->lut);
	3426	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	3427	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3428	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3429	+
	3430	+ rk3588_crtc_load_lut(&vp->rockchip_crtc.crtc, vp->lut);
	3431	+ if (vcstate->splice_mode)
	3432	+ rk3588_crtc_load_lut(&splice_vp->rockchip_crtc.crtc, vp->lut);
2857	3433	vop2_cfg_done(crtc);
2858	3434	}
2859	3435	/*
..	..	@@ -2948,9 +3524,11 @@
2948	3524	return 0;
2949	3525	}
2950	3526
	3527	+#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
2951	3528	static int vop2_crtc_atomic_cubic_lut_set(struct drm_crtc *crtc,
2952	3529	struct drm_crtc_state *old_state)
2953	3530	{
	3531	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
2954	3532	struct vop2_video_port *vp = to_vop2_video_port(crtc);
2955	3533	struct rockchip_drm_private *private = crtc->dev->dev_private;
2956	3534	struct drm_color_lut *lut = vp->cubic_lut;
..	..	@@ -3001,13 +3579,61 @@
3001	3579	*cubic_lut_kvaddr = 0;
3002	3580	}
3003	3581
	3582	+ VOP_MODULE_SET(vop2, vp, lut_dma_rid, vp->lut_dma_rid);
3004	3583	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
3005	3584	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 1);
3006	3585	VOP_MODULE_SET(vop2, vp, cubic_lut_en, 1);
3007	3586	VOP_CTRL_SET(vop2, lut_dma_en, 1);
3008	3587
	3588	+ if (vcstate->splice_mode) {
	3589	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	3590	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	3591	+
	3592	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_mst, cubic_lut_mst);
	3593	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_update_en, 1);
	3594	+ VOP_MODULE_SET(vop2, splice_vp, cubic_lut_en, 1);
	3595	+ }
	3596	+
3009	3597	return 0;
3010	3598	}
	3599	+
	3600	+static void drm_crtc_enable_cubic_lut(struct drm_crtc *crtc, unsigned int cubic_lut_size)
	3601	+{
	3602	+ struct drm_device *dev = crtc->dev;
	3603	+ struct drm_mode_config *config = &dev->mode_config;
	3604	+
	3605	+ if (cubic_lut_size) {
	3606	+ drm_object_attach_property(&crtc->base,
	3607	+ config->cubic_lut_property, 0);
	3608	+ drm_object_attach_property(&crtc->base,
	3609	+ config->cubic_lut_size_property,
	3610	+ cubic_lut_size);
	3611	+ }
	3612	+}
	3613	+
	3614	+static void vop2_cubic_lut_init(struct vop2 *vop2)
	3615	+{
	3616	+ const struct vop2_data *vop2_data = vop2->data;
	3617	+ const struct vop2_video_port_data *vp_data;
	3618	+ struct vop2_video_port *vp;
	3619	+ struct drm_crtc *crtc;
	3620	+ int i;
	3621	+
	3622	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	3623	+ vp = &vop2->vps[i];
	3624	+ crtc = &vp->rockchip_crtc.crtc;
	3625	+ if (!crtc->dev)
	3626	+ continue;
	3627	+ vp_data = &vop2_data->vp[vp->id];
	3628	+ vp->cubic_lut_len = vp_data->cubic_lut_len;
	3629	+
	3630	+ if (vp->cubic_lut_len)
	3631	+ drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
	3632	+ }
	3633	+}
	3634	+#else
	3635	+static void vop2_cubic_lut_init(struct vop2 *vop2) { }
	3636	+#endif
3011	3637
3012	3638	static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
3013	3639	{
..	..	@@ -3025,7 +3651,15 @@
3025	3651	goto err;
3026	3652	}
3027	3653
	3654	+ ret = clk_prepare_enable(vop2->pclk);
	3655	+ if (ret < 0) {
	3656	+ dev_err(vop2->dev, "failed to enable pclk - %d\n", ret);
	3657	+ goto err1;
	3658	+ }
	3659	+
3028	3660	return 0;
	3661	+err1:
	3662	+ clk_disable_unprepare(vop2->aclk);
3029	3663	err:
3030	3664	clk_disable_unprepare(vop2->hclk);
3031	3665
..	..	@@ -3142,6 +3776,18 @@
3142	3776
3143	3777	}
3144	3778
	3779	+static void rk3588_vop2_regsbak(struct vop2 *vop2)
	3780	+{
	3781	+ uint32_t *base = vop2->regs;
	3782	+ int i;
	3783	+
	3784	+ /*
	3785	+ * No need to backup DSC/GAMMA_LUT/BPP_LUT/MMU
	3786	+ */
	3787	+ for (i = 0; i < (0x2000 >> 2); i++)
	3788	+ vop2->regsbak[i] = base[i];
	3789	+}
	3790	+
3145	3791	static void vop2_initial(struct drm_crtc *crtc)
3146	3792	{
3147	3793	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3166,7 +3812,13 @@
3166	3812	if (vop2_soc_is_rk3566())
3167	3813	VOP_CTRL_SET(vop2, otp_en, 1);
3168	3814
3169		- memcpy(vop2->regsbak, vop2->regs, vop2->len);
	3815	+ /*
	3816	+ * rk3588 don't support access mmio by memcpy
	3817	+ */
	3818	+ if (vop2->version == VOP_VERSION_RK3588)
	3819	+ rk3588_vop2_regsbak(vop2);
	3820	+ else
	3821	+ memcpy(vop2->regsbak, vop2->regs, vop2->len);
3170	3822
3171	3823	VOP_MODULE_SET(vop2, wb, axi_yrgb_id, 0xd);
3172	3824	VOP_MODULE_SET(vop2, wb, axi_uv_id, 0xe);
..	..	@@ -3178,10 +3830,10 @@
3178	3830	}
3179	3831
3180	3832	/*
3181		- * This is unused and error init value for rk3528 vp1, if less of this config,
	3833	+ * This is unused and error init value for rk3528/rk3562 vp1, if less of this config,
3182	3834	* vp1 can't display normally.
3183	3835	*/
3184		- if (vop2->version == VOP_VERSION_RK3528)
	3836	+ if (vop2->version == VOP_VERSION_RK3528 \|\| vop2->version == VOP_VERSION_RK3562)
3185	3837	vop2_mask_write(vop2, 0x700, 0x3, 4, 0, 0, true);
3186	3838
3187	3839	VOP_CTRL_SET(vop2, cfg_done_en, 1);
..	..	@@ -3192,6 +3844,7 @@
3192	3844	VOP_CTRL_SET(vop2, auto_gating_en, 0);
3193	3845
3194	3846	VOP_CTRL_SET(vop2, aclk_pre_auto_gating_en, 0);
	3847	+
3195	3848	/*
3196	3849	* Register OVERLAY_LAYER_SEL and OVERLAY_PORT_SEL should take effect immediately,
3197	3850	* than windows configuration(CLUSTER/ESMART/SMART) can take effect according the
..	..	@@ -3204,9 +3857,17 @@
3204	3857	*/
3205	3858	VOP_CTRL_SET(vop2, if_ctrl_cfg_done_imd, 1);
3206	3859
	3860	+ /* Close dynamic turn on/off rk3588 PD_ESMART and keep esmart pd on when enable */
	3861	+ if (vop2->version == VOP_VERSION_RK3588) {
	3862	+ struct vop2_power_domain *esmart_pd = vop2_find_pd_by_id(vop2, VOP2_PD_ESMART);
	3863	+
	3864	+ if (vop2_power_domain_status(esmart_pd))
	3865	+ esmart_pd->on = true;
	3866	+ else
	3867	+ vop2_power_domain_on(esmart_pd);
	3868	+ }
3207	3869	vop2_layer_map_initial(vop2, current_vp_id);
3208	3870	vop2_axi_irqs_enable(vop2);
3209		-
3210	3871	vop2->is_enabled = true;
3211	3872	}
3212	3873
..	..	@@ -3220,6 +3881,93 @@
3220	3881	vp->id, ret);
3221	3882	}
3222	3883
	3884	+/*
	3885	+ * The internal PD of VOP2 on rk3588 take effect immediately
	3886	+ * for power up and take effect by vsync for power down.
	3887	+ *
	3888	+ * And the PD_CLUSTER0 is a parent PD of PD_CLUSTER1/2/3,
	3889	+ * we may have this use case:
	3890	+ * Cluster0 is attached to VP0 for HDMI output,
	3891	+ * Cluster1 is attached to VP1 for MIPI DSI,
	3892	+
	3893	+ * When we enable Cluster1 on VP1, we should enable PD_CLUSTER0 as
	3894	+ * it is the parent PD, event though HDMI is plugout, VP1 is disabled,
	3895	+ * the PD of Cluster0 should keep power on.
	3896	+
	3897	+ * When system go to suspend:
	3898	+ * (1) Power down PD of Cluster1 before VP1 standby(the power down is take
	3899	+ * effect by vsync)
	3900	+ * (2) Power down PD of Cluster0
	3901	+ *
	3902	+ * But we have problem at step (2), Cluster0 is attached to VP0. but VP0
	3903	+ * is in standby mode, as it is never used or hdmi plugout. So there is
	3904	+ * no vsync, the power down will never take effect.
	3905	+
	3906	+ * According to IC designer: We must power down all internal PD of VOP
	3907	+ * before we power down the global PD_VOP.
	3908	+
	3909	+ * So we get this workaround:
	3910	+ * If we found a VP is in standby mode when we want power down a PD is
	3911	+ * attached to it, we release the VP from standby mode, than it will
	3912	+ * run a default timing and generate vsync. Than we can power down the
	3913	+ * PD by this vsync. After all this is done, we standby the VP at last.
	3914	+ */
	3915	+static void vop2_power_domain_off_by_disabled_vp(struct vop2_power_domain *pd)
	3916	+{
	3917	+ struct vop2_video_port *vp = NULL;
	3918	+ struct vop2 *vop2 = pd->vop2;
	3919	+ struct vop2_win *win;
	3920	+ struct drm_crtc *crtc;
	3921	+ uint32_t vp_id;
	3922	+ uint8_t phys_id;
	3923	+ int ret;
	3924	+
	3925	+ if (pd->data->id == VOP2_PD_CLUSTER0 \|\| pd->data->id == VOP2_PD_CLUSTER1 \|\|
	3926	+ pd->data->id == VOP2_PD_CLUSTER2 \|\| pd->data->id == VOP2_PD_CLUSTER3 \|\|
	3927	+ pd->data->id == VOP2_PD_ESMART) {
	3928	+ phys_id = ffs(pd->data->module_id_mask) - 1;
	3929	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	3930	+ vp_id = ffs(win->vp_mask) - 1;
	3931	+ vp = &vop2->vps[vp_id];
	3932	+ } else {
	3933	+ DRM_DEV_ERROR(vop2->dev, "unexpected power on pd%d\n", ffs(pd->data->id) - 1);
	3934	+ }
	3935	+
	3936	+ if (vp) {
	3937	+ ret = clk_prepare_enable(vp->dclk);
	3938	+ if (ret < 0)
	3939	+ DRM_DEV_ERROR(vop2->dev, "failed to enable dclk for video port%d - %d\n",
	3940	+ vp->id, ret);
	3941	+ crtc = &vp->rockchip_crtc.crtc;
	3942	+ VOP_MODULE_SET(vop2, vp, standby, 0);
	3943	+ vop2_power_domain_off(pd);
	3944	+ vop2_cfg_done(crtc);
	3945	+ vop2_wait_power_domain_off(pd);
	3946	+
	3947	+ reinit_completion(&vp->dsp_hold_completion);
	3948	+ vop2_dsp_hold_valid_irq_enable(crtc);
	3949	+ VOP_MODULE_SET(vop2, vp, standby, 1);
	3950	+ ret = wait_for_completion_timeout(&vp->dsp_hold_completion, msecs_to_jiffies(50));
	3951	+ if (!ret)
	3952	+ DRM_DEV_INFO(vop2->dev, "wait for vp%d dsp_hold timeout\n", vp->id);
	3953	+
	3954	+ vop2_dsp_hold_valid_irq_disable(crtc);
	3955	+ clk_disable_unprepare(vp->dclk);
	3956	+ }
	3957	+}
	3958	+
	3959	+static void vop2_power_off_all_pd(struct vop2 *vop2)
	3960	+{
	3961	+ struct vop2_power_domain pd, n;
	3962	+
	3963	+ list_for_each_entry_safe_reverse(pd, n, &vop2->pd_list_head, list) {
	3964	+ if (vop2_power_domain_status(pd))
	3965	+ vop2_power_domain_off_by_disabled_vp(pd);
	3966	+ pd->on = false;
	3967	+ pd->vp_mask = 0;
	3968	+ }
	3969	+}
	3970	+
3223	3971	static void vop2_disable(struct drm_crtc *crtc)
3224	3972	{
3225	3973	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -3230,7 +3978,6 @@
3230	3978	if (--vop2->enable_count > 0)
3231	3979	return;
3232	3980
3233		- vop2->is_enabled = false;
3234	3981	if (vop2->is_iommu_enabled) {
3235	3982	/*
3236	3983	* vop2 standby complete, so iommu detach is safe.
..	..	@@ -3239,25 +3986,358 @@
3239	3986	rockchip_drm_dma_detach_device(vop2->drm_dev, vop2->dev);
3240	3987	vop2->is_iommu_enabled = false;
3241	3988	}
	3989	+ if (vop2->version == VOP_VERSION_RK3588)
	3990	+ vop2_power_off_all_pd(vop2);
3242	3991
	3992	+ vop2->is_enabled = false;
3243	3993	pm_runtime_put_sync(vop2->dev);
3244	3994
	3995	+ clk_disable_unprepare(vop2->pclk);
3245	3996	clk_disable_unprepare(vop2->aclk);
3246	3997	clk_disable_unprepare(vop2->hclk);
	3998	+}
	3999	+
	4000	+static void vop2_crtc_disable_dsc(struct vop2 *vop2, u8 dsc_id)
	4001	+{
	4002	+ struct vop2_dsc *dsc = &vop2->dscs[dsc_id];
	4003	+
	4004	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	4005	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, 0);
	4006	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 0);
	4007	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 0);
	4008	+}
	4009	+
	4010	+static struct vop2_clk vop2_clk_get(struct vop2 vop2, const char *name)
	4011	+{
	4012	+ struct vop2_clk clk, n;
	4013	+
	4014	+ if (!name)
	4015	+ return NULL;
	4016	+
	4017	+ list_for_each_entry_safe(clk, n, &vop2->clk_list_head, list) {
	4018	+ if (!strcmp(clk_hw_get_name(&clk->hw), name))
	4019	+ return clk;
	4020	+ }
	4021	+
	4022	+ return NULL;
	4023	+}
	4024	+
	4025	+static void vop2_clk_set_parent(struct clk clk, struct clk parent)
	4026	+{
	4027	+ int ret = 0;
	4028	+
	4029	+ if (parent)
	4030	+ ret = clk_set_parent(clk, parent);
	4031	+ if (ret < 0)
	4032	+ DRM_WARN("failed to set %s as parent for %s\n",
	4033	+ __clk_get_name(parent), __clk_get_name(clk));
	4034	+}
	4035	+
	4036	+static int vop2_extend_clk_init(struct vop2 *vop2)
	4037	+{
	4038	+ const char * const extend_clk_name[] = {
	4039	+ "hdmi0_phy_pll", "hdmi1_phy_pll"};
	4040	+ struct drm_device *drm_dev = vop2->drm_dev;
	4041	+ struct clk *clk;
	4042	+ struct vop2_extend_pll *extend_pll;
	4043	+ int i;
	4044	+
	4045	+ INIT_LIST_HEAD(&vop2->extend_clk_list_head);
	4046	+
	4047	+ if (vop2->version != VOP_VERSION_RK3588)
	4048	+ return 0;
	4049	+
	4050	+ for (i = 0; i < ARRAY_SIZE(extend_clk_name); i++) {
	4051	+ clk = devm_clk_get_optional(drm_dev->dev, extend_clk_name[i]);
	4052	+ if (IS_ERR(clk)) {
	4053	+ dev_warn(drm_dev->dev, "failed to get %s: %ld\n",
	4054	+ extend_clk_name[i], PTR_ERR(clk));
	4055	+ continue;
	4056	+ }
	4057	+
	4058	+ if (!clk)
	4059	+ continue;
	4060	+
	4061	+ extend_pll = devm_kzalloc(drm_dev->dev, sizeof(*extend_pll), GFP_KERNEL);
	4062	+ if (!extend_pll)
	4063	+ return -ENOMEM;
	4064	+
	4065	+ extend_pll->clk = clk;
	4066	+ extend_pll->vp_mask = 0;
	4067	+ strncpy(extend_pll->clk_name, extend_clk_name[i], sizeof(extend_pll->clk_name));
	4068	+ list_add_tail(&extend_pll->list, &vop2->extend_clk_list_head);
	4069	+ }
	4070	+
	4071	+ return 0;
	4072	+}
	4073	+
	4074	+static struct vop2_extend_pll vop2_extend_clk_find_by_name(struct vop2 vop2, char *clk_name)
	4075	+{
	4076	+ struct vop2_extend_pll *extend_pll;
	4077	+
	4078	+ list_for_each_entry(extend_pll, &vop2->extend_clk_list_head, list) {
	4079	+ if (!strcmp(extend_pll->clk_name, clk_name))
	4080	+ return extend_pll;
	4081	+ }
	4082	+
	4083	+ return NULL;
	4084	+}
	4085	+
	4086	+static int vop2_extend_clk_switch_pll(struct vop2 vop2, struct vop2_extend_pll src,
	4087	+ struct vop2_extend_pll *dst)
	4088	+{
	4089	+ struct vop2_clk *dclk;
	4090	+ u32 vp_mask;
	4091	+ int i = 0;
	4092	+ char clk_name[32];
	4093	+
	4094	+ if (!src->vp_mask)
	4095	+ return -EINVAL;
	4096	+
	4097	+ if (dst->vp_mask)
	4098	+ return -EBUSY;
	4099	+
	4100	+ vp_mask = src->vp_mask;
	4101	+
	4102	+ while (vp_mask) {
	4103	+ if ((BIT(i) & src->vp_mask)) {
	4104	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", i);
	4105	+ dclk = vop2_clk_get(vop2, clk_name);
	4106	+ clk_set_rate(dst->clk, dclk->rate);
	4107	+ vop2_clk_set_parent(vop2->vps[i].dclk, dst->clk);
	4108	+ src->vp_mask &= ~BIT(i);
	4109	+ dst->vp_mask \|= BIT(i);
	4110	+ }
	4111	+ i++;
	4112	+ vp_mask = vp_mask >> 1;
	4113	+ }
	4114	+
	4115	+ return 0;
	4116	+}
	4117	+
	4118	+static inline int vop2_extend_clk_get_vp_id(struct vop2_extend_pll *ext_pll)
	4119	+{
	4120	+ return ffs(ext_pll->vp_mask) - 1;
	4121	+}
	4122	+
	4123	+/*
	4124	+ * Here are 2 hdmi phy pll can use for video port dclk. The strategies of how to use hdmi phy pll
	4125	+ * as follow:
	4126	+ *
	4127	+ * 1. hdmi phy pll can be used for video port0/1/2 when output format under 4K@60Hz;
	4128	+ *
	4129	+ * 2. When a video port connect both hdmi0 and hdmi1(may also connect other output interface),
	4130	+ * it must hold the hdmi0 and hdmi1 phy pll, and other video port can't use it. if request dclk
	4131	+ * is under 4K@60Hz, set the video port dlk parent as hdmi0 phy pll.if hdmi0 or hdmi1 phy pll
	4132	+ * is used by other video port, report a error.
	4133	+ *
	4134	+ * 3. When a video port(A) connect hdmi0(may also connect other output interface but not hdmi1),
	4135	+ * it must hold the hdmi0 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4136	+ * phy pll is used by other video port, report a error. If hdmi0 phy pll is used by another
	4137	+ * video port(B) and hdmi1 phy pll is free, set hdmi1 phy pll as video port(B) dclk parent and
	4138	+ * video port(A) hold hdmi0 phy pll. If hdmi0 phy pll is free, video port(A) hold hdmi0 pll.If
	4139	+ * video port(A) hold hdmi0 phy pll and request dclk is under 4k@60Hz, set hdmi0 phy pll as
	4140	+ * video port(A) dclk parent.
	4141	+ *
	4142	+ * 4. When a video port(A) connect hdmi1(may also connect other output interface but not hdmi0),
	4143	+ * it must hold the hdmi1 phy pll, and other video port can't use it. If both hdmi0 and hdmi1
	4144	+ * phy pll is used by other video port, report a error. If hdmi1 phy pll is used by another
	4145	+ * video port(B) and hdmi0 phy pll is free, set hdmi0 phy pll as video port(B) dclk parent and
	4146	+ * video port(A) hold hdmi1 phy pll. If hdmi1 phy pll is free, video port(A) hold hdmi1 pll. If
	4147	+ * video port(A) hold hdmi1 phy pll and request dclk is under 4k@60Hz, set hdmi1 phy pll as
	4148	+ * video port(A) dclk parent.
	4149	+ *
	4150	+ * 5. When a video port connect dp(0, 1, or both, may also connect other output type but not hdmi0
	4151	+ * and hdmi1). If the request dclk is higher than 4K@60Hz or video port id is 2, do nothing.
	4152	+ * Otherwise get a free hdmi phy pll as video port dclk parent. If no free hdmi phy pll can be
	4153	+ * get, report a error.
	4154	+ */
	4155	+
	4156	+static int vop2_clk_set_parent_extend(struct vop2_video_port *vp,
	4157	+ struct rockchip_crtc_state *vcstate, bool enable)
	4158	+{
	4159	+ struct vop2 *vop2 = vp->vop2;
	4160	+ struct vop2_extend_pll hdmi0_phy_pll, hdmi1_phy_pll;
	4161	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	4162	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	4163	+
	4164	+ hdmi0_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	4165	+ hdmi1_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	4166	+
	4167	+ if (hdmi0_phy_pll)
	4168	+ clk_get_rate(hdmi0_phy_pll->clk);
	4169	+ if (hdmi1_phy_pll)
	4170	+ clk_get_rate(hdmi1_phy_pll->clk);
	4171	+
	4172	+ if ((!hdmi0_phy_pll && !hdmi1_phy_pll) \|\|
	4173	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) && !hdmi0_phy_pll) \|\|
	4174	+ ((vcstate->output_if & VOP_OUTPUT_IF_HDMI1) && !hdmi1_phy_pll))
	4175	+ return 0;
	4176	+
	4177	+ if (enable) {
	4178	+ if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4179	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4180	+ if (hdmi0_phy_pll->vp_mask) {
	4181	+ DRM_ERROR("hdmi0 phy pll is used by vp%d\n",
	4182	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4183	+ return -EBUSY;
	4184	+ }
	4185	+
	4186	+ if (hdmi1_phy_pll->vp_mask) {
	4187	+ DRM_ERROR("hdmi1 phy pll is used by vp%d\n",
	4188	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4189	+ return -EBUSY;
	4190	+ }
	4191	+
	4192	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4193	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4194	+ else
	4195	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4196	+
	4197	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4198	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4199	+ } else if ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4200	+ !(vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4201	+ if (hdmi0_phy_pll->vp_mask) {
	4202	+ if (hdmi1_phy_pll) {
	4203	+ if (hdmi1_phy_pll->vp_mask) {
	4204	+ DRM_ERROR("hdmi0: phy pll is used by vp%d:vp%d\n",
	4205	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4206	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4207	+ return -EBUSY;
	4208	+ }
	4209	+
	4210	+ vop2_extend_clk_switch_pll(vop2, hdmi0_phy_pll,
	4211	+ hdmi1_phy_pll);
	4212	+ } else {
	4213	+ DRM_ERROR("hdmi0: phy pll is used by vp%d\n",
	4214	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll));
	4215	+ return -EBUSY;
	4216	+ }
	4217	+ }
	4218	+
	4219	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4220	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4221	+ else
	4222	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4223	+
	4224	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4225	+ } else if (!(vcstate->output_if & VOP_OUTPUT_IF_HDMI0) &&
	4226	+ (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)) {
	4227	+ if (hdmi1_phy_pll->vp_mask) {
	4228	+ if (hdmi0_phy_pll) {
	4229	+ if (hdmi0_phy_pll->vp_mask) {
	4230	+ DRM_ERROR("hdmi1: phy pll is used by vp%d:vp%d\n",
	4231	+ vop2_extend_clk_get_vp_id(hdmi0_phy_pll),
	4232	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4233	+ return -EBUSY;
	4234	+ }
	4235	+
	4236	+ vop2_extend_clk_switch_pll(vop2, hdmi1_phy_pll,
	4237	+ hdmi0_phy_pll);
	4238	+ } else {
	4239	+ DRM_ERROR("hdmi1: phy pll is used by vp%d\n",
	4240	+ vop2_extend_clk_get_vp_id(hdmi1_phy_pll));
	4241	+ return -EBUSY;
	4242	+ }
	4243	+ }
	4244	+
	4245	+ if (adjusted_mode->crtc_clock > VOP2_MAX_DCLK_RATE)
	4246	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4247	+ else
	4248	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4249	+
	4250	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4251	+ } else if (output_if_is_dp(vcstate->output_if)) {
	4252	+ if (vp->id == 2) {
	4253	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4254	+ return 0;
	4255	+ }
	4256	+
	4257	+ if (hdmi0_phy_pll && !hdmi0_phy_pll->vp_mask) {
	4258	+ vop2_clk_set_parent(vp->dclk, hdmi0_phy_pll->clk);
	4259	+ hdmi0_phy_pll->vp_mask \|= BIT(vp->id);
	4260	+ } else if (hdmi1_phy_pll && !hdmi1_phy_pll->vp_mask) {
	4261	+ vop2_clk_set_parent(vp->dclk, hdmi1_phy_pll->clk);
	4262	+ hdmi1_phy_pll->vp_mask \|= BIT(vp->id);
	4263	+ } else {
	4264	+ vop2_clk_set_parent(vp->dclk, vp->dclk_parent);
	4265	+ DRM_INFO("No free hdmi phy pll for DP, use default parent\n");
	4266	+ }
	4267	+ }
	4268	+ } else {
	4269	+ if (hdmi0_phy_pll && (BIT(vp->id) & hdmi0_phy_pll->vp_mask))
	4270	+ hdmi0_phy_pll->vp_mask &= ~BIT(vp->id);
	4271	+
	4272	+ if (hdmi1_phy_pll && (BIT(vp->id) & hdmi1_phy_pll->vp_mask))
	4273	+ hdmi1_phy_pll->vp_mask &= ~BIT(vp->id);
	4274	+ }
	4275	+
	4276	+ return 0;
	4277	+}
	4278	+
	4279	+static void vop2_crtc_atomic_disable_for_psr(struct drm_crtc *crtc,
	4280	+ struct drm_crtc_state *old_state)
	4281	+{
	4282	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4283	+ struct vop2 *vop2 = vp->vop2;
	4284	+
	4285	+ vop2_disable_all_planes_for_crtc(crtc);
	4286	+ drm_crtc_vblank_off(crtc);
	4287	+ if (hweight8(vop2->active_vp_mask) == 1) {
	4288	+ u32 adjust_aclk_rate = 0;
	4289	+ u32 htotal = (VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16) & 0xffff;
	4290	+ u32 pre_scan_dly = VOP_MODULE_GET(vop2, vp, pre_scan_htiming);
	4291	+ u32 pre_scan_hblank = pre_scan_dly & 0x1fff;
	4292	+ u32 pre_scan_hactive = (pre_scan_dly >> 16) & 0x1fff;
	4293	+ u32 dclk_rate = crtc->state->adjusted_mode.crtc_clock / 1000;
	4294	+ /**
	4295	+ * (pre_scan_hblank + pre_scan_hactive) x aclk_margin / adjust_aclk_rate = hotal / dclk_rate
	4296	+ * aclk_margin = 1.2, so
	4297	+ * adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) x 1.2 * aclk_margin / htotal
	4298	+ */
	4299	+
	4300	+ adjust_aclk_rate = (pre_scan_hblank + pre_scan_hactive) * dclk_rate * 12 / 10 / htotal;
	4301	+
	4302	+ vop2->aclk_rate = clk_get_rate(vop2->aclk);
	4303	+ clk_set_rate(vop2->aclk, adjust_aclk_rate * 1000000L);
	4304	+ vop2->aclk_rate_reset = true;
	4305	+ }
3247	4306	}
3248	4307
3249	4308	static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
3250	4309	struct drm_crtc_state *old_state)
3251	4310	{
3252	4311	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4312	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3253	4313	struct vop2 *vop2 = vp->vop2;
3254	4314	const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	4315	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	4316	+ bool dual_channel = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE);
3255	4317	int ret;
3256	4318
3257	4319	WARN_ON(vp->event);
	4320	+
	4321	+ if (crtc->state->self_refresh_active) {
	4322	+ vop2_crtc_atomic_disable_for_psr(crtc, old_state);
	4323	+ goto out;
	4324	+ }
	4325	+
3258	4326	vop2_lock(vop2);
3259	4327	DRM_DEV_INFO(vop2->dev, "Crtc atomic disable vp%d\n", vp->id);
	4328	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 0);
	4329	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 0);
3260	4330	drm_crtc_vblank_off(crtc);
	4331	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4332	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4333	+ vop2->data->nr_dscs) {
	4334	+ if (dual_channel) {
	4335	+ vop2_crtc_disable_dsc(vop2, 0);
	4336	+ vop2_crtc_disable_dsc(vop2, 1);
	4337	+ } else {
	4338	+ vop2_crtc_disable_dsc(vop2, vcstate->dsc_id);
	4339	+ }
	4340	+ }
3261	4341
3262	4342	if (vp->cubic_lut) {
3263	4343	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
..	..	@@ -3268,6 +4348,47 @@
3268	4348	VOP_MODULE_SET(vop2, vp, hdr_lut_update_en, 0);
3269	4349	vop2_disable_all_planes_for_crtc(crtc);
3270	4350
	4351	+ if (vop2->dscs[vcstate->dsc_id].enabled &&
	4352	+ vop2->dscs[vcstate->dsc_id].attach_vp_id == vp->id &&
	4353	+ vop2->data->nr_dscs && vop2->dscs[vcstate->dsc_id].pd) {
	4354	+ if (dual_channel) {
	4355	+ vop2_power_domain_put(vop2->dscs[0].pd);
	4356	+ vop2_power_domain_put(vop2->dscs[1].pd);
	4357	+ vop2->dscs[0].pd->vp_mask = 0;
	4358	+ vop2->dscs[1].pd->vp_mask = 0;
	4359	+ vop2->dscs[0].attach_vp_id = -1;
	4360	+ vop2->dscs[1].attach_vp_id = -1;
	4361	+ } else {
	4362	+ vop2_power_domain_put(vop2->dscs[vcstate->dsc_id].pd);
	4363	+ vop2->dscs[vcstate->dsc_id].pd->vp_mask = 0;
	4364	+ vop2->dscs[vcstate->dsc_id].attach_vp_id = -1;
	4365	+ }
	4366	+ vop2->dscs[vcstate->dsc_id].enabled = false;
	4367	+ vcstate->dsc_enable = false;
	4368	+ }
	4369	+
	4370	+ if (vp->output_if & VOP_OUTPUT_IF_eDP0)
	4371	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 0);
	4372	+
	4373	+ if (vp->output_if & VOP_OUTPUT_IF_eDP1)
	4374	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 0);
	4375	+
	4376	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI0) {
	4377	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 0);
	4378	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 0);
	4379	+ }
	4380	+
	4381	+ if (vp->output_if & VOP_OUTPUT_IF_HDMI1) {
	4382	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 0);
	4383	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 0);
	4384	+ }
	4385	+
	4386	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 0);
	4387	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 0);
	4388	+
	4389	+ vp->output_if = 0;
	4390	+
	4391	+ vop2_clk_set_parent_extend(vp, vcstate, false);
3271	4392	/*
3272	4393	* Vop standby will take effect at end of current frame,
3273	4394	* if dsp hold valid irq happen, it means standby complete.
..	..	@@ -3280,6 +4401,8 @@
3280	4401
3281	4402	spin_lock(&vop2->reg_lock);
3282	4403
	4404	+ VOP_MODULE_SET(vop2, vp, splice_en, 0);
	4405	+
3283	4406	VOP_MODULE_SET(vop2, vp, standby, 1);
3284	4407
3285	4408	spin_unlock(&vop2->reg_lock);
..	..	@@ -3291,12 +4414,21 @@
3291	4414	vop2_dsp_hold_valid_irq_disable(crtc);
3292	4415
3293	4416	vop2_disable(crtc);
	4417	+
	4418	+ vop2->active_vp_mask &= ~BIT(vp->id);
	4419	+ if (vcstate->splice_mode)
	4420	+ vop2->active_vp_mask &= ~BIT(splice_vp->id);
	4421	+ vcstate->splice_mode = false;
	4422	+ vcstate->output_flags = 0;
	4423	+ vp->splice_mode_right = false;
	4424	+ vp->loader_protect = false;
	4425	+ splice_vp->splice_mode_right = false;
3294	4426	memset(&vp->active_tv_state, 0, sizeof(vp->active_tv_state));
3295	4427	vop2_unlock(vop2);
3296	4428
3297		- vop2->active_vp_mask &= ~BIT(vp->id);
3298	4429	vop2_set_system_status(vop2);
3299	4430
	4431	+out:
3300	4432	if (crtc->state->event && !crtc->state->active) {
3301	4433	spin_lock_irq(&crtc->dev->event_lock);
3302	4434	drm_crtc_send_vblank_event(crtc, crtc->state->event);
..	..	@@ -3306,23 +4438,140 @@
3306	4438	}
3307	4439	}
3308	4440
	4441	+static int vop2_cluster_two_win_mode_check(struct drm_plane_state *pstate)
	4442	+{
	4443	+ struct drm_atomic_state *state = pstate->state;
	4444	+ struct drm_plane *plane = pstate->plane;
	4445	+ struct vop2_win *win = to_vop2_win(plane);
	4446	+ struct vop2 *vop2 = win->vop2;
	4447	+ struct vop2_win *main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
	4448	+ struct drm_plane_state *main_pstate;
	4449	+ int actual_w = drm_rect_width(&pstate->src) >> 16;
	4450	+ int xoffset;
	4451	+
	4452	+ if (pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4453	+ xoffset = 0;
	4454	+ else
	4455	+ xoffset = pstate->src.x1 >> 16;
	4456	+
	4457	+ if ((actual_w + xoffset % 16) > 2048) {
	4458	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4459	+ win->name, actual_w, xoffset);
	4460	+ return -EINVAL;
	4461	+ }
	4462	+
	4463	+ main_pstate = drm_atomic_get_new_plane_state(state, &main_win->base);
	4464	+
	4465	+ if (pstate->fb->modifier != main_pstate->fb->modifier) {
	4466	+ DRM_ERROR("%s(fb->modifier: 0x%llx) must use same data layout as %s(fb->modifier: 0x%llx)\n",
	4467	+ win->name, pstate->fb->modifier, main_win->name, main_pstate->fb->modifier);
	4468	+ return -EINVAL;
	4469	+ }
	4470	+
	4471	+ if (main_pstate->fb->modifier == DRM_FORMAT_MOD_LINEAR)
	4472	+ xoffset = 0;
	4473	+ else
	4474	+ xoffset = main_pstate->src.x1 >> 16;
	4475	+ actual_w = drm_rect_width(&main_pstate->src) >> 16;
	4476	+
	4477	+ if ((actual_w + xoffset % 16) > 2048) {
	4478	+ DRM_ERROR("%s act_w(%d) + xoffset(%d) / 16 << 2048 in two win mode\n",
	4479	+ main_win->name, actual_w, xoffset);
	4480	+ return -EINVAL;
	4481	+ }
	4482	+
	4483	+ return 0;
	4484	+}
	4485	+
	4486	+static int vop2_cluter_splice_scale_check(struct vop2_win win, struct drm_plane_state pstate,
	4487	+ u16 hdisplay)
	4488	+{
	4489	+ struct drm_rect src = drm_plane_state_src(pstate);
	4490	+ struct drm_rect dst = drm_plane_state_dest(pstate);
	4491	+ u16 half_hdisplay = hdisplay >> 1;
	4492	+
	4493	+ /* scale up is ok */
	4494	+ if ((drm_rect_width(&src) >> 16) <= drm_rect_width(&dst))
	4495	+ return 0;
	4496	+
	4497	+ if ((drm_rect_width(&src) >> 16) <= VOP2_MAX_VP_OUTPUT_WIDTH)
	4498	+ return 0;
	4499	+ /*
	4500	+ * Cluster scale down limitation in splice mode:
	4501	+ * If scale down, must display at horizontal center
	4502	+ */
	4503	+ if ((dst.x1 < half_hdisplay) && (dst.x2 > half_hdisplay)) {
	4504	+ if ((dst.x2 + dst.x1) != hdisplay) {
	4505	+ DRM_ERROR("%s src_w: %d dst_w %d dst(%d %d) must scale down at center in splice mode\n",
	4506	+ win->name, drm_rect_width(&src) >> 16,
	4507	+ drm_rect_width(&dst), dst.x1, dst.x2);
	4508	+ return -EINVAL;
	4509	+ }
	4510	+
	4511	+ if (drm_rect_calc_hscale(&src, &dst, 1, FRAC_16_16(6, 5)) < 0) {
	4512	+ DRM_ERROR("%s %d --> %d scale down factor should < 1.2 in splice mode\n",
	4513	+ win->name, drm_rect_width(&src) >> 16, drm_rect_width(&dst));
	4514	+ return -EINVAL;
	4515	+ }
	4516	+ }
	4517	+
	4518	+ return 0;
	4519	+}
	4520	+
	4521	+static int vop2_plane_splice_check(struct drm_plane plane, struct drm_plane_state pstate,
	4522	+ struct drm_display_mode *mode)
	4523	+{
	4524	+ struct vop2_win *win = to_vop2_win(plane);
	4525	+ int ret = 0;
	4526	+
	4527	+ if (!(win->feature & WIN_FEATURE_SPLICE_LEFT)) {
	4528	+ DRM_ERROR("%s can't be left win in splice mode\n", win->name);
	4529	+ return -EINVAL;
	4530	+ }
	4531	+
	4532	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4533	+ DRM_ERROR("%s can't use two win mode in splice mode\n", win->name);
	4534	+ return -EINVAL;
	4535	+ }
	4536	+
	4537	+ if ((pstate->rotation & DRM_MODE_ROTATE_270) \|\|
	4538	+ (pstate->rotation & DRM_MODE_ROTATE_90) \|\|
	4539	+ (pstate->rotation & DRM_MODE_REFLECT_X)) {
	4540	+ DRM_ERROR("%s can't rotate 270/90 and xmirror in splice mode\n", win->name);
	4541	+ return -EINVAL;
	4542	+ }
	4543	+
	4544	+ /* check for cluster splice scale down */
	4545	+ if (win->feature & WIN_FEATURE_CLUSTER_MAIN)
	4546	+ ret = vop2_cluter_splice_scale_check(win, pstate, mode->hdisplay);
	4547	+
	4548	+ return ret;
	4549	+}
	4550	+
3309	4551	static int vop2_plane_atomic_check(struct drm_plane plane, struct drm_plane_state state)
3310	4552	{
3311	4553	struct vop2_plane_state *vpstate = to_vop2_plane_state(state);
3312	4554	struct vop2_win *win = to_vop2_win(plane);
	4555	+ struct vop2_win *splice_win;
	4556	+ struct vop2 *vop2 = win->vop2;
3313	4557	struct drm_framebuffer *fb = state->fb;
	4558	+ struct drm_display_mode *mode;
3314	4559	struct drm_crtc *crtc = state->crtc;
3315	4560	struct drm_crtc_state *cstate;
	4561	+ struct rockchip_crtc_state *vcstate;
3316	4562	struct vop2_video_port *vp;
3317	4563	const struct vop2_data *vop2_data;
3318	4564	struct drm_rect *dest = &vpstate->dest;
3319	4565	struct drm_rect *src = &vpstate->src;
	4566	+ struct drm_gem_object obj, uv_obj;
	4567	+ struct rockchip_gem_object rk_obj, rk_uv_obj;
3320	4568	int min_scale = win->regs->scl ? FRAC_16_16(1, 8) : DRM_PLANE_HELPER_NO_SCALING;
3321	4569	int max_scale = win->regs->scl ? FRAC_16_16(8, 1) : DRM_PLANE_HELPER_NO_SCALING;
3322	4570	uint32_t tile_size = 1;
	4571	+ int max_input_w;
	4572	+ int max_input_h;
3323	4573	unsigned long offset;
3324	4574	dma_addr_t dma_addr;
3325		- void *kvaddr;
3326	4575	int ret;
3327	4576
3328	4577	crtc = crtc ? crtc : plane->state->crtc;
..	..	@@ -3338,6 +4587,26 @@
3338	4587	if (WARN_ON(!cstate))
3339	4588	return -EINVAL;
3340	4589
	4590	+ mode = &cstate->mode;
	4591	+ vcstate = to_rockchip_crtc_state(cstate);
	4592	+
	4593	+ max_input_w = vop2_data->max_input.width;
	4594	+ max_input_h = vop2_data->max_input.height;
	4595	+
	4596	+ if (vop2_has_feature(win->vop2, VOP_FEATURE_SPLICE)) {
	4597	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	4598	+ vcstate->splice_mode = true;
	4599	+ ret = vop2_plane_splice_check(plane, state, mode);
	4600	+ if (ret < 0)
	4601	+ return ret;
	4602	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	4603	+ splice_win->splice_mode_right = true;
	4604	+ splice_win->left_win = win;
	4605	+ win->splice_win = splice_win;
	4606	+ max_input_w <<= 1;
	4607	+ }
	4608	+ }
	4609	+
3341	4610	vpstate->xmirror_en = (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0;
3342	4611	vpstate->ymirror_en = (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0;
3343	4612	vpstate->rotate_270_en = (state->rotation & DRM_MODE_ROTATE_270) ? 1 : 0;
..	..	@@ -3347,7 +4616,6 @@
3347	4616	DRM_ERROR("Can't rotate 90 and 270 at the same time\n");
3348	4617	return -EINVAL;
3349	4618	}
3350		-
3351	4619
3352	4620	ret = drm_atomic_helper_check_plane_state(state, cstate,
3353	4621	min_scale, max_scale,
..	..	@@ -3388,13 +4656,13 @@
3388	4656	return 0;
3389	4657	}
3390	4658
3391		- if (drm_rect_width(src) >> 16 > vop2_data->max_input.width \|\|
3392		- drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
	4659	+ if (drm_rect_width(src) >> 16 > max_input_w \|\|
	4660	+ drm_rect_height(src) >> 16 > max_input_h) {
3393	4661	DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
3394	4662	drm_rect_width(src) >> 16,
3395	4663	drm_rect_height(src) >> 16,
3396		- vop2_data->max_input.width,
3397		- vop2_data->max_input.height);
	4664	+ max_input_w,
	4665	+ max_input_h);
3398	4666	return -EINVAL;
3399	4667	}
3400	4668
..	..	@@ -3417,11 +4685,31 @@
3417	4685	* This is special feature at rk356x, the cluster layer only can support
3418	4686	* afbc format and can't support linear format;
3419	4687	*/
3420		- if (VOP_MAJOR(vop2_data->version) == 0x40 && VOP_MINOR(vop2_data->version) == 0x15) {
	4688	+ if (vp->vop2->version == VOP_VERSION_RK3568) {
3421	4689	if (vop2_cluster_window(win) && !vpstate->afbc_en) {
3422	4690	DRM_ERROR("Unsupported linear format at %s\n", win->name);
3423	4691	return -EINVAL;
3424	4692	}
	4693	+ }
	4694	+
	4695	+ if (vp->vop2->version > VOP_VERSION_RK3568) {
	4696	+ if (vop2_cluster_window(win) && !vpstate->afbc_en && fb->format->is_yuv && !is_vop3(vop2)) {
	4697	+ DRM_ERROR("Unsupported linear yuv format at %s\n", win->name);
	4698	+ return -EINVAL;
	4699	+ }
	4700	+
	4701	+ if (vop2_cluster_window(win) && !vpstate->afbc_en &&
	4702	+ (win->supported_rotations & state->rotation)) {
	4703	+ DRM_ERROR("Unsupported linear rotation(%d) format at %s\n",
	4704	+ state->rotation, win->name);
	4705	+ return -EINVAL;
	4706	+ }
	4707	+ }
	4708	+
	4709	+ if (win->feature & WIN_FEATURE_CLUSTER_SUB) {
	4710	+ ret = vop2_cluster_two_win_mode_check(state);
	4711	+ if (ret < 0)
	4712	+ return ret;
3425	4713	}
3426	4714
3427	4715	/*
..	..	@@ -3433,7 +4721,10 @@
3433	4721	return -EINVAL;
3434	4722	}
3435	4723
3436		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[0] / 8 * tile_size;
	4724	+ if (fb->format->char_per_block[0] == 0)
	4725	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[0] * tile_size;
	4726	+ else
	4727	+ offset = drm_format_info_min_pitch(fb->format, 0, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size;
3437	4728	vpstate->offset = offset + fb->offsets[0];
3438	4729
3439	4730	/*
..	..	@@ -3446,30 +4737,33 @@
3446	4737	else
3447	4738	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[0];
3448	4739
3449		- dma_addr = rockchip_fb_get_dma_addr(fb, 0);
3450		- kvaddr = rockchip_fb_get_kvaddr(fb, 0);
	4740	+ obj = fb->obj[0];
	4741	+ rk_obj = to_rockchip_obj(obj);
3451	4742
3452		- vpstate->yrgb_mst = dma_addr + offset + fb->offsets[0];
3453		- vpstate->yrgb_kvaddr = kvaddr + offset + fb->offsets[0];
3454		- if (fb->format->is_yuv) {
3455		- int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
3456		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
	4743	+ vpstate->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
	4744	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	4745	+ int hsub = fb->format->hsub;
	4746	+ int vsub = fb->format->vsub;
3457	4747
3458		- offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->bpp[1] / hsub / 8 * tile_size;
	4748	+ if (fb->format->char_per_block[0] == 0)
	4749	+ offset = ALIGN_DOWN(src->x1 >> 16, tile_size) * fb->format->cpp[1] / hsub * tile_size;
	4750	+ else
	4751	+ offset = drm_format_info_min_pitch(fb->format, 1, ALIGN_DOWN(src->x1 >> 16, tile_size)) * tile_size / hsub;
	4752	+
3459	4753	if (vpstate->tiled_en)
3460	4754	offset /= vsub;
3461	4755	offset += ALIGN_DOWN(src->y1 >> 16, tile_size) * fb->pitches[1] / vsub;
	4756	+
	4757	+ uv_obj = fb->obj[1];
	4758	+ rk_uv_obj = to_rockchip_obj(uv_obj);
	4759	+
3462	4760	if (vpstate->ymirror_en && !vpstate->afbc_en)
3463	4761	offset += fb->pitches[1] * ((state->src_h >> 16) - 2) / vsub;
3464		- dma_addr = rockchip_fb_get_dma_addr(fb, 1);
3465		- dma_addr += offset + fb->offsets[1];
	4762	+ dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
3466	4763	vpstate->uv_mst = dma_addr;
3467		-
3468	4764	/* tile 4x4 m0 format, y and uv is packed together */
3469		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0) {
	4765	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0)
3470	4766	vpstate->yrgb_mst += offset;
3471		- vpstate->yrgb_kvaddr += offset;
3472		- }
3473	4767	}
3474	4768
3475	4769	return 0;
..	..	@@ -3483,15 +4777,17 @@
3483	4777	struct vop2_plane_state *vpstate = to_vop2_plane_state(plane->state);
3484	4778	#endif
3485	4779
3486		- DRM_DEV_DEBUG(vop2->dev, "%s disable\n", win->name);
	4780	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE, "%s disable %s\n",
	4781	+ win->name, current->comm);
3487	4782
3488	4783	if (!old_state->crtc)
3489	4784	return;
3490	4785
3491	4786	spin_lock(&vop2->reg_lock);
3492	4787
3493		- vop2_win_disable(win);
3494		- VOP_WIN_SET(vop2, win, yuv_clip, 0);
	4788	+ vop2_win_disable(win, false);
	4789	+ if (win->splice_win)
	4790	+ vop2_win_disable(win->splice_win, false);
3495	4791
3496	4792	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
3497	4793	kfree(vpstate->planlist);
..	..	@@ -3555,6 +4851,64 @@
3555	4851	VOP_WIN_SET(vop2, win, color_key, color_key);
3556	4852	}
3557	4853
	4854	+static void vop2_calc_drm_rect_for_splice(struct vop2_plane_state *vpstate,
	4855	+ struct drm_rect left_src, struct drm_rect left_dst,
	4856	+ struct drm_rect right_src, struct drm_rect right_dst)
	4857	+{
	4858	+ struct drm_crtc *crtc = vpstate->base.crtc;
	4859	+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
	4860	+ struct drm_rect *dst = &vpstate->dest;
	4861	+ struct drm_rect *src = &vpstate->src;
	4862	+ u16 half_hdisplay = mode->crtc_hdisplay >> 1;
	4863	+ int hscale = drm_rect_calc_hscale(src, dst, 0, INT_MAX);
	4864	+ int dst_w = drm_rect_width(dst);
	4865	+ int src_w = drm_rect_width(src) >> 16;
	4866	+ int left_src_w, left_dst_w, right_dst_w;
	4867	+ struct drm_plane_state *pstate = &vpstate->base;
	4868	+ struct drm_framebuffer *fb = pstate->fb;
	4869	+
	4870	+ left_dst_w = min_t(u16, half_hdisplay, dst->x2) - dst->x1;
	4871	+ if (left_dst_w < 0)
	4872	+ left_dst_w = 0;
	4873	+ right_dst_w = dst_w - left_dst_w;
	4874	+
	4875	+ if (!right_dst_w)
	4876	+ left_src_w = src_w;
	4877	+ else
	4878	+ left_src_w = (left_dst_w * hscale) >> 16;
	4879	+
	4880	+ /*
	4881	+ * Make sure the yrgb/uv mst of right win are byte aligned
	4882	+ * with full pixel.
	4883	+ */
	4884	+ if (right_dst_w) {
	4885	+ if (fb->format->format == DRM_FORMAT_NV15)
	4886	+ left_src_w &= ~0x7;
	4887	+ else if (fb->format->format == DRM_FORMAT_NV12)
	4888	+ left_src_w &= ~0x1;
	4889	+ }
	4890	+ left_src->x1 = src->x1;
	4891	+ left_src->x2 = src->x1 + (left_src_w << 16);
	4892	+ left_dst->x1 = dst->x1;
	4893	+ left_dst->x2 = dst->x1 + left_dst_w;
	4894	+ right_src->x1 = left_src->x2;
	4895	+ right_src->x2 = src->x2;
	4896	+ right_dst->x1 = dst->x1 + left_dst_w - half_hdisplay;
	4897	+ if (right_dst->x1 < 0)
	4898	+ right_dst->x1 = 0;
	4899	+
	4900	+ right_dst->x2 = right_dst->x1 + right_dst_w;
	4901	+
	4902	+ left_src->y1 = src->y1;
	4903	+ left_src->y2 = src->y2;
	4904	+ left_dst->y1 = dst->y1;
	4905	+ left_dst->y2 = dst->y2;
	4906	+ right_src->y1 = src->y1;
	4907	+ right_src->y2 = src->y2;
	4908	+ right_dst->y1 = dst->y1;
	4909	+ right_dst->y2 = dst->y2;
	4910	+}
	4911	+
3558	4912	static void rk3588_vop2_win_cfg_axi(struct vop2_win *win)
3559	4913	{
3560	4914	struct vop2 *vop2 = win->vop2;
..	..	@@ -3589,49 +4943,301 @@
3589	4943	}
3590	4944	}
3591	4945
	4946	+static void vop2_win_atomic_update(struct vop2_win win, struct drm_rect src, struct drm_rect *dst,
	4947	+ struct drm_plane_state *pstate)
	4948	+{
	4949	+ struct drm_crtc *crtc = pstate->crtc;
	4950	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	4951	+ struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
	4952	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	4953	+ struct vop2 *vop2 = win->vop2;
	4954	+ struct drm_framebuffer *fb = pstate->fb;
	4955	+ struct drm_rect *left_src = &vpstate->src;
	4956	+ uint32_t bpp = rockchip_drm_get_bpp(fb->format);
	4957	+ uint32_t actual_w, actual_h, dsp_w, dsp_h;
	4958	+ uint32_t dsp_stx, dsp_sty;
	4959	+ uint32_t act_info, dsp_info, dsp_st;
	4960	+ uint32_t format;
	4961	+ uint32_t afbc_format;
	4962	+ uint32_t rb_swap;
	4963	+ uint32_t uv_swap;
	4964	+ uint32_t afbc_half_block_en;
	4965	+ uint32_t afbc_tile_num;
	4966	+ uint32_t lb_mode;
	4967	+ uint32_t stride, uv_stride = 0;
	4968	+ uint32_t transform_offset;
	4969	+ /* offset of the right window in splice mode */
	4970	+ uint32_t splice_pixel_offset = 0;
	4971	+ uint32_t splice_yrgb_offset = 0;
	4972	+ uint32_t splice_uv_offset = 0;
	4973	+ uint32_t afbc_xoffset;
	4974	+ uint32_t hsub;
	4975	+ dma_addr_t yrgb_mst;
	4976	+ dma_addr_t uv_mst;
	4977	+
	4978	+ struct drm_format_name_buf format_name;
	4979	+ bool dither_up;
	4980	+ bool tile_4x4_m0 = vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 ? true : false;
	4981	+
	4982	+ actual_w = drm_rect_width(src) >> 16;
	4983	+ actual_h = drm_rect_height(src) >> 16;
	4984	+
	4985	+ if (!actual_w \|\| !actual_h) {
	4986	+ vop2_win_disable(win, true);
	4987	+ return;
	4988	+ }
	4989	+
	4990	+ dsp_w = drm_rect_width(dst);
	4991	+ /*
	4992	+ * This win is for the right part of the plane,
	4993	+ * we need calculate the fb offset for it.
	4994	+ */
	4995	+ if (win->splice_mode_right) {
	4996	+ splice_pixel_offset = (src->x1 - left_src->x1) >> 16;
	4997	+ splice_yrgb_offset = drm_format_info_min_pitch(fb->format, 0, splice_pixel_offset);
	4998	+ if (fb->format->is_yuv && fb->format->num_planes > 1) {
	4999	+ hsub = fb->format->hsub;
	5000	+ splice_uv_offset = drm_format_info_min_pitch(fb->format, 1, splice_pixel_offset / hsub);
	5001	+ }
	5002	+ }
	5003	+
	5004	+ if (dst->x1 + dsp_w > adjusted_mode->crtc_hdisplay) {
	5005	+ DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
	5006	+ vp->id, win->name, dst->x1, dsp_w, adjusted_mode->crtc_hdisplay);
	5007	+ dsp_w = adjusted_mode->crtc_hdisplay - dst->x1;
	5008	+ if (dsp_w < 4)
	5009	+ dsp_w = 4;
	5010	+ actual_w = dsp_w * actual_w / drm_rect_width(dst);
	5011	+ }
	5012	+ dsp_h = drm_rect_height(dst);
	5013	+ if (dst->y1 + dsp_h > adjusted_mode->crtc_vdisplay) {
	5014	+ DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
	5015	+ vp->id, win->name, dst->y1, dsp_h, adjusted_mode->crtc_vdisplay);
	5016	+ dsp_h = adjusted_mode->crtc_vdisplay - dst->y1;
	5017	+ if (dsp_h < 4)
	5018	+ dsp_h = 4;
	5019	+ actual_h = dsp_h * actual_h / drm_rect_height(dst);
	5020	+ }
	5021	+
	5022	+ /*
	5023	+ * Workaround only for rk3568 vop
	5024	+ */
	5025	+ if (vop2->version == VOP_VERSION_RK3568) {
	5026	+ /*
	5027	+ * This is workaround solution for IC design:
	5028	+ * esmart can't support scale down when actual_w % 16 == 1.
	5029	+ */
	5030	+ if (!(win->feature & WIN_FEATURE_AFBDC)) {
	5031	+ if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
	5032	+ DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
	5033	+ actual_w -= 1;
	5034	+ }
	5035	+ }
	5036	+
	5037	+ if (vpstate->afbc_en && actual_w % 4) {
	5038	+ DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
	5039	+ vp->id, win->name, actual_w);
	5040	+ actual_w = ALIGN_DOWN(actual_w, 4);
	5041	+ }
	5042	+ }
	5043	+
	5044	+ act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
	5045	+ dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
	5046	+ stride = DIV_ROUND_UP(fb->pitches[0], 4);
	5047	+ dsp_stx = dst->x1;
	5048	+ dsp_sty = dst->y1;
	5049	+ dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
	5050	+
	5051	+ if (vpstate->tiled_en) {
	5052	+ if (is_vop3(vop2))
	5053	+ format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
	5054	+ else
	5055	+ format = vop2_convert_tiled_format(fb->format->format);
	5056	+ } else {
	5057	+ format = vop2_convert_format(fb->format->format);
	5058	+ }
	5059	+
	5060	+ vop2_setup_csc_mode(vp, vpstate);
	5061	+
	5062	+ afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
	5063	+
	5064	+ vop2_win_enable(win);
	5065	+ spin_lock(&vop2->reg_lock);
	5066	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_PLANE,
	5067	+ "vp%d update %s[%dx%d->%dx%d@(%d, %d)] fmt[%.4s%s] addr[%pad] by %s\n",
	5068	+ vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
	5069	+ dsp_stx, dsp_sty,
	5070	+ drm_get_format_name(fb->format->format, &format_name),
	5071	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst, current->comm);
	5072	+
	5073	+ if (vop2->version != VOP_VERSION_RK3568)
	5074	+ rk3588_vop2_win_cfg_axi(win);
	5075	+
	5076	+ if (!win->parent && !vop2_cluster_window(win) && is_vop3(vop2))
	5077	+ VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
	5078	+
	5079	+ if (vpstate->afbc_en) {
	5080	+ /* the afbc superblock is 16 x 16 */
	5081	+ afbc_format = vop2_convert_afbc_format(fb->format->format);
	5082	+ /* Enable color transform for YTR */
	5083	+ if (fb->modifier & AFBC_FORMAT_MOD_YTR)
	5084	+ afbc_format \|= (1 << 4);
	5085	+ afbc_tile_num = ALIGN(actual_w, 16) >> 4;
	5086	+
	5087	+ /* The right win should have a src offset in splice mode */
	5088	+ afbc_xoffset = (src->x1 >> 16);
	5089	+ /* AFBC pic_vir_width is count by pixel, this is different
	5090	+ * with WIN_VIR_STRIDE.
	5091	+ */
	5092	+ if (!bpp) {
	5093	+ WARN(1, "bpp is zero\n");
	5094	+ bpp = 1;
	5095	+ }
	5096	+ stride = (fb->pitches[0] << 3) / bpp;
	5097	+ if ((stride & 0x3f) &&
	5098	+ (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
	5099	+ DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
	5100	+ vp->id, win->name, stride, pstate->rotation);
	5101	+
	5102	+ rb_swap = vop2_afbc_rb_swap(fb->format->format);
	5103	+ uv_swap = vop2_afbc_uv_swap(fb->format->format);
	5104	+ vpstate->afbc_half_block_en = afbc_half_block_en;
	5105	+
	5106	+ transform_offset = vop2_afbc_transform_offset(vpstate, splice_pixel_offset);
	5107	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
	5108	+ VOP_AFBC_SET(vop2, win, format, afbc_format);
	5109	+ VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
	5110	+ VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
	5111	+
	5112	+ if (vop2->version == VOP_VERSION_RK3568)
	5113	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
	5114	+ else
	5115	+ VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
	5116	+ VOP_AFBC_SET(vop2, win, block_split_en, 0);
	5117	+ VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
	5118	+ VOP_AFBC_SET(vop2, win, pic_size, act_info);
	5119	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5120	+ VOP_AFBC_SET(vop2, win, pic_offset, (afbc_xoffset \| src->y1));
	5121	+ VOP_AFBC_SET(vop2, win, dsp_offset, (dst->x1 \| (dst->y1 << 16)));
	5122	+ VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
	5123	+ VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
	5124	+ VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5125	+ VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5126	+ VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
	5127	+ VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
	5128	+ } else {
	5129	+ VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
	5130	+ transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
	5131	+ VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
	5132	+ VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
	5133	+ VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
	5134	+ }
	5135	+
	5136	+ if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
	5137	+ act_info = swahw32(act_info);
	5138	+ actual_w = drm_rect_height(src) >> 16;
	5139	+ actual_h = drm_rect_width(src) >> 16;
	5140	+ }
	5141	+
	5142	+ yrgb_mst = vpstate->yrgb_mst + splice_yrgb_offset;
	5143	+ uv_mst = vpstate->uv_mst + splice_uv_offset;
	5144	+ /* rk3588 should set half_blocK_en to 1 in line and tile mode */
	5145	+ VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
	5146	+
	5147	+ VOP_WIN_SET(vop2, win, format, format);
	5148	+ VOP_WIN_SET(vop2, win, yrgb_mst, yrgb_mst);
	5149	+
	5150	+ rb_swap = vop2_win_rb_swap(fb->format->format);
	5151	+ uv_swap = vop2_win_uv_swap(fb->format->format);
	5152	+ if (vpstate->tiled_en) {
	5153	+ uv_swap = 1;
	5154	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5155	+ stride <<= 3;
	5156	+ else
	5157	+ stride <<= 2;
	5158	+ }
	5159	+ VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
	5160	+ VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
	5161	+
	5162	+ if (fb->format->is_yuv) {
	5163	+ uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
	5164	+ if (vpstate->tiled_en) {
	5165	+ int vsub = fb->format->vsub;
	5166	+
	5167	+ if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
	5168	+ uv_stride = uv_stride * 8 / vsub;
	5169	+ else
	5170	+ uv_stride = uv_stride * 4 / vsub;
	5171	+ VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
	5172	+ }
	5173	+
	5174	+ VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
	5175	+ VOP_WIN_SET(vop2, win, uv_mst, uv_mst);
	5176	+ }
	5177	+
	5178	+ /* tile 4x4 m0 format, y and uv is packed together */
	5179	+ if (tile_4x4_m0)
	5180	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
	5181	+ else
	5182	+ VOP_WIN_SET(vop2, win, yrgb_vir, stride);
	5183	+
	5184	+ vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
	5185	+ vop2_plane_setup_color_key(&win->base);
	5186	+ VOP_WIN_SET(vop2, win, act_info, act_info);
	5187	+ VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
	5188	+ VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
	5189	+
	5190	+ VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
	5191	+ VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
	5192	+ VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
	5193	+
	5194	+ if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
	5195	+ VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
	5196	+
	5197	+ dither_up = vop2_win_dither_up(fb->format->format);
	5198	+ VOP_WIN_SET(vop2, win, dither_up, dither_up);
	5199	+
	5200	+ VOP_WIN_SET(vop2, win, enable, 1);
	5201	+ if (vop2_cluster_window(win)) {
	5202	+ lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
	5203	+ VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
	5204	+ VOP_CLUSTER_SET(vop2, win, scl_lb_mode, lb_mode == 1 ? 3 : 0);
	5205	+ VOP_CLUSTER_SET(vop2, win, enable, 1);
	5206	+ VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1);
	5207	+ }
	5208	+ spin_unlock(&vop2->reg_lock);
	5209	+}
	5210	+
3592	5211	static void vop2_plane_atomic_update(struct drm_plane plane, struct drm_plane_state old_state)
3593	5212	{
3594	5213	struct drm_plane_state *pstate = plane->state;
3595	5214	struct drm_crtc *crtc = pstate->crtc;
3596	5215	struct vop2_win *win = to_vop2_win(plane);
	5216	+ struct vop2_win *splice_win;
3597	5217	struct vop2_video_port *vp = to_vop2_video_port(crtc);
3598	5218	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
3599		- struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
3600	5219	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
3601		- struct vop2 *vop2 = win->vop2;
3602	5220	struct drm_framebuffer *fb = pstate->fb;
3603		- uint32_t bpp = fb->format->bpp[0];
3604		- uint32_t actual_w, actual_h, dsp_w, dsp_h;
3605		- uint32_t dsp_stx, dsp_sty;
3606		- uint32_t act_info, dsp_info, dsp_st;
3607		- uint32_t format, check_size;
3608		- uint32_t afbc_format;
3609		- uint32_t rb_swap;
3610		- uint32_t uv_swap;
3611		- struct drm_rect *src = &vpstate->src;
3612		- struct drm_rect *dest = &vpstate->dest;
3613		- uint32_t afbc_tile_num;
3614		- uint32_t afbc_half_block_en;
3615		- uint32_t lb_mode;
3616		- uint32_t stride, uv_stride = 0;
3617		- uint32_t transform_offset;
3618	5221	struct drm_format_name_buf format_name;
3619		- bool dither_up;
3620		- bool tile_4x4_m0 = vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0 ? true : false;
	5222	+ struct vop2 *vop2 = win->vop2;
	5223	+ struct drm_rect wsrc;
	5224	+ struct drm_rect wdst;
	5225	+ /* right part in splice mode */
	5226	+ struct drm_rect right_wsrc;
	5227	+ struct drm_rect right_wdst;
3621	5228
3622	5229	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
	5230	+ struct drm_rect *psrc = &vpstate->src;
3623	5231	bool AFBC_flag = false;
3624	5232	struct vop_dump_list *planlist;
3625	5233	unsigned long num_pages;
3626	5234	struct page **pages;
3627		- struct rockchip_drm_fb *rk_fb;
3628	5235	struct drm_gem_object *obj;
3629	5236	struct rockchip_gem_object *rk_obj;
3630	5237
3631	5238	num_pages = 0;
3632	5239	pages = NULL;
3633		- rk_fb = to_rockchip_fb(fb);
3634		- obj = rk_fb->obj[0];
	5240	+ obj = fb->obj[0];
3635	5241	rk_obj = to_rockchip_obj(obj);
3636	5242	if (rk_obj) {
3637	5243	num_pages = rk_obj->num_pages;
..	..	@@ -3670,219 +5276,24 @@
3670	5276	vp->skip_vsync = false;
3671	5277	}
3672	5278
3673		- actual_w = drm_rect_width(src) >> 16;
3674		- actual_h = drm_rect_height(src) >> 16;
3675		- dsp_w = drm_rect_width(dest);
3676		- if (dest->x1 + dsp_w > adjusted_mode->crtc_hdisplay) {
3677		- DRM_ERROR("vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
3678		- vp->id, win->name, dest->x1, dsp_w, adjusted_mode->crtc_hdisplay);
3679		- dsp_w = adjusted_mode->hdisplay - dest->x1;
3680		- if (dsp_w < 4)
3681		- dsp_w = 4;
3682		- actual_w = dsp_w * actual_w / drm_rect_width(dest);
3683		- }
3684		- dsp_h = drm_rect_height(dest);
3685		- check_size = adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE ? adjusted_mode->vdisplay : adjusted_mode->crtc_vdisplay;
3686		- if (dest->y1 + dsp_h > check_size) {
3687		- DRM_ERROR("vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
3688		- vp->id, win->name, dest->y1, dsp_h, adjusted_mode->crtc_vdisplay);
3689		- dsp_h = adjusted_mode->vdisplay - dest->y1;
3690		- if (dsp_h < 4)
3691		- dsp_h = 4;
3692		- actual_h = dsp_h * actual_h / drm_rect_height(dest);
3693		- }
	5279	+ if (vcstate->splice_mode) {
	5280	+ DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@(%d,%d)] fmt[%.4s%s] addr[%pad]\n",
	5281	+ vp->id, win->name, drm_rect_width(&vpstate->src) >> 16,
	5282	+ drm_rect_height(&vpstate->src) >> 16,
	5283	+ drm_rect_width(&vpstate->dest), drm_rect_height(&vpstate->dest),
	5284	+ vpstate->dest.x1, vpstate->dest.y1,
	5285	+ drm_get_format_name(fb->format->format, &format_name),
	5286	+ modifier_to_string(fb->modifier), &vpstate->yrgb_mst);
3694	5287
3695		- /*
3696		- * Workaround only for rk3568 vop
3697		- */
3698		- if (vop2->version == VOP_VERSION_RK3568) {
3699		- /*
3700		- * This is workaround solution for IC design:
3701		- * esmart can't support scale down when actual_w % 16 == 1.
3702		- */
3703		- if (!(win->feature & WIN_FEATURE_AFBDC)) {
3704		- if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
3705		- DRM_WARN("vp%d %s act_w[%d] MODE 16 == 1\n", vp->id, win->name, actual_w);
3706		- actual_w -= 1;
3707		- }
3708		- }
3709		-
3710		- if (vpstate->afbc_en && actual_w % 4) {
3711		- DRM_ERROR("vp%d %s actual_w[%d] should align as 4 pixel when enable afbc\n",
3712		- vp->id, win->name, actual_w);
3713		- actual_w = ALIGN_DOWN(actual_w, 4);
3714		- }
3715		- }
3716		-
3717		- act_info = (actual_h - 1) << 16 \| ((actual_w - 1) & 0xffff);
3718		- dsp_info = (dsp_h - 1) << 16 \| ((dsp_w - 1) & 0xffff);
3719		- stride = DIV_ROUND_UP(fb->pitches[0], 4);
3720		- dsp_stx = dest->x1;
3721		- dsp_sty = dest->y1;
3722		- dsp_st = dsp_sty << 16 \| (dsp_stx & 0xffff);
3723		-
3724		- if (vpstate->tiled_en) {
3725		- if (is_vop3(vop2))
3726		- format = vop3_convert_tiled_format(fb->format->format, vpstate->tiled_en);
3727		- else
3728		- format = vop2_convert_tiled_format(fb->format->format);
	5288	+ vop2_calc_drm_rect_for_splice(vpstate, &wsrc, &wdst, &right_wsrc, &right_wdst);
	5289	+ splice_win = win->splice_win;
	5290	+ vop2_win_atomic_update(splice_win, &right_wsrc, &right_wdst, pstate);
3729	5291	} else {
3730		- format = vop2_convert_format(fb->format->format);
	5292	+ memcpy(&wsrc, &vpstate->src, sizeof(struct drm_rect));
	5293	+ memcpy(&wdst, &vpstate->dest, sizeof(struct drm_rect));
3731	5294	}
3732	5295
3733		- vop2_setup_csc_mode(vp, vpstate);
3734		- afbc_half_block_en = vop2_afbc_half_block_enable(vpstate);
3735		-
3736		- spin_lock(&vop2->reg_lock);
3737		- DRM_DEV_DEBUG(vop2->dev, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%.4s%s] addr[%pad] zpos[%d]\n",
3738		- vp->id, win->name, actual_w, actual_h, dsp_w, dsp_h,
3739		- dsp_stx, dsp_sty,
3740		- drm_get_format_name(fb->format->format, &format_name),
3741		- modifier_to_string(fb->modifier), &vpstate->yrgb_mst, vpstate->zpos);
3742		-
3743		- if (vop2->version != VOP_VERSION_RK3568)
3744		- rk3588_vop2_win_cfg_axi(win);
3745		-
3746		- if (is_vop3(vop2) && !vop2_cluster_window(win) && !win->parent)
3747		- VOP_WIN_SET(vop2, win, scale_engine_num, win->scale_engine_num);
3748		-
3749		- if (vpstate->afbc_en) {
3750		- /* the afbc superblock is 16 x 16 */
3751		- afbc_format = vop2_convert_afbc_format(fb->format->format);
3752		- /* Enable color transform for YTR */
3753		- if (fb->modifier & AFBC_FORMAT_MOD_YTR)
3754		- afbc_format \|= (1 << 4);
3755		- afbc_tile_num = ALIGN(actual_w, 16) >> 4;
3756		- /* AFBC pic_vir_width is count by pixel, this is different
3757		- * with WIN_VIR_STRIDE.
3758		- */
3759		- if (!bpp) {
3760		- WARN(1, "bpp is zero\n");
3761		- bpp = 1;
3762		- }
3763		- stride = (fb->pitches[0] << 3) / bpp;
3764		- if ((stride & 0x3f) &&
3765		- (vpstate->xmirror_en \|\| vpstate->rotate_90_en \|\| vpstate->rotate_270_en))
3766		- DRM_ERROR("vp%d %s stride[%d] must align as 64 pixel when enable xmirror/rotate_90/rotate_270[0x%x]\n",
3767		- vp->id, win->name, stride, pstate->rotation);
3768		-
3769		- rb_swap = vop2_afbc_rb_swap(fb->format->format);
3770		- uv_swap = vop2_afbc_uv_swap(fb->format->format);
3771		- /*
3772		- * This is a workaround for crazy IC design, Cluster
3773		- * and Esmart/Smart use different format configuration map:
3774		- * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
3775		- *
3776		- * This is one thing we can make the convert simple:
3777		- * AFBCD decode all the YUV data to YUV444. So we just
3778		- * set all the yuv 10 bit to YUV444_10.
3779		- */
3780		- if (fb->format->is_yuv && (bpp == 10) && (vop2->version == VOP_VERSION_RK3568))
3781		- format = VOP2_CLUSTER_YUV444_10;
3782		-
3783		- vpstate->afbc_half_block_en = afbc_half_block_en;
3784		- transform_offset = vop2_afbc_transform_offset(vpstate);
3785		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 1);
3786		- VOP_AFBC_SET(vop2, win, format, afbc_format);
3787		- VOP_AFBC_SET(vop2, win, rb_swap, rb_swap);
3788		- VOP_AFBC_SET(vop2, win, uv_swap, uv_swap);
3789		- if (vop2->version == VOP_VERSION_RK3568)
3790		- VOP_AFBC_SET(vop2, win, auto_gating_en, 0);
3791		- else
3792		- VOP_AFBC_SET(vop2, win, auto_gating_en, 1);
3793		- VOP_AFBC_SET(vop2, win, block_split_en, 0);
3794		- VOP_AFBC_SET(vop2, win, hdr_ptr, vpstate->yrgb_mst);
3795		- VOP_AFBC_SET(vop2, win, pic_size, act_info);
3796		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3797		- VOP_AFBC_SET(vop2, win, pic_offset, ((src->x1 >> 16) \| src->y1));
3798		- VOP_AFBC_SET(vop2, win, dsp_offset, (dest->x1 \| (dest->y1 << 16)));
3799		- VOP_AFBC_SET(vop2, win, pic_vir_width, stride);
3800		- VOP_AFBC_SET(vop2, win, tile_num, afbc_tile_num);
3801		- VOP_AFBC_SET(vop2, win, xmirror, vpstate->xmirror_en);
3802		- VOP_AFBC_SET(vop2, win, ymirror, vpstate->ymirror_en);
3803		- VOP_AFBC_SET(vop2, win, rotate_270, vpstate->rotate_270_en);
3804		- VOP_AFBC_SET(vop2, win, rotate_90, vpstate->rotate_90_en);
3805		- } else {
3806		- VOP_AFBC_SET(vop2, win, enable, 0);
3807		- VOP_CLUSTER_SET(vop2, win, afbc_enable, 0);
3808		- transform_offset = vop2_tile_transform_offset(vpstate, vpstate->tiled_en);
3809		- VOP_AFBC_SET(vop2, win, transform_offset, transform_offset);
3810		- VOP_WIN_SET(vop2, win, ymirror, vpstate->ymirror_en);
3811		- VOP_WIN_SET(vop2, win, xmirror, vpstate->xmirror_en);
3812		- }
3813		-
3814		- if (vpstate->rotate_90_en \|\| vpstate->rotate_270_en) {
3815		- act_info = swahw32(act_info);
3816		- actual_w = drm_rect_height(src) >> 16;
3817		- actual_h = drm_rect_width(src) >> 16;
3818		- }
3819		- VOP_AFBC_SET(vop2, win, half_block_en, afbc_half_block_en);
3820		-
3821		- VOP_WIN_SET(vop2, win, format, format);
3822		- VOP_WIN_SET(vop2, win, yrgb_mst, vpstate->yrgb_mst);
3823		-
3824		- rb_swap = vop2_win_rb_swap(fb->format->format);
3825		- uv_swap = vop2_win_uv_swap(fb->format->format);
3826		- if (vpstate->tiled_en) {
3827		- uv_swap = 1;
3828		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3829		- stride <<= 3;
3830		- else
3831		- stride <<= 2;
3832		- }
3833		- VOP_WIN_SET(vop2, win, rb_swap, rb_swap);
3834		- VOP_WIN_SET(vop2, win, uv_swap, uv_swap);
3835		-
3836		- if (fb->format->is_yuv) {
3837		- uv_stride = DIV_ROUND_UP(fb->pitches[1], 4);
3838		- if (vpstate->tiled_en) {
3839		- int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
3840		-
3841		- if (vpstate->tiled_en == ROCKCHIP_TILED_BLOCK_SIZE_8x8)
3842		- uv_stride = uv_stride * 8 / vsub;
3843		- else
3844		- uv_stride = uv_stride * 4 / vsub;
3845		- VOP_WIN_SET(vop2, win, tile_mode, tile_4x4_m0);
3846		- }
3847		-
3848		- VOP_WIN_SET(vop2, win, uv_vir, uv_stride);
3849		- VOP_WIN_SET(vop2, win, uv_mst, vpstate->uv_mst);
3850		- }
3851		-
3852		- /* tile 4x4 m0 format, y and uv is packed together */
3853		- if (tile_4x4_m0)
3854		- VOP_WIN_SET(vop2, win, yrgb_vir, stride + uv_stride);
3855		- else
3856		- VOP_WIN_SET(vop2, win, yrgb_vir, stride);
3857		-
3858		- vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, pstate);
3859		- vop2_plane_setup_color_key(plane);
3860		- VOP_WIN_SET(vop2, win, act_info, act_info);
3861		- VOP_WIN_SET(vop2, win, dsp_info, dsp_info);
3862		- VOP_WIN_SET(vop2, win, dsp_st, dsp_st);
3863		-
3864		- VOP_WIN_SET(vop2, win, y2r_en, vpstate->y2r_en);
3865		- VOP_WIN_SET(vop2, win, r2y_en, vpstate->r2y_en);
3866		- VOP_WIN_SET(vop2, win, csc_mode, vpstate->csc_mode);
3867		-
3868		- if (win->feature & WIN_FEATURE_Y2R_13BIT_DEPTH && !vop2_cluster_window(win))
3869		- VOP_WIN_SET(vop2, win, csc_13bit_en, !!(vpstate->csc_mode & CSC_BT709L_13BIT));
3870		-
3871		- dither_up = vop2_win_dither_up(fb->format->format);
3872		- VOP_WIN_SET(vop2, win, dither_up, dither_up);
3873		-
3874		- VOP_WIN_SET(vop2, win, enable, 1);
3875		- if (vop2_cluster_window(win)) {
3876		- lb_mode = vop2_get_cluster_lb_mode(win, vpstate);
3877		- VOP_CLUSTER_SET(vop2, win, lb_mode, lb_mode);
3878		- VOP_CLUSTER_SET(vop2, win, scl_lb_mode, lb_mode == 1 ? 3 : 0);
3879		- VOP_CLUSTER_SET(vop2, win, enable, 1);
3880		- VOP_CLUSTER_SET(vop2, win, frm_reset_en, 1);
3881		- }
3882		- if (vcstate->output_if & VOP_OUTPUT_IF_BT1120 \|\|
3883		- vcstate->output_if & VOP_OUTPUT_IF_BT656)
3884		- VOP_WIN_SET(vop2, win, yuv_clip, 1);
3885		- spin_unlock(&vop2->reg_lock);
	5296	+ vop2_win_atomic_update(win, &wsrc, &wdst, pstate);
3886	5297
3887	5298	vop2->is_iommu_needed = true;
3888	5299	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
..	..	@@ -3899,18 +5310,18 @@
3899	5310	planlist->dump_info.pages = pages;
3900	5311	planlist->dump_info.offset = vpstate->offset;
3901	5312	planlist->dump_info.pitches = fb->pitches[0];
3902		- planlist->dump_info.height = actual_h;
3903		- planlist->dump_info.pixel_format = fb->format->format;
3904		- list_add_tail(&planlist->entry, &crtc->vop_dump_list_head);
	5313	+ planlist->dump_info.height = drm_rect_height(psrc) >> 16;
	5314	+ planlist->dump_info.format = fb->format;
	5315	+ list_add_tail(&planlist->entry, &vp->rockchip_crtc.vop_dump_list_head);
3905	5316	vpstate->planlist = planlist;
3906	5317	} else {
3907	5318	DRM_ERROR("can't alloc a node of planlist %p\n", planlist);
3908	5319	return;
3909	5320	}
3910		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
3911		- crtc->vop_dump_times > 0) {
3912		- vop_plane_dump(&planlist->dump_info, crtc->frame_count);
3913		- crtc->vop_dump_times--;
	5321	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	5322	+ vp->rockchip_crtc.vop_dump_times > 0) {
	5323	+ rockchip_drm_dump_plane_buffer(&planlist->dump_info, vp->rockchip_crtc.frame_count);
	5324	+ vp->rockchip_crtc.vop_dump_times--;
3914	5325	}
3915	5326	#endif
3916	5327	}
..	..	@@ -4056,11 +5467,8 @@
4056	5467	if (!vpstate)
4057	5468	return;
4058	5469
4059		- plane->state = &vpstate->base;
4060		- plane->state->plane = plane;
4061		- plane->state->zpos = win->zpos;
4062		- plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE;
4063		- plane->state->rotation = DRM_MODE_ROTATE_0;
	5470	+ __drm_atomic_helper_plane_reset(plane, &vpstate->base);
	5471	+ vpstate->base.zpos = win->zpos;
4064	5472	}
4065	5473
4066	5474	static struct drm_plane_state vop2_atomic_plane_duplicate_state(struct drm_plane plane)
..	..	@@ -4248,6 +5656,192 @@
4248	5656	spin_unlock_irqrestore(&drm->event_lock, flags);
4249	5657	}
4250	5658
	5659	+static bool vop2_crtc_line_flag_irq_is_enabled(struct vop2_video_port *vp)
	5660	+{
	5661	+ struct vop2 *vop2 = vp->vop2;
	5662	+ const struct vop2_data *vop2_data = vop2->data;
	5663	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5664	+ const struct vop_intr *intr = vp_data->intr;
	5665	+ uint32_t line_flag_irq;
	5666	+ unsigned long flags;
	5667	+
	5668	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5669	+ line_flag_irq = VOP_INTR_GET_TYPE(vop2, intr, enable, LINE_FLAG_INTR);
	5670	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5671	+
	5672	+ return !!line_flag_irq;
	5673	+}
	5674	+
	5675	+static void vop2_crtc_line_flag_irq_enable(struct vop2_video_port *vp)
	5676	+{
	5677	+ struct vop2 *vop2 = vp->vop2;
	5678	+ const struct vop2_data *vop2_data = vop2->data;
	5679	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5680	+ const struct vop_intr *intr = vp_data->intr;
	5681	+ unsigned long flags;
	5682	+
	5683	+ if (!vop2->is_enabled)
	5684	+ return;
	5685	+
	5686	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5687	+ VOP_INTR_SET_TYPE(vop2, intr, clear, LINE_FLAG_INTR, 1);
	5688	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 1);
	5689	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5690	+}
	5691	+
	5692	+static void vop2_crtc_line_flag_irq_disable(struct vop2_video_port *vp)
	5693	+{
	5694	+ struct vop2 *vop2 = vp->vop2;
	5695	+ const struct vop2_data *vop2_data = vop2->data;
	5696	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	5697	+ const struct vop_intr *intr = vp_data->intr;
	5698	+ unsigned long flags;
	5699	+
	5700	+ if (!vop2->is_enabled)
	5701	+ return;
	5702	+
	5703	+ spin_lock_irqsave(&vop2->irq_lock, flags);
	5704	+ VOP_INTR_SET_TYPE(vop2, intr, enable, LINE_FLAG_INTR, 0);
	5705	+ spin_unlock_irqrestore(&vop2->irq_lock, flags);
	5706	+}
	5707	+
	5708	+static void vop3_mcu_mode_setup(struct drm_crtc *crtc)
	5709	+{
	5710	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5711	+ struct vop2 *vop2 = vp->vop2;
	5712	+
	5713	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5714	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5715	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, vp->mcu_timing.mcu_pix_total);
	5716	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, vp->mcu_timing.mcu_cs_pst);
	5717	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, vp->mcu_timing.mcu_cs_pend);
	5718	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, vp->mcu_timing.mcu_rw_pst);
	5719	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, vp->mcu_timing.mcu_rw_pend);
	5720	+}
	5721	+
	5722	+static void vop3_mcu_bypass_mode_setup(struct drm_crtc *crtc)
	5723	+{
	5724	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5725	+ struct vop2 *vop2 = vp->vop2;
	5726	+
	5727	+ VOP_MODULE_SET(vop2, vp, mcu_type, 1);
	5728	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 1);
	5729	+ VOP_MODULE_SET(vop2, vp, mcu_pix_total, 53);
	5730	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pst, 6);
	5731	+ VOP_MODULE_SET(vop2, vp, mcu_cs_pend, 48);
	5732	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pst, 12);
	5733	+ VOP_MODULE_SET(vop2, vp, mcu_rw_pend, 30);
	5734	+}
	5735	+
	5736	+static u32 vop3_mode_done(struct vop2_video_port *vp)
	5737	+{
	5738	+ return VOP_MODULE_GET(vp->vop2, vp, out_mode);
	5739	+}
	5740	+
	5741	+static void vop3_set_out_mode(struct drm_crtc *crtc, u32 out_mode)
	5742	+{
	5743	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5744	+ struct vop2 *vop2 = vp->vop2;
	5745	+ int ret;
	5746	+ u32 val;
	5747	+
	5748	+ VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
	5749	+ vop2_cfg_done(crtc);
	5750	+ ret = readx_poll_timeout(vop3_mode_done, vp, val, val == out_mode,
	5751	+ 1000, 500 * 1000);
	5752	+ if (ret)
	5753	+ dev_err(vop2->dev, "wait mode 0x%x timeout\n", out_mode);
	5754	+}
	5755	+
	5756	+static void vop3_crtc_send_mcu_cmd(struct drm_crtc *crtc, u32 type, u32 value)
	5757	+{
	5758	+ struct drm_crtc_state *crtc_state;
	5759	+ struct drm_display_mode *adjusted_mode;
	5760	+ struct vop2_video_port *vp;
	5761	+ struct vop2 *vop2;
	5762	+
	5763	+ if (!crtc)
	5764	+ return;
	5765	+
	5766	+ crtc_state = crtc->state;
	5767	+ adjusted_mode = &crtc_state->adjusted_mode;
	5768	+ vp = to_vop2_video_port(crtc);
	5769	+ vop2 = vp->vop2;
	5770	+
	5771	+ /*
	5772	+ * 1.set mcu bypass mode timing.
	5773	+ * 2.set dclk rate to 150M.
	5774	+ */
	5775	+ if ((type == MCU_SETBYPASS) && value) {
	5776	+ vop3_mcu_bypass_mode_setup(crtc);
	5777	+ clk_set_rate(vp->dclk, 150000000);
	5778	+ }
	5779	+
	5780	+ mutex_lock(&vop2->vop2_lock);
	5781	+ if (vop2 && vop2->is_enabled) {
	5782	+ switch (type) {
	5783	+ case MCU_WRCMD:
	5784	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 0);
	5785	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5786	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5787	+ break;
	5788	+ case MCU_WRDATA:
	5789	+ VOP_MODULE_SET(vop2, vp, mcu_rs, 1);
	5790	+ VOP_MODULE_SET(vop2, vp, mcu_rw_bypass_port, value);
	5791	+ break;
	5792	+ case MCU_SETBYPASS:
	5793	+ VOP_MODULE_SET(vop2, vp, mcu_bypass, value ? 1 : 0);
	5794	+ break;
	5795	+ default:
	5796	+ break;
	5797	+ }
	5798	+ }
	5799	+ mutex_unlock(&vop2->vop2_lock);
	5800	+
	5801	+ /*
	5802	+ * 1.restore mcu data mode timing.
	5803	+ * 2.restore dclk rate to crtc_clock.
	5804	+ */
	5805	+ if ((type == MCU_SETBYPASS) && !value) {
	5806	+ vop3_mcu_mode_setup(crtc);
	5807	+ clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	5808	+ }
	5809	+}
	5810	+
	5811	+static int vop2_crtc_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
	5812	+{
	5813	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5814	+ struct vop2 *vop2 = vp->vop2;
	5815	+ unsigned long jiffies_left;
	5816	+ int ret = 0;
	5817	+
	5818	+ if (!vop2->is_enabled)
	5819	+ return -ENODEV;
	5820	+
	5821	+ mutex_lock(&vop2->vop2_lock);
	5822	+
	5823	+ if (vop2_crtc_line_flag_irq_is_enabled(vp)) {
	5824	+ ret = -EBUSY;
	5825	+ goto out;
	5826	+ }
	5827	+
	5828	+ reinit_completion(&vp->line_flag_completion);
	5829	+ vop2_crtc_line_flag_irq_enable(vp);
	5830	+ jiffies_left = wait_for_completion_timeout(&vp->line_flag_completion,
	5831	+ msecs_to_jiffies(mstimeout));
	5832	+ vop2_crtc_line_flag_irq_disable(vp);
	5833	+
	5834	+ if (jiffies_left == 0) {
	5835	+ DRM_DEV_ERROR(vop2->dev, "timeout waiting for lineflag IRQ\n");
	5836	+ ret = -ETIMEDOUT;
	5837	+ goto out;
	5838	+ }
	5839	+
	5840	+out:
	5841	+ mutex_unlock(&vop2->vop2_lock);
	5842	+ return ret;
	5843	+}
	5844	+
4251	5845	static int vop2_crtc_enable_line_flag_event(struct drm_crtc *crtc, uint32_t line)
4252	5846	{
4253	5847	struct vop2_video_port *vp = to_vop2_video_port(crtc);
..	..	@@ -4291,20 +5885,69 @@
4291	5885	spin_unlock_irqrestore(&vop2->irq_lock, flags);
4292	5886	}
4293	5887
4294		-
4295	5888	static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on)
4296	5889	{
4297	5890	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	5891	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4298	5892	struct vop2 *vop2 = vp->vop2;
4299	5893	struct rockchip_drm_private *private = crtc->dev->dev_private;
	5894	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	5895	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	5896	+ struct drm_crtc_state *crtc_state;
	5897	+ struct drm_display_mode *mode;
	5898	+ struct vop2_win win, splice_win;
	5899	+ struct vop2_extend_pll *ext_pll;
	5900	+ struct clk *parent_clk;
	5901	+ const char *clk_name;
4300	5902
4301	5903	if (on == vp->loader_protect)
4302	5904	return 0;
4303	5905
4304	5906	if (on) {
	5907	+ vp->loader_protect = true;
4305	5908	vop2->active_vp_mask \|= BIT(vp->id);
4306	5909	vop2_set_system_status(vop2);
4307	5910	vop2_initial(crtc);
	5911	+ if (crtc->primary) {
	5912	+ win = to_vop2_win(crtc->primary);
	5913	+ if (VOP_WIN_GET(vop2, win, enable)) {
	5914	+ if (win->pd) {
	5915	+ win->pd->ref_count++;
	5916	+ win->pd->vp_mask \|= BIT(vp->id);
	5917	+ }
	5918	+
	5919	+ crtc_state = drm_atomic_get_crtc_state(crtc->state->state, crtc);
	5920	+ mode = &crtc_state->adjusted_mode;
	5921	+ if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	5922	+ vcstate->splice_mode = true;
	5923	+ splice_win = vop2_find_win_by_phys_id(vop2,
	5924	+ win->splice_win_id);
	5925	+ splice_win->splice_mode_right = true;
	5926	+ splice_win->left_win = win;
	5927	+ win->splice_win = splice_win;
	5928	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	5929	+ splice_win->vp_mask = BIT(splice_vp->id);
	5930	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	5931	+
	5932	+ if (splice_win->pd &&
	5933	+ VOP_WIN_GET(vop2, splice_win, enable)) {
	5934	+ splice_win->pd->ref_count++;
	5935	+ splice_win->pd->vp_mask \|= BIT(splice_vp->id);
	5936	+ }
	5937	+ }
	5938	+ }
	5939	+ }
	5940	+ parent_clk = clk_get_parent(vp->dclk);
	5941	+ clk_name = __clk_get_name(parent_clk);
	5942	+ if (!strcmp(clk_name, "clk_hdmiphy_pixel0")) {
	5943	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll");
	5944	+ if (ext_pll)
	5945	+ ext_pll->vp_mask \|= BIT(vp->id);
	5946	+ } else if (!strcmp(clk_name, "clk_hdmiphy_pixel1")) {
	5947	+ ext_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll");
	5948	+ if (ext_pll)
	5949	+ ext_pll->vp_mask \|= BIT(vp->id);
	5950	+ }
4308	5951	drm_crtc_vblank_on(crtc);
4309	5952	if (private->cubic_lut[vp->id].enable) {
4310	5953	dma_addr_t cubic_lut_mst;
..	..	@@ -4313,10 +5956,8 @@
4313	5956	cubic_lut_mst = cubic_lut->offset + private->cubic_lut_dma_addr;
4314	5957	VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
4315	5958	}
4316		- vp->loader_protect = true;
4317	5959	} else {
4318	5960	vop2_crtc_atomic_disable(crtc, NULL);
4319		- vp->loader_protect = false;
4320	5961	}
4321	5962
4322	5963	return 0;
..	..	@@ -4338,6 +5979,10 @@
4338	5979	struct drm_rect src, dest;
4339	5980	struct drm_framebuffer *fb = pstate->fb;
4340	5981	struct drm_format_name_buf format_name;
	5982	+ struct drm_gem_object *obj;
	5983	+ struct rockchip_gem_object *rk_obj;
	5984	+ dma_addr_t fb_addr;
	5985	+
4341	5986	int i;
4342	5987
4343	5988	DEBUG_PRINT(" %s: %s\n", win->name, pstate->crtc ? "ACTIVE" : "DISABLED");
..	..	@@ -4368,8 +6013,10 @@
4368	6013	DEBUG_PRINT("\tdst: pos[%d, %d] rect[%d x %d]\n", dest->x1, dest->y1,
4369	6014	drm_rect_width(dest), drm_rect_height(dest));
4370	6015
4371		- for (i = 0; i < drm_format_num_planes(fb->format->format); i++) {
4372		- dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
	6016	+ for (i = 0; i < fb->format->num_planes; i++) {
	6017	+ obj = fb->obj[0];
	6018	+ rk_obj = to_rockchip_obj(obj);
	6019	+ fb_addr = rk_obj->dma_addr + fb->offsets[0];
4373	6020
4374	6021	DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
4375	6022	i, &fb_addr, fb->pitches[i], fb->offsets[i]);
..	..	@@ -4449,8 +6096,8 @@
4449	6096
4450	6097	/* only need to dump once at first active crtc for vop2 */
4451	6098	for (i = 0; i < vop2_data->nr_vps; i++) {
4452		- if (vop2->vps[i].crtc.state->active) {
4453		- first_active_crtc = &vop2->vps[i].crtc;
	6099	+ if (vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6100	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4454	6101	break;
4455	6102	}
4456	6103	}
..	..	@@ -4492,8 +6139,8 @@
4492	6139
4493	6140	/* only need to dump once at first active crtc for vop2 */
4494	6141	for (i = 0; i < vop2_data->nr_vps; i++) {
4495		- if (vop2->vps[i].crtc.state->active) {
4496		- first_active_crtc = &vop2->vps[i].crtc;
	6142	+ if (vop2->vps[i].rockchip_crtc.crtc.state->active) {
	6143	+ first_active_crtc = &vop2->vps[i].rockchip_crtc.crtc;
4497	6144	break;
4498	6145	}
4499	6146	}
..	..	@@ -4529,7 +6176,7 @@
4529	6176	struct vop2_video_port *vp = &vop2->vps[i];
4530	6177
4531	6178	if (!vp->lut \|\| !vp->gamma_lut_active \|\|
4532		- !vop2->lut_regs \|\| !vp->crtc.state->enable) {
	6179	+ !vop2->lut_regs \|\| !vp->rockchip_crtc.crtc.state->enable) {
4533	6180	DEBUG_PRINT("Video port%d gamma disabled\n", vp->id);
4534	6181	continue;
4535	6182	}
..	..	@@ -4556,7 +6203,7 @@
4556	6203	struct vop2_video_port *vp = &vop2->vps[i];
4557	6204
4558	6205	if ((!vp->cubic_lut_gem_obj && !private->cubic_lut[vp->id].enable) \|\|
4559		- !vp->cubic_lut \|\| !vp->crtc.state->enable) {
	6206	+ !vp->cubic_lut \|\| !vp->rockchip_crtc.crtc.state->enable) {
4560	6207	DEBUG_PRINT("Video port%d cubic lut disabled\n", vp->id);
4561	6208	continue;
4562	6209	}
..	..	@@ -4599,24 +6246,17 @@
4599	6246	goto remove;
4600	6247	}
4601	6248	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4602		- drm_debugfs_vop_add(crtc, vop2->debugfs);
	6249	+ rockchip_drm_add_dump_buffer(crtc, vop2->debugfs);
	6250	+ rockchip_drm_debugfs_add_color_bar(crtc, vop2->debugfs);
4603	6251	#endif
4604	6252	for (i = 0; i < ARRAY_SIZE(vop2_debugfs_files); i++)
4605	6253	vop2->debugfs_files[i].data = vop2;
4606	6254
4607		- ret = drm_debugfs_create_files(vop2->debugfs_files,
4608		- ARRAY_SIZE(vop2_debugfs_files),
4609		- vop2->debugfs,
4610		- minor);
4611		- if (ret) {
4612		- dev_err(vop2->dev, "could not install rockchip_debugfs_list\n");
4613		- goto free;
4614		- }
4615		-
	6255	+ drm_debugfs_create_files(vop2->debugfs_files,
	6256	+ ARRAY_SIZE(vop2_debugfs_files),
	6257	+ vop2->debugfs,
	6258	+ minor);
4616	6259	return 0;
4617		-free:
4618		- kfree(vop2->debugfs_files);
4619		- vop2->debugfs_files = NULL;
4620	6260	remove:
4621	6261	debugfs_remove(vop2->debugfs);
4622	6262	vop2->debugfs = NULL;
..	..	@@ -4624,29 +6264,59 @@
4624	6264	}
4625	6265
4626	6266	static enum drm_mode_status
4627		-vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode,
4628		- int output_type)
	6267	+vop2_crtc_mode_valid(struct drm_crtc crtc, const struct drm_display_mode mode)
4629	6268	{
	6269	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
4630	6270	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4631	6271	struct vop2 *vop2 = vp->vop2;
4632	6272	const struct vop2_data *vop2_data = vop2->data;
4633	6273	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
4634	6274	int request_clock = mode->clock;
4635	6275	int clock;
	6276	+ unsigned long aclk_rate;
	6277	+ uint8_t active_vp_mask = vop2->active_vp_mask;
	6278	+
	6279	+ /*
	6280	+ * For RK3588, VP0 and VP1 will be both used in splice mode. All display
	6281	+ * modes of the right VP should be set as invalid when vop2 is working in
	6282	+ * splice mode.
	6283	+ */
	6284	+ if (vp->splice_mode_right)
	6285	+ return MODE_BAD;
	6286	+
	6287	+ if ((active_vp_mask & BIT(ROCKCHIP_VOP_VP1)) && !vcstate->splice_mode &&
	6288	+ mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	6289	+ DRM_DEV_DEBUG(vop2->dev, "can not support resolution %dx%d, vp1 is busy\n",
	6290	+ mode->hdisplay, mode->vdisplay);
	6291	+ return MODE_BAD;
	6292	+ }
4636	6293
4637	6294	if (mode->hdisplay > vp_data->max_output.width)
4638	6295	return MODE_BAD_HVALUE;
4639	6296
4640		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6297	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4641	6298	request_clock *= 2;
4642	6299
4643		- clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
	6300	+ aclk_rate = clk_get_rate(vop2->aclk) / 1000;
	6301	+
	6302	+ if (request_clock > VOP2_MAX_DCLK_RATE && aclk_rate <= VOP2_COMMON_ACLK_RATE)
	6303	+ return MODE_BAD;
	6304	+
	6305	+ if ((request_clock <= VOP2_MAX_DCLK_RATE) &&
	6306	+ (vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") \|\|
	6307	+ vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"))) {
	6308	+ clock = request_clock;
	6309	+ } else {
	6310	+ if (request_clock > VOP2_MAX_DCLK_RATE)
	6311	+ request_clock = request_clock >> 2;
	6312	+ clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000;
	6313	+ }
4644	6314
4645	6315	/*
4646	6316	* Hdmi or DisplayPort request a Accurate clock.
4647	6317	*/
4648		- if (output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
4649		- output_type == DRM_MODE_CONNECTOR_DisplayPort)
	6318	+ if (vcstate->output_type == DRM_MODE_CONNECTOR_HDMIA \|\|
	6319	+ vcstate->output_type == DRM_MODE_CONNECTOR_DisplayPort)
4650	6320	if (clock != request_clock)
4651	6321	return MODE_CLOCK_RANGE;
4652	6322
..	..	@@ -4673,7 +6343,7 @@
4673	6343	struct drm_framebuffer *fb = pstate->fb;
4674	6344	struct drm_rect *dst = &vpstate->dest;
4675	6345	struct drm_rect *src = &vpstate->src;
4676		- int bpp = fb->format->bpp[0];
	6346	+ int bpp = rockchip_drm_get_bpp(fb->format);
4677	6347	int src_width = drm_rect_width(src) >> 16;
4678	6348	int src_height = drm_rect_height(src) >> 16;
4679	6349	int dst_width = drm_rect_width(dst);
..	..	@@ -4721,10 +6391,9 @@
4721	6391
4722	6392	static size_t vop2_crtc_bandwidth(struct drm_crtc *crtc,
4723	6393	struct drm_crtc_state *crtc_state,
4724		- size_t *frame_bw_mbyte,
4725		- unsigned int *plane_num_total)
	6394	+ struct dmcfreq_vop_info *vop_bw_info)
4726	6395	{
4727		- struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
	6396	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
4728	6397	uint16_t htotal = adjusted_mode->crtc_htotal;
4729	6398	uint16_t vdisplay = adjusted_mode->crtc_vdisplay;
4730	6399	int clock = adjusted_mode->crtc_clock;
..	..	@@ -4733,44 +6402,49 @@
4733	6402	struct drm_plane_state *pstate;
4734	6403	struct vop2_bandwidth *pbandwidth;
4735	6404	struct drm_plane *plane;
4736		- uint64_t line_bandwidth;
	6405	+ u64 line_bw_mbyte = 0;
4737	6406	int8_t cnt = 0, plane_num = 0;
	6407	+ int i = 0;
4738	6408	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4739	6409	struct vop_dump_list pos, n;
	6410	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
4740	6411	#endif
4741	6412
4742	6413	if (!htotal \|\| !vdisplay)
4743	6414	return 0;
4744	6415
4745	6416	#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
4746		- if (!crtc->vop_dump_list_init_flag) {
4747		- INIT_LIST_HEAD(&crtc->vop_dump_list_head);
4748		- crtc->vop_dump_list_init_flag = true;
	6417	+ if (!vp->rockchip_crtc.vop_dump_list_init_flag) {
	6418	+ INIT_LIST_HEAD(&vp->rockchip_crtc.vop_dump_list_head);
	6419	+ vp->rockchip_crtc.vop_dump_list_init_flag = true;
4749	6420	}
4750		- list_for_each_entry_safe(pos, n, &crtc->vop_dump_list_head, entry) {
	6421	+ list_for_each_entry_safe(pos, n, &vp->rockchip_crtc.vop_dump_list_head, entry) {
4751	6422	list_del(&pos->entry);
4752	6423	}
4753		- if (crtc->vop_dump_status == DUMP_KEEP \|\|
4754		- crtc->vop_dump_times > 0) {
4755		- crtc->frame_count++;
	6424	+ if (vp->rockchip_crtc.vop_dump_status == DUMP_KEEP \|\|
	6425	+ vp->rockchip_crtc.vop_dump_times > 0) {
	6426	+ vp->rockchip_crtc.frame_count++;
4756	6427	}
4757	6428	#endif
4758	6429
4759		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
4760		- plane_num++;
	6430	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6431	+ if (pstate->crtc == crtc)
	6432	+ plane_num++;
	6433	+ }
4761	6434
4762		- if (plane_num_total)
4763		- *plane_num_total += plane_num;
	6435	+ vop_bw_info->plane_num += plane_num;
4764	6436	pbandwidth = kmalloc_array(plane_num, sizeof(*pbandwidth),
4765	6437	GFP_KERNEL);
4766	6438	if (!pbandwidth)
4767	6439	return -ENOMEM;
4768		- drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
4769		- int act_w, act_h, bpp, afbc_fac;
4770	6440
4771		- pstate = drm_atomic_get_new_plane_state(state, plane);
	6441	+ for_each_new_plane_in_state(state, plane, pstate, i) {
	6442	+ int act_w, act_h, bpp, afbc_fac;
	6443	+ int fps = drm_mode_vrefresh(adjusted_mode);
	6444	+
4772	6445	if (!pstate \|\| pstate->crtc != crtc \|\| !pstate->fb)
4773	6446	continue;
	6447	+
4774	6448	/* This is an empirical value, if it's afbc format, the frame buffer size div 2 */
4775	6449	afbc_fac = rockchip_afbc(plane, pstate->fb->modifier) ? 2 : 1;
4776	6450
..	..	@@ -4781,24 +6455,25 @@
4781	6455
4782	6456	act_w = drm_rect_width(&pstate->src) >> 16;
4783	6457	act_h = drm_rect_height(&pstate->src) >> 16;
4784		- bpp = pstate->fb->format->bpp[0];
	6458	+ bpp = rockchip_drm_get_bpp(pstate->fb->format);
4785	6459
4786		- frame_bw_mbyte += act_w act_h / 1000 * bpp / 8 * adjusted_mode->vrefresh / afbc_fac / 1000;
	6460	+ vop_bw_info->frame_bw_mbyte += act_w * act_h / 1000 * bpp / 8 * fps / 1000;
4787	6461	}
4788	6462
4789	6463	sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop2_bandwidth_cmp, NULL);
4790	6464
4791		- line_bandwidth = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
	6465	+ line_bw_mbyte = vop2_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
4792	6466	kfree(pbandwidth);
4793	6467	/*
4794	6468	* line_bandwidth(MB/s)
4795		- * = line_bandwidth(Byte) / line_time(s)
	6469	+ * = line_bandwidth / line_time
4796	6470	* = line_bandwidth(Byte) * clock(KHZ) / 1000 / htotal
4797	6471	*/
4798		- line_bandwidth *= clock;
4799		- do_div(line_bandwidth, htotal * 1000);
	6472	+ line_bw_mbyte *= clock;
	6473	+ do_div(line_bw_mbyte, htotal * 1000);
	6474	+ vop_bw_info->line_bw_mbyte = line_bw_mbyte;
4800	6475
4801		- return line_bandwidth;
	6476	+ return 0;
4802	6477	}
4803	6478
4804	6479	static void vop2_crtc_close(struct drm_crtc *crtc)
..	..	@@ -4830,6 +6505,44 @@
4830	6505	VOP_MODULE_SET(vop2, vp, edpi_wms_fs, 1);
4831	6506	}
4832	6507
	6508	+static int vop2_crtc_set_color_bar(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode)
	6509	+{
	6510	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6511	+ struct vop2 *vop2 = vp->vop2;
	6512	+ int ret = 0;
	6513	+
	6514	+ if (!crtc->state->active) {
	6515	+ DRM_INFO("Video port%d disabled\n", vp->id);
	6516	+ return -EINVAL;
	6517	+ }
	6518	+
	6519	+ switch (mode) {
	6520	+ case ROCKCHIP_COLOR_BAR_OFF:
	6521	+ DRM_INFO("disable color bar in VP%d\n", vp->id);
	6522	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 0);
	6523	+ vop2_cfg_done(crtc);
	6524	+ break;
	6525	+ case ROCKCHIP_COLOR_BAR_HORIZONTAL:
	6526	+ DRM_INFO("enable horizontal color bar in VP%d\n", vp->id);
	6527	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 0);
	6528	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6529	+ vop2_cfg_done(crtc);
	6530	+ break;
	6531	+ case ROCKCHIP_COLOR_BAR_VERTICAL:
	6532	+ DRM_INFO("enable vertical color bar in VP%d\n", vp->id);
	6533	+ VOP_MODULE_SET(vop2, vp, color_bar_mode, 1);
	6534	+ VOP_MODULE_SET(vop2, vp, color_bar_en, 1);
	6535	+ vop2_cfg_done(crtc);
	6536	+ break;
	6537	+ default:
	6538	+ DRM_INFO("Unsupported color bar mode\n");
	6539	+ ret = -EINVAL;
	6540	+ break;
	6541	+ }
	6542	+
	6543	+ return ret;
	6544	+}
	6545	+
4833	6546	static const struct rockchip_crtc_funcs private_crtc_funcs = {
4834	6547	.loader_protect = vop2_crtc_loader_protect,
4835	6548	.cancel_pending_vblank = vop2_crtc_cancel_pending_vblank,
..	..	@@ -4837,10 +6550,13 @@
4837	6550	.debugfs_dump = vop2_crtc_debugfs_dump,
4838	6551	.regs_dump = vop2_crtc_regs_dump,
4839	6552	.active_regs_dump = vop2_crtc_active_regs_dump,
4840		- .mode_valid = vop2_crtc_mode_valid,
4841	6553	.bandwidth = vop2_crtc_bandwidth,
4842	6554	.crtc_close = vop2_crtc_close,
4843	6555	.te_handler = vop2_crtc_te_handler,
	6556	+ .crtc_send_mcu_cmd = vop3_crtc_send_mcu_cmd,
	6557	+ .wait_vact_end = vop2_crtc_wait_vact_end,
	6558	+ .crtc_standby = vop2_crtc_standby,
	6559	+ .crtc_set_color_bar = vop2_crtc_set_color_bar,
4844	6560	};
4845	6561
4846	6562	static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
..	..	@@ -4849,6 +6565,10 @@
4849	6565	{
4850	6566	struct vop2_video_port *vp = to_vop2_video_port(crtc);
4851	6567	struct vop2 *vop2 = vp->vop2;
	6568	+ struct drm_connector *connector;
	6569	+ struct drm_connector_list_iter conn_iter;
	6570	+ struct drm_crtc_state *new_crtc_state = container_of(mode, struct drm_crtc_state, mode);
	6571	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(new_crtc_state);
4852	6572
4853	6573	/*
4854	6574	* For RK3568 and RK3588, the hactive of video timing must
..	..	@@ -4872,12 +6592,30 @@
4872	6592
4873	6593	drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V \| CRTC_STEREO_DOUBLE);
4874	6594
4875		- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
	6595	+ if (mode->flags & DRM_MODE_FLAG_DBLCLK \|\| vcstate->output_if & VOP_OUTPUT_IF_BT656)
4876	6596	adj_mode->crtc_clock *= 2;
4877	6597
4878		- adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
4879		- adj_mode->crtc_clock * 1000), 1000);
	6598	+ if (vp->mcu_timing.mcu_pix_total) {
	6599	+ if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888)
	6600	+ adj_mode->crtc_clock *= 3;
	6601	+ else if (vcstate->output_mode == ROCKCHIP_OUT_MODE_S888_DUMMY)
	6602	+ adj_mode->crtc_clock *= 4;
	6603	+ }
4880	6604
	6605	+ drm_connector_list_iter_begin(crtc->dev, &conn_iter);
	6606	+ drm_for_each_connector_iter(connector, &conn_iter) {
	6607	+ if ((new_crtc_state->connector_mask & drm_connector_mask(connector)) &&
	6608	+ ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) \|\|
	6609	+ (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA))) {
	6610	+ drm_connector_list_iter_end(&conn_iter);
	6611	+ return true;
	6612	+ }
	6613	+ }
	6614	+ drm_connector_list_iter_end(&conn_iter);
	6615	+
	6616	+ if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE)
	6617	+ adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk,
	6618	+ adj_mode->crtc_clock * 1000), 1000);
4881	6619	return true;
4882	6620	}
4883	6621
..	..	@@ -4896,24 +6634,25 @@
4896	6634	case MEDIA_BUS_FMT_RGB666_1X18:
4897	6635	case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
4898	6636	case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
4899		- case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
4900	6637	VOP_MODULE_SET(vop2, vp, dither_down_en, 1);
4901	6638	VOP_MODULE_SET(vop2, vp, dither_down_mode, RGB888_TO_RGB666);
4902	6639	VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
4903	6640	break;
	6641	+ case MEDIA_BUS_FMT_YUYV8_1X16:
4904	6642	case MEDIA_BUS_FMT_YUV8_1X24:
4905	6643	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
4906	6644	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4907	6645	VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 1);
4908	6646	break;
	6647	+ case MEDIA_BUS_FMT_YUYV10_1X20:
4909	6648	case MEDIA_BUS_FMT_YUV10_1X30:
4910	6649	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
4911	6650	case MEDIA_BUS_FMT_RGB101010_1X30:
4912	6651	VOP_MODULE_SET(vop2, vp, dither_down_en, 0);
4913	6652	VOP_MODULE_SET(vop2, vp, pre_dither_down_en, 0);
4914	6653	break;
4915		- case MEDIA_BUS_FMT_SRGB888_3X8:
4916		- case MEDIA_BUS_FMT_SRGB888_DUMMY_4X8:
	6654	+ case MEDIA_BUS_FMT_RGB888_3X8:
	6655	+ case MEDIA_BUS_FMT_RGB888_DUMMY_4X8:
4917	6656	case MEDIA_BUS_FMT_RGB888_1X24:
4918	6657	case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
4919	6658	case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
..	..	@@ -5009,18 +6748,598 @@
5009	6748	u16 vact_end = vact_st + vdisplay;
5010	6749	u32 htotal_sync = htotal << 16 \| hsync_len;
5011	6750	u32 hactive_st_end = hact_st << 16 \| hact_end;
5012		- u32 vtotal_sync = vtotal << 16 \| vsync_len;
5013	6751	u32 vactive_st_end = vact_st << 16 \| vact_end;
5014	6752	u32 crtc_clock = adjusted_mode->crtc_clock * 100;
5015	6753
5016	6754	if (htotal_sync != VOP_MODULE_GET(vop2, vp, htotal_pw) \|\|
5017	6755	hactive_st_end != VOP_MODULE_GET(vop2, vp, hact_st_end) \|\|
5018		- vtotal_sync != VOP_MODULE_GET(vop2, vp, vtotal_pw) \|\|
	6756	+ vtotal != VOP_MODULE_GET(vop2, vp, dsp_vtotal) \|\|
	6757	+ vsync_len != VOP_MODULE_GET(vop2, vp, dsp_vs_end) \|\|
5019	6758	vactive_st_end != VOP_MODULE_GET(vop2, vp, vact_st_end) \|\|
5020	6759	crtc_clock != clk_get_rate(vp->dclk))
5021	6760	return true;
5022	6761
5023	6762	return false;
	6763	+}
	6764	+
	6765	+static int vop2_cru_set_rate(struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	6766	+{
	6767	+ int ret = 0;
	6768	+
	6769	+ if (if_pixclk) {
	6770	+ ret = clk_set_rate(if_pixclk->hw.clk, if_pixclk->rate);
	6771	+ if (ret < 0) {
	6772	+ DRM_DEV_ERROR(if_pixclk->vop2->dev, "set %s to %ld failed: %d\n",
	6773	+ clk_hw_get_name(&if_pixclk->hw), if_pixclk->rate, ret);
	6774	+ return ret;
	6775	+ }
	6776	+ }
	6777	+
	6778	+ if (if_dclk) {
	6779	+ ret = clk_set_rate(if_dclk->hw.clk, if_dclk->rate);
	6780	+ if (ret < 0)
	6781	+ DRM_DEV_ERROR(if_dclk->vop2->dev, "set %s to %ld failed %d\n",
	6782	+ clk_hw_get_name(&if_dclk->hw), if_dclk->rate, ret);
	6783	+ }
	6784	+
	6785	+ return ret;
	6786	+}
	6787	+
	6788	+static int vop2_set_dsc_clk(struct drm_crtc *crtc, u8 dsc_id)
	6789	+{
	6790	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6791	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6792	+ struct vop2 *vop2 = vp->vop2;
	6793	+ const struct vop2_data *vop2_data = vop2->data;
	6794	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	6795	+ struct vop2_clk dsc_txp_clk, dsc_pxl_clk, dsc_cds_clk, dsc_txp_clk_parent;
	6796	+ char clk_name[32];
	6797	+ int ret = 0;
	6798	+
	6799	+ /* set clk parent */
	6800	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	6801	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_src_name);
	6802	+ dsc_txp_clk_parent = vop2_clk_get(vop2, clk_name);
	6803	+ if (!dsc_txp_clk \|\| !dsc_txp_clk_parent) {
	6804	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc clk\n");
	6805	+ return -ENODEV;
	6806	+ }
	6807	+ ret = clk_set_parent(dsc_txp_clk->hw.clk, dsc_txp_clk_parent->hw.clk);
	6808	+ if (ret < 0) {
	6809	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	6810	+ __clk_get_name(dsc_txp_clk_parent->hw.clk),
	6811	+ __clk_get_name(dsc_txp_clk->hw.clk), ret);
	6812	+ return ret;
	6813	+ }
	6814	+
	6815	+ /* set dsc txp clk rate */
	6816	+ clk_set_rate(dsc_txp_clk->hw.clk, vcstate->dsc_txp_clk_rate);
	6817	+
	6818	+ /* set dsc pxl clk rate */
	6819	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	6820	+ if (!dsc_pxl_clk) {
	6821	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_pxl_clk\n");
	6822	+ return -ENODEV;
	6823	+ }
	6824	+ clk_set_rate(dsc_pxl_clk->hw.clk, vcstate->dsc_pxl_clk_rate);
	6825	+
	6826	+ /* set dsc cds clk rate */
	6827	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	6828	+ if (!dsc_cds_clk) {
	6829	+ DRM_DEV_ERROR(vop2->dev, "failed to get dsc_cds_clk\n");
	6830	+ return -ENODEV;
	6831	+ }
	6832	+ clk_set_rate(dsc_cds_clk->hw.clk, vcstate->dsc_cds_clk_rate);
	6833	+
	6834	+ return 0;
	6835	+}
	6836	+
	6837	+static int vop2_calc_if_clk(struct drm_crtc crtc, const struct vop2_connector_if_data if_data,
	6838	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk, int conn_id)
	6839	+{
	6840	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6841	+ struct vop2 *vop2 = vp->vop2;
	6842	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	6843	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6844	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	6845	+ unsigned long dclk_core_rate, dclk_out_rate = 0;
	6846	+ /conn_dclk = conn_pixclk or conn_dclk = conn_pixclk / 2 /
	6847	+ u64 hdmi_edp_pixclk, hdmi_edp_dclk, mipi_pixclk;
	6848	+ char dclk_core_div_shift = 2;
	6849	+ char K = 1;
	6850	+ char clk_name[32];
	6851	+ struct vop2_clk dclk_core, dclk_out, *dclk;
	6852	+ int ret;
	6853	+ bool dsc_txp_clk_is_biggest = false;
	6854	+ u8 dsc_id = conn_id & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	6855	+
	6856	+ dclk_core_div_shift = if_data->post_proc_div_shift;
	6857	+ dclk_core_rate = v_pixclk >> dclk_core_div_shift;
	6858	+
	6859	+ if (!if_dclk && (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id)))
	6860	+ return -EINVAL;
	6861	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) &&
	6862	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420)) {
	6863	+ DRM_DEV_ERROR(vop2->dev, "Dual channel and YUV420 can't work together\n");
	6864	+ return -EINVAL;
	6865	+ }
	6866	+
	6867	+ if ((vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) \|\|
	6868	+ (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420))
	6869	+ K = 2;
	6870	+
	6871	+ if (output_if_is_hdmi(conn_id)) {
	6872	+ if (vcstate->dsc_enable) {
	6873	+ hdmi_edp_pixclk = vcstate->dsc_cds_clk_rate << 1;
	6874	+ hdmi_edp_dclk = vcstate->dsc_cds_clk_rate;
	6875	+ } else {
	6876	+ hdmi_edp_pixclk = (dclk_core_rate << 1) / K;
	6877	+ hdmi_edp_dclk = dclk_core_rate / K;
	6878	+ }
	6879	+
	6880	+ if_pixclk->rate = hdmi_edp_pixclk;
	6881	+ if_dclk->rate = hdmi_edp_dclk;
	6882	+ } else if (output_if_is_edp(conn_id)) {
	6883	+ hdmi_edp_pixclk = v_pixclk;
	6884	+ do_div(hdmi_edp_pixclk, K);
	6885	+ hdmi_edp_dclk = hdmi_edp_pixclk;
	6886	+
	6887	+ if_pixclk->rate = hdmi_edp_pixclk;
	6888	+ if_dclk->rate = hdmi_edp_dclk;
	6889	+ } else if (output_if_is_dp(conn_id)) {
	6890	+ dclk_out_rate = v_pixclk >> 2;
	6891	+ dclk_out_rate = dclk_out_rate / K;
	6892	+ if_pixclk->rate = dclk_out_rate;
	6893	+ } else if (output_if_is_mipi(conn_id)) {
	6894	+ if (vcstate->dsc_enable)
	6895	+ /* dsc output is 96bit, dsi input is 192 bit */
	6896	+ mipi_pixclk = vcstate->dsc_cds_clk_rate >> 1;
	6897	+ else
	6898	+ mipi_pixclk = dclk_core_rate / K;
	6899	+
	6900	+ dclk_out_rate = dclk_core_rate / K;
	6901	+ if_pixclk->rate = mipi_pixclk;
	6902	+ } else if (output_if_is_dpi(conn_id)) {
	6903	+ if_pixclk->rate = v_pixclk;
	6904	+ }
	6905	+
	6906	+ /*
	6907	+ * RGB/eDP/HDMI: if_pixclk >= dclk_core
	6908	+ * DP: dp_pixclk = dclk_out <= dclk_core
	6909	+ * DSI: mipi_pixclk <= dclk_out <= dclk_core
	6910	+ *
	6911	+ */
	6912	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	6913	+ dclk_core = vop2_clk_get(vop2, clk_name);
	6914	+
	6915	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	6916	+ dclk_out = vop2_clk_get(vop2, clk_name);
	6917	+
	6918	+ /*
	6919	+ * HDMI use 1:1 dclk for rgb/yuv444, 1:2 for yuv420 when
	6920	+ * pixclk <= 600
	6921	+ * We want use HDMI PHY clk as dclk source for DP/HDMI.
	6922	+ * The max freq of HDMI PHY CLK is 600 MHZ.
	6923	+ * When used for HDMI, the input freq and v_pixclk must
	6924	+ * keep 1:1 for rgb/yuv444, 1:2 for yuv420
	6925	+ */
	6926	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_dp(conn_id) \|\| output_if_is_mipi(conn_id)) {
	6927	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	6928	+ dclk = vop2_clk_get(vop2, clk_name);
	6929	+ if (v_pixclk <= (VOP2_MAX_DCLK_RATE * 1000)) {
	6930	+ if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420 \|\|
	6931	+ (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE))
	6932	+ v_pixclk = v_pixclk >> 1;
	6933	+ } else {
	6934	+ v_pixclk = v_pixclk >> 2;
	6935	+ }
	6936	+ clk_set_rate(dclk->hw.clk, v_pixclk);
	6937	+ }
	6938	+
	6939	+ if (vcstate->dsc_enable) {
	6940	+ if ((vcstate->dsc_txp_clk_rate >= dclk_core_rate) &&
	6941	+ (vcstate->dsc_txp_clk_rate >= if_pixclk->rate)) {
	6942	+ dsc_txp_clk_is_biggest = true;
	6943	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	6944	+ vop2_set_dsc_clk(crtc, 0);
	6945	+ vop2_set_dsc_clk(crtc, 1);
	6946	+ } else {
	6947	+ vop2_set_dsc_clk(crtc, dsc_id);
	6948	+ }
	6949	+ }
	6950	+ }
	6951	+
	6952	+ if (dclk_core_rate > if_pixclk->rate) {
	6953	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	6954	+ if (output_if_is_mipi(conn_id))
	6955	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	6956	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	6957	+ } else {
	6958	+ if (output_if_is_mipi(conn_id))
	6959	+ clk_set_rate(dclk_out->hw.clk, dclk_out_rate);
	6960	+ ret = vop2_cru_set_rate(if_pixclk, if_dclk);
	6961	+ clk_set_rate(dclk_core->hw.clk, dclk_core_rate);
	6962	+ }
	6963	+
	6964	+ if (!dsc_txp_clk_is_biggest && vcstate->dsc_enable) {
	6965	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	6966	+ vop2_set_dsc_clk(crtc, 0);
	6967	+ vop2_set_dsc_clk(crtc, 1);
	6968	+ } else {
	6969	+ vop2_set_dsc_clk(crtc, dsc_id);
	6970	+ }
	6971	+ }
	6972	+
	6973	+ return ret;
	6974	+}
	6975	+
	6976	+static int vop2_calc_dsc_clk(struct drm_crtc *crtc)
	6977	+{
	6978	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	6979	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	6980	+ struct vop2 *vop2 = vp->vop2;
	6981	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	6982	+ u64 v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
	6983	+ u8 k = 1;
	6984	+
	6985	+ if (!vop2->data->nr_dscs) {
	6986	+ DRM_WARN("Unsupported DSC\n");
	6987	+
	6988	+ return 0;
	6989	+ }
	6990	+
	6991	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	6992	+ k = 2;
	6993	+
	6994	+ vcstate->dsc_txp_clk_rate = v_pixclk;
	6995	+ do_div(vcstate->dsc_txp_clk_rate, (vcstate->dsc_pixel_num * k));
	6996	+
	6997	+ vcstate->dsc_pxl_clk_rate = v_pixclk;
	6998	+ do_div(vcstate->dsc_pxl_clk_rate, (vcstate->dsc_slice_num * k));
	6999	+
	7000	+ /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel)
	7001	+ * cds_dat_width = 96;
	7002	+ * bits_per_pixel = [8-12];
	7003	+ * As cds clk is div from txp clk and only support 1/2/4 div,
	7004	+ * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4,
	7005	+ * otherwise dsc_cds = crtc_clock / 8;
	7006	+ */
	7007	+ vcstate->dsc_cds_clk_rate = v_pixclk / (vcstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8);
	7008	+
	7009	+ return 0;
	7010	+}
	7011	+
	7012	+static int vop2_calc_cru_cfg(struct drm_crtc *crtc, int conn_id,
	7013	+ struct vop2_clk if_pixclk, struct vop2_clk if_dclk)
	7014	+{
	7015	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7016	+ struct vop2 *vop2 = vp->vop2;
	7017	+ const struct vop2_connector_if_data *if_data;
	7018	+ struct vop2_clk if_clk_src, if_clk_parent;
	7019	+ char clk_name[32];
	7020	+ int ret;
	7021	+
	7022	+ if (vop2->version != VOP_VERSION_RK3588)
	7023	+ return 0;
	7024	+
	7025	+ if_data = vop2_find_connector_if_data(vop2, conn_id);
	7026	+ if_clk_src = vop2_clk_get(vop2, if_data->clk_src_name);
	7027	+ snprintf(clk_name, sizeof(clk_name), "%s%d", if_data->clk_parent_name, vp->id);
	7028	+ if_clk_parent = vop2_clk_get(vop2, clk_name);
	7029	+ *if_pixclk = vop2_clk_get(vop2, if_data->pixclk_name);
	7030	+ *if_dclk = vop2_clk_get(vop2, if_data->dclk_name);
	7031	+ if (!(*if_pixclk) \|\| !if_clk_parent) {
	7032	+ DRM_DEV_ERROR(vop2->dev, "failed to get connector interface clk\n");
	7033	+ return -ENODEV;
	7034	+ }
	7035	+
	7036	+ ret = clk_set_parent(if_clk_src->hw.clk, if_clk_parent->hw.clk);
	7037	+ if (ret < 0) {
	7038	+ DRM_DEV_ERROR(vop2->dev, "failed to set parent(%s) for %s: %d\n",
	7039	+ __clk_get_name(if_clk_parent->hw.clk),
	7040	+ __clk_get_name(if_clk_src->hw.clk), ret);
	7041	+ return ret;
	7042	+ }
	7043	+
	7044	+ /* HDMI and eDP use independent if_pixclk and if_dclk, and others if_pixclk = if_dclk */
	7045	+ if (output_if_is_hdmi(conn_id) \|\| output_if_is_edp(conn_id))
	7046	+ ret = vop2_calc_if_clk(crtc, if_data, if_pixclk, if_dclk, conn_id);
	7047	+ else
	7048	+ ret = vop2_calc_if_clk(crtc, if_data, *if_pixclk, NULL, conn_id);
	7049	+
	7050	+ return ret;
	7051	+}
	7052	+
	7053	+static void vop2_crtc_load_pps(struct drm_crtc *crtc, u8 dsc_id)
	7054	+{
	7055	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7056	+ struct vop2 *vop2 = vp->vop2;
	7057	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7058	+
	7059	+ struct drm_dsc_picture_parameter_set *pps = &vcstate->pps;
	7060	+ struct drm_dsc_picture_parameter_set config_pps;
	7061	+ int i = 0;
	7062	+ u32 pps_val = (u32 )&config_pps;
	7063	+ u32 offset;
	7064	+ struct vop2_dsc *dsc;
	7065	+
	7066	+ dsc = &vop2->dscs[dsc_id];
	7067	+ offset = dsc->regs->dsc_pps0_3.offset;
	7068	+
	7069	+ memcpy(&config_pps, pps, sizeof(config_pps));
	7070	+
	7071	+ if ((config_pps.pps_3 & 0xf) > dsc->max_linebuf_depth) {
	7072	+ config_pps.pps_3 &= 0xf0;
	7073	+ config_pps.pps_3 \|= dsc->max_linebuf_depth;
	7074	+ DRM_WARN("DSC%d max_linebuf_depth is: %d, current set value is: %d\n",
	7075	+ dsc_id, dsc->max_linebuf_depth, config_pps.pps_3 & 0xf);
	7076	+ }
	7077	+
	7078	+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
	7079	+ config_pps.rc_range_parameters[i] =
	7080	+ (pps->rc_range_parameters[i] >> 3 & 0x1f) \|
	7081	+ ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) \|
	7082	+ ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) \|
	7083	+ ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10);
	7084	+ }
	7085	+
	7086	+ for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++)
	7087	+ vop2_writel(vop2, offset + i * 4, *pps_val++);
	7088	+}
	7089	+
	7090	+static void vop2_crtc_enable_dsc(struct drm_crtc crtc, struct drm_crtc_state old_state, u8 dsc_id)
	7091	+{
	7092	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7093	+ struct vop2 *vop2 = vp->vop2;
	7094	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7095	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7096	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
	7097	+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	7098	+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
	7099	+ u16 htotal = adjusted_mode->crtc_htotal;
	7100	+ u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
	7101	+ u16 vdisplay = adjusted_mode->crtc_vdisplay;
	7102	+ u16 vtotal = adjusted_mode->crtc_vtotal;
	7103	+ u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
	7104	+ u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
	7105	+ u16 vact_end = vact_st + vdisplay;
	7106	+ u8 dsc_interface_mode = 0;
	7107	+ struct vop2_dsc *dsc;
	7108	+ struct vop2_clk dsc_cds_clk, dsc_pxl_clk, *dsc_txp_clk;
	7109	+ const struct vop2_data *vop2_data = vop2->data;
	7110	+ const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id];
	7111	+ bool mipi_ds_mode = false;
	7112	+ uint32_t *reg_base = vop2->regs;
	7113	+ u32 offset = 0;
	7114	+
	7115	+ if (!vop2->data->nr_dscs) {
	7116	+ DRM_WARN("Unsupported DSC\n");
	7117	+
	7118	+ return;
	7119	+ }
	7120	+
	7121	+ if (vcstate->dsc_slice_num > dsc_data->max_slice_num)
	7122	+ DRM_ERROR("DSC%d supported max slice is: %d, current is: %d\n",
	7123	+ dsc_data->id, dsc_data->max_slice_num, vcstate->dsc_slice_num);
	7124	+
	7125	+ dsc = &vop2->dscs[dsc_id];
	7126	+ if (dsc->pd) {
	7127	+ dsc->pd->vp_mask = BIT(vp->id);
	7128	+ vop2_power_domain_get(dsc->pd);
	7129	+ }
	7130	+
	7131	+ VOP_MODULE_SET(vop2, dsc, scan_timing_para_imd_en, 1);
	7132	+ VOP_MODULE_SET(vop2, dsc, dsc_port_sel, vp->id);
	7133	+ if (vcstate->output_if & (VOP_OUTPUT_IF_HDMI0 \| VOP_OUTPUT_IF_HDMI1)) {
	7134	+ dsc_interface_mode = VOP_DSC_IF_HDMI;
	7135	+ } else {
	7136	+ mipi_ds_mode = !!(vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE);
	7137	+ if (mipi_ds_mode)
	7138	+ dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE;
	7139	+ else
	7140	+ dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE;
	7141	+ }
	7142	+
	7143	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7144	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 0);
	7145	+ else
	7146	+ VOP_MODULE_SET(vop2, dsc, dsc_man_mode, 1);
	7147	+ dsc_cds_clk = vop2_clk_get(vop2, dsc_data->dsc_cds_clk_name);
	7148	+ dsc_pxl_clk = vop2_clk_get(vop2, dsc_data->dsc_pxl_clk_name);
	7149	+ dsc_txp_clk = vop2_clk_get(vop2, dsc_data->dsc_txp_clk_name);
	7150	+
	7151	+ VOP_MODULE_SET(vop2, dsc, dsc_interface_mode, dsc_interface_mode);
	7152	+ VOP_MODULE_SET(vop2, dsc, dsc_pixel_num, vcstate->dsc_pixel_num >> 1);
	7153	+ VOP_MODULE_SET(vop2, dsc, dsc_txp_clk_div, dsc_txp_clk->div_val);
	7154	+ VOP_MODULE_SET(vop2, dsc, dsc_pxl_clk_div, dsc_pxl_clk->div_val);
	7155	+ VOP_MODULE_SET(vop2, dsc, dsc_cds_clk_div, dsc_cds_clk->div_val);
	7156	+ VOP_MODULE_SET(vop2, dsc, dsc_scan_en, !mipi_ds_mode);
	7157	+ VOP_MODULE_SET(vop2, dsc, dsc_halt_en, mipi_ds_mode);
	7158	+
	7159	+ if (!mipi_ds_mode) {
	7160	+ u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end;
	7161	+ u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16;
	7162	+ u64 dsc_cds_rate = vcstate->dsc_cds_clk_rate;
	7163	+ u32 v_pixclk_mhz = adjusted_mode->crtc_clock / 1000; /* video timing pixclk */
	7164	+ u32 dly_num, dsc_cds_rate_mhz, val = 0;
	7165	+ struct vop2_clk *dclk_core;
	7166	+ char clk_name[32];
	7167	+ int k = 1;
	7168	+
	7169	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7170	+ k = 2;
	7171	+
	7172	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7173	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7174	+
	7175	+ if (target_bpp >> 4 < dsc->min_bits_per_pixel)
	7176	+ DRM_ERROR("Unsupported bpp less than: %d\n", dsc->min_bits_per_pixel);
	7177	+
	7178	+ /*
	7179	+ * dly_num = delay_line_num * T(one-line) / T (dsc_cds)
	7180	+ * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz
	7181	+ * T (dsc_cds) = 1 / dsc_cds_rate_mhz
	7182	+ *
	7183	+ * HDMI:
	7184	+ * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay
	7185	+ * delay_line_num = 4 - BPP / 8
	7186	+ * = (64 - target_bpp / 8) / 16
	7187	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7188	+ *
	7189	+ * MIPI DSI[4320 and 9216 is buffer size for DSC]:
	7190	+ * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size;
	7191	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7192	+ * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size;
	7193	+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7194	+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num
	7195	+ */
	7196	+ do_div(dsc_cds_rate, 1000000); /* hz to Mhz */
	7197	+ dsc_cds_rate_mhz = dsc_cds_rate;
	7198	+ dsc_hsync = hsync_len / 2;
	7199	+ if (dsc_interface_mode == VOP_DSC_IF_HDMI) {
	7200	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
	7201	+ } else {
	7202	+ int dsc_buf_size = dsc->id == 0 ? 4320 * 8 : 9216 * 2;
	7203	+ int delay_line_num = dsc_buf_size / vcstate->dsc_slice_num / be16_to_cpu(vcstate->pps.chunk_size);
	7204	+
	7205	+ delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
	7206	+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num;
	7207	+
	7208	+ /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */
	7209	+ if (dsc_hsync < 8)
	7210	+ dsc_hsync = 8;
	7211	+ }
	7212	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_mode, 0);
	7213	+ VOP_MODULE_SET(vop2, dsc, dsc_init_dly_num, dly_num);
	7214	+ /*
	7215	+ * htotal / dclk_core = dsc_htotal /cds_clk
	7216	+ *
	7217	+ * dclk_core = DCLK / (1 << dclk_core->div_val)
	7218	+ * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val)
	7219	+ * txp_clk = DCLK / (1 << dsc_txp_clk->div_val)
	7220	+ *
	7221	+ * dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7222	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val))
	7223	+ */
	7224	+ dsc_htotal = htotal * (1 << dclk_core->div_val) /
	7225	+ ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val));
	7226	+ val = dsc_htotal << 16 \| dsc_hsync;
	7227	+ VOP_MODULE_SET(vop2, dsc, dsc_htotal_pw, val);
	7228	+
	7229	+ dsc_hact_st = hact_st / 2;
	7230	+ dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st;
	7231	+ val = dsc_hact_end << 16 \| dsc_hact_st;
	7232	+ VOP_MODULE_SET(vop2, dsc, dsc_hact_st_end, val);
	7233	+
	7234	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, vtotal);
	7235	+ VOP_MODULE_SET(vop2, dsc, dsc_vs_end, vsync_len);
	7236	+ VOP_MODULE_SET(vop2, dsc, dsc_vact_st_end, vact_end << 16 \| vact_st);
	7237	+ }
	7238	+
	7239	+ VOP_MODULE_SET(vop2, dsc, rst_deassert, 1);
	7240	+ udelay(10);
	7241	+ /* read current dsc core register and backup to regsbak */
	7242	+ offset = dsc->regs->dsc_en.offset;
	7243	+ vop2->regsbak[offset >> 2] = reg_base[offset >> 2];
	7244	+
	7245	+ VOP_MODULE_SET(vop2, dsc, dsc_en, 1);
	7246	+ vop2_crtc_load_pps(crtc, dsc_id);
	7247	+
	7248	+ VOP_MODULE_SET(vop2, dsc, dsc_rbit, 1);
	7249	+ VOP_MODULE_SET(vop2, dsc, dsc_rbyt, 0);
	7250	+ VOP_MODULE_SET(vop2, dsc, dsc_flal, 1);
	7251	+ VOP_MODULE_SET(vop2, dsc, dsc_mer, 1);
	7252	+ VOP_MODULE_SET(vop2, dsc, dsc_epb, 0);
	7253	+ VOP_MODULE_SET(vop2, dsc, dsc_epl, 1);
	7254	+ VOP_MODULE_SET(vop2, dsc, dsc_nslc, ilog2(vcstate->dsc_slice_num));
	7255	+ VOP_MODULE_SET(vop2, dsc, dsc_sbo, 1);
	7256	+ VOP_MODULE_SET(vop2, dsc, dsc_ifep, dsc_sink_cap->version_minor == 2 ? 1 : 0);
	7257	+ VOP_MODULE_SET(vop2, dsc, dsc_pps_upd, 1);
	7258	+
	7259	+ DRM_DEV_INFO(vop2->dev, "DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n",
	7260	+ dsc->id,
	7261	+ vcstate->dsc_txp_clk_rate, dsc_txp_clk->div_val,
	7262	+ vcstate->dsc_pxl_clk_rate, dsc_pxl_clk->div_val,
	7263	+ vcstate->dsc_cds_clk_rate, dsc_cds_clk->div_val);
	7264	+
	7265	+ dsc->attach_vp_id = vp->id;
	7266	+ dsc->enabled = true;
	7267	+}
	7268	+
	7269	+static void vop2_setup_dual_channel_if(struct drm_crtc *crtc)
	7270	+{
	7271	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7272	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7273	+ struct vop2 *vop2 = vp->vop2;
	7274	+
	7275	+ VOP_MODULE_SET(vop2, vp, dual_channel_en, 1);
	7276	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
	7277	+ VOP_MODULE_SET(vop2, vp, dual_channel_swap, 1);
	7278	+
	7279	+ if (vcstate->output_if & VOP_OUTPUT_IF_DP1)
	7280	+ VOP_CTRL_SET(vop2, dp_dual_en, 1);
	7281	+ else if (vcstate->output_if & VOP_OUTPUT_IF_eDP1)
	7282	+ VOP_CTRL_SET(vop2, edp_dual_en, 1);
	7283	+ else if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1)
	7284	+ VOP_CTRL_SET(vop2, hdmi_dual_en, 1);
	7285	+ else if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1)
	7286	+ VOP_CTRL_SET(vop2, mipi_dual_en, 1);
	7287	+}
	7288	+
	7289	+/*
	7290	+ * MIPI port mux on rk3588:
	7291	+ * 0: Video Port2
	7292	+ * 1: Video Port3
	7293	+ * 3: Video Port 1(MIPI1 only)
	7294	+ */
	7295	+static int vop2_get_mipi_port_mux(struct vop2 *vop2, int vp_id)
	7296	+{
	7297	+ if (vop2->version == VOP_VERSION_RK3588) {
	7298	+ if (vp_id == 1)
	7299	+ return 3;
	7300	+ else if (vp_id == 3)
	7301	+ return 1;
	7302	+ else
	7303	+ return 0;
	7304	+ } else {
	7305	+ return vp_id;
	7306	+ }
	7307	+}
	7308	+
	7309	+static u32 vop2_get_hdmi_pol(struct vop2 *vop2, u32 flags)
	7310	+{
	7311	+ u32 val;
	7312	+
	7313	+ if (vop2->version == VOP_VERSION_RK3588) {
	7314	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0;
	7315	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0;
	7316	+ } else {
	7317	+ val = (flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
	7318	+ val \|= (flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
	7319	+ }
	7320	+
	7321	+ return val;
	7322	+}
	7323	+
	7324	+static void vop2_post_color_swap(struct drm_crtc *crtc)
	7325	+{
	7326	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7327	+ struct vop2 *vop2 = vp->vop2;
	7328	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7329	+ u32 output_if = vcstate->output_if;
	7330	+ u32 data_swap = 0;
	7331	+
	7332	+ if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode) \|\|
	7333	+ vop3_output_rb_swap(vcstate->bus_format, vcstate->output_mode))
	7334	+ data_swap = DSP_RB_SWAP;
	7335	+
	7336	+ if (vop2->version == VOP_VERSION_RK3588 &&
	7337	+ (output_if_is_hdmi(output_if) \|\| output_if_is_dp(output_if)) &&
	7338	+ (vcstate->bus_format == MEDIA_BUS_FMT_YUV8_1X24 \|\|
	7339	+ vcstate->bus_format == MEDIA_BUS_FMT_YUV10_1X30))
	7340	+ data_swap \|= DSP_RG_SWAP;
	7341	+
	7342	+ VOP_MODULE_SET(vop2, vp, dsp_data_swap, data_swap);
5024	7343	}
5025	7344
5026	7345	/*
..	..	@@ -5048,7 +7367,7 @@
5048	7367	static void vop3_setup_pipe_dly(struct vop2_video_port vp, const struct vop2_zpos vop2_zpos)
5049	7368	{
5050	7369	struct vop2 *vop2 = vp->vop2;
5051		- struct drm_crtc *crtc = &vp->crtc;
	7370	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
5052	7371	const struct vop2_zpos *zpos;
5053	7372	struct drm_plane *plane;
5054	7373	struct vop2_plane_state *vpstate;
..	..	@@ -5124,15 +7443,25 @@
5124	7443	}
5125	7444	}
5126	7445
	7446	+static int vop2_get_vrefresh(struct vop2_video_port vp, const struct drm_display_mode mode)
	7447	+{
	7448	+ if (vp->mcu_timing.mcu_pix_total)
	7449	+ return drm_mode_vrefresh(mode) / vp->mcu_timing.mcu_pix_total;
	7450	+ else
	7451	+ return drm_mode_vrefresh(mode);
	7452	+}
	7453	+
5127	7454	static void vop2_crtc_atomic_enable(struct drm_crtc crtc, struct drm_crtc_state old_state)
5128	7455	{
5129	7456	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7457	+ struct vop2_video_port *splice_vp;
5130	7458	struct vop2 *vop2 = vp->vop2;
5131	7459	const struct vop2_data *vop2_data = vop2->data;
5132	7460	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5133	7461	const struct vop_intr *intr = vp_data->intr;
5134	7462	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
5135	7463	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7464	+ struct rockchip_dsc_sink_cap *dsc_sink_cap = &vcstate->dsc_sink_cap;
5136	7465	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
5137	7466	u16 hdisplay = adjusted_mode->crtc_hdisplay;
5138	7467	u16 htotal = adjusted_mode->crtc_htotal;
..	..	@@ -5147,14 +7476,57 @@
5147	7476	bool dclk_inv, yc_swap = false;
5148	7477	int act_end;
5149	7478	uint32_t val;
	7479	+ char clk_name[32];
	7480	+ struct vop2_clk *if_pixclk = NULL;
	7481	+ struct vop2_clk *if_dclk = NULL;
	7482	+ struct vop2_clk dclk, dclk_out, *dclk_core;
	7483	+ int splice_en = 0;
	7484	+ int port_mux;
	7485	+ int ret;
	7486	+
	7487	+ if (old_state && old_state->self_refresh_active) {
	7488	+ drm_crtc_vblank_on(crtc);
	7489	+ if (vop2->aclk_rate_reset)
	7490	+ clk_set_rate(vop2->aclk, vop2->aclk_rate);
	7491	+ vop2->aclk_rate_reset = false;
	7492	+
	7493	+ return;
	7494	+ }
5150	7495
5151	7496	vop2->active_vp_mask \|= BIT(vp->id);
5152	7497	vop2_set_system_status(vop2);
5153	7498
5154	7499	vop2_lock(vop2);
5155		- DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
5156		- hdisplay, vdisplay, interlaced ? "i" : "p",
5157		- adjusted_mode->vrefresh, vcstate->output_type, vp->id);
	7500	+ DRM_DEV_INFO(vop2->dev, "Update mode to %dx%d%s%d, type: %d(if:%x) for vp%d dclk: %d\n",
	7501	+ hdisplay, adjusted_mode->vdisplay, interlaced ? "i" : "p",
	7502	+ vop2_get_vrefresh(vp, adjusted_mode), vcstate->output_type, vcstate->output_if,
	7503	+ vp->id, adjusted_mode->crtc_clock * 1000);
	7504	+
	7505	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	7506	+ vcstate->splice_mode = true;
	7507	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	7508	+ splice_vp->splice_mode_right = true;
	7509	+ splice_vp->left_vp = vp;
	7510	+ splice_en = 1;
	7511	+ vop2->active_vp_mask \|= BIT(splice_vp->id);
	7512	+ }
	7513	+
	7514	+ if (vcstate->dsc_enable) {
	7515	+ int k = 1;
	7516	+
	7517	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7518	+ k = 2;
	7519	+
	7520	+ vcstate->dsc_id = vcstate->output_if & (VOP_OUTPUT_IF_MIPI0 \| VOP_OUTPUT_IF_HDMI0) ? 0 : 1;
	7521	+ vcstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k;
	7522	+ vcstate->dsc_pixel_num = vcstate->dsc_slice_num > 4 ? 4 : vcstate->dsc_slice_num;
	7523	+
	7524	+ vop2_calc_dsc_clk(crtc);
	7525	+ DRM_DEV_INFO(vop2->dev, "Enable DSC%d slice:%dx%d, slice num:%d\n",
	7526	+ vcstate->dsc_id, dsc_sink_cap->slice_width,
	7527	+ dsc_sink_cap->slice_height, vcstate->dsc_slice_num);
	7528	+ }
	7529	+
5158	7530	vop2_initial(crtc);
5159	7531	vcstate->vdisplay = vdisplay;
5160	7532	vcstate->mode_update = vop2_crtc_mode_update(crtc);
..	..	@@ -5165,26 +7537,51 @@
5165	7537	val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
5166	7538	val \|= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
5167	7539
	7540	+ vp->output_if = vcstate->output_if;
	7541	+
5168	7542	if (vcstate->output_if & VOP_OUTPUT_IF_RGB) {
	7543	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7544	+ if (ret < 0)
	7545	+ goto out;
	7546	+
5169	7547	VOP_CTRL_SET(vop2, rgb_en, 1);
5170	7548	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
5171	7549	VOP_CTRL_SET(vop2, rgb_pin_pol, val);
5172		- VOP_GRF_SET(vop2, grf_dclk_inv, dclk_inv);
	7550	+ VOP_GRF_SET(vop2, sys_grf, grf_dclk_inv, dclk_inv);
5173	7551	}
5174	7552
5175	7553	if (vcstate->output_if & VOP_OUTPUT_IF_BT1120) {
5176		- VOP_CTRL_SET(vop2, rgb_en, 1);
5177		- VOP_CTRL_SET(vop2, bt1120_en, 1);
	7554	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7555	+ if (ret < 0)
	7556	+ goto out;
	7557	+
	7558	+ if (vop2->version == VOP_VERSION_RK3588) {
	7559	+ VOP_CTRL_SET(vop2, bt1120_en, 3);
	7560	+ } else {
	7561	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7562	+ VOP_CTRL_SET(vop2, bt1120_en, 1);
	7563	+ }
5178	7564	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
5179		- VOP_GRF_SET(vop2, grf_bt1120_clk_inv, !dclk_inv);
	7565	+ VOP_GRF_SET(vop2, sys_grf, grf_bt1120_clk_inv, !dclk_inv);
	7566	+ VOP_CTRL_SET(vop2, bt1120_dclk_pol, !dclk_inv);
5180	7567	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
5181	7568	VOP_CTRL_SET(vop2, bt1120_yc_swap, yc_swap);
5182	7569	}
5183	7570
5184	7571	if (vcstate->output_if & VOP_OUTPUT_IF_BT656) {
5185		- VOP_CTRL_SET(vop2, bt656_en, 1);
	7572	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_RGB, &if_pixclk, &if_dclk);
	7573	+ if (ret < 0)
	7574	+ goto out;
	7575	+
	7576	+ if (vop2->version == VOP_VERSION_RK3588) {
	7577	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7578	+ } else {
	7579	+ VOP_CTRL_SET(vop2, rgb_en, 1);
	7580	+ VOP_CTRL_SET(vop2, bt656_en, 1);
	7581	+ }
5186	7582	VOP_CTRL_SET(vop2, rgb_mux, vp_data->id);
5187		- VOP_GRF_SET(vop2, grf_bt656_clk_inv, !dclk_inv);
	7583	+ VOP_GRF_SET(vop2, sys_grf, grf_bt656_clk_inv, !dclk_inv);
	7584	+ VOP_CTRL_SET(vop2, bt656_dclk_pol, !dclk_inv);
5188	7585	yc_swap = vop2_output_yc_swap(vcstate->bus_format);
5189	7586	VOP_CTRL_SET(vop2, bt656_yc_swap, yc_swap);
5190	7587	}
..	..	@@ -5213,8 +7610,18 @@
5213	7610	}
5214	7611
5215	7612	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI0) {
	7613	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI0, &if_pixclk, &if_dclk);
	7614	+ if (ret < 0)
	7615	+ goto out;
	7616	+ if (if_pixclk)
	7617	+ VOP_CTRL_SET(vop2, mipi0_pixclk_div, if_pixclk->div_val);
	7618	+
	7619	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7620	+ VOP_CTRL_SET(vop2, mipi0_ds_mode, 1);
	7621	+
	7622	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
5216	7623	VOP_CTRL_SET(vop2, mipi0_en, 1);
5217		- VOP_CTRL_SET(vop2, mipi0_mux, vp_data->id);
	7624	+ VOP_CTRL_SET(vop2, mipi0_mux, port_mux);
5218	7625	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
5219	7626	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
5220	7627	if (vcstate->hold_mode) {
..	..	@@ -5224,8 +7631,19 @@
5224	7631	}
5225	7632
5226	7633	if (vcstate->output_if & VOP_OUTPUT_IF_MIPI1) {
	7634	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_MIPI1, &if_pixclk, &if_dclk);
	7635	+ if (ret < 0)
	7636	+ goto out;
	7637	+ if (if_pixclk)
	7638	+ VOP_CTRL_SET(vop2, mipi1_pixclk_div, if_pixclk->div_val);
	7639	+
	7640	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE)
	7641	+ VOP_CTRL_SET(vop2, mipi1_ds_mode, 1);
	7642	+
	7643	+ port_mux = vop2_get_mipi_port_mux(vop2, vp_data->id);
	7644	+
5227	7645	VOP_CTRL_SET(vop2, mipi1_en, 1);
5228		- VOP_CTRL_SET(vop2, mipi1_mux, vp_data->id);
	7646	+ VOP_CTRL_SET(vop2, mipi1_mux, port_mux);
5229	7647	VOP_CTRL_SET(vop2, mipi_pin_pol, val);
5230	7648	VOP_CTRL_SET(vop2, mipi_dclk_pol, dclk_inv);
5231	7649	if (vcstate->hold_mode) {
..	..	@@ -5234,41 +7652,78 @@
5234	7652	}
5235	7653	}
5236	7654
5237		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
5238		- VOP_MODULE_SET(vop2, vp, mipi_dual_en, 1);
5239		- if (vcstate->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP)
5240		- VOP_MODULE_SET(vop2, vp, mipi_dual_channel_swap, 1);
5241		- }
	7655	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
	7656	+ vop2_setup_dual_channel_if(crtc);
5242	7657
5243	7658	if (vcstate->output_if & VOP_OUTPUT_IF_eDP0) {
	7659	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP0, &if_pixclk, &if_dclk);
	7660	+ if (ret < 0)
	7661	+ goto out;
	7662	+ if (if_pixclk && if_dclk) {
	7663	+ VOP_CTRL_SET(vop2, edp0_pixclk_div, if_pixclk->div_val);
	7664	+ VOP_CTRL_SET(vop2, edp0_dclk_div, if_dclk->div_val);
	7665	+ }
	7666	+
5244	7667	VOP_CTRL_SET(vop2, edp0_en, 1);
5245	7668	VOP_CTRL_SET(vop2, edp0_mux, vp_data->id);
5246	7669	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5247	7670	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7671	+ VOP_GRF_SET(vop2, grf, grf_edp0_en, 1);
5248	7672	}
5249	7673
5250	7674	if (vcstate->output_if & VOP_OUTPUT_IF_eDP1) {
	7675	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_eDP1, &if_pixclk, &if_dclk);
	7676	+ if (ret < 0)
	7677	+ goto out;
	7678	+ if (if_pixclk && if_dclk) {
	7679	+ VOP_CTRL_SET(vop2, edp1_pixclk_div, if_pixclk->div_val);
	7680	+ VOP_CTRL_SET(vop2, edp1_dclk_div, if_dclk->div_val);
	7681	+ }
	7682	+
5251	7683	VOP_CTRL_SET(vop2, edp1_en, 1);
5252	7684	VOP_CTRL_SET(vop2, edp1_mux, vp_data->id);
5253	7685	VOP_CTRL_SET(vop2, edp_pin_pol, val);
5254	7686	VOP_CTRL_SET(vop2, edp_dclk_pol, dclk_inv);
	7687	+ VOP_GRF_SET(vop2, grf, grf_edp1_en, 1);
5255	7688	}
5256	7689
5257	7690	if (vcstate->output_if & VOP_OUTPUT_IF_DP0) {
	7691	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7692	+ if (ret < 0)
	7693	+ goto out;
5258	7694	VOP_CTRL_SET(vop2, dp0_en, 1);
5259	7695	VOP_CTRL_SET(vop2, dp0_mux, vp_data->id);
5260		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5261		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7696	+ VOP_CTRL_SET(vop2, dp0_dclk_pol, 0);
	7697	+ VOP_CTRL_SET(vop2, dp0_pin_pol, val);
5262	7698	}
5263	7699
5264	7700	if (vcstate->output_if & VOP_OUTPUT_IF_DP1) {
	7701	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_DP0, &if_pixclk, &if_dclk);
	7702	+ if (ret < 0)
	7703	+ goto out;
	7704	+
5265	7705	VOP_CTRL_SET(vop2, dp1_en, 1);
5266	7706	VOP_CTRL_SET(vop2, dp1_mux, vp_data->id);
5267		- VOP_CTRL_SET(vop2, dp_dclk_pol, 0);
5268		- VOP_CTRL_SET(vop2, dp_pin_pol, val);
	7707	+ VOP_CTRL_SET(vop2, dp1_dclk_pol, 0);
	7708	+ VOP_CTRL_SET(vop2, dp1_pin_pol, val);
5269	7709	}
5270	7710
5271	7711	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI0) {
	7712	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI0, &if_pixclk, &if_dclk);
	7713	+ if (ret < 0)
	7714	+ goto out;
	7715	+ if (if_pixclk && if_dclk) {
	7716	+ VOP_CTRL_SET(vop2, hdmi0_pixclk_div, if_pixclk->div_val);
	7717	+ VOP_CTRL_SET(vop2, hdmi0_dclk_div, if_dclk->div_val);
	7718	+ }
	7719	+
	7720	+ if (vcstate->dsc_enable)
	7721	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_dsc_en, 1);
	7722	+
	7723	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	7724	+ VOP_GRF_SET(vop2, grf, grf_hdmi0_en, 1);
	7725	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi0_pin_pol, val);
	7726	+
5272	7727	VOP_CTRL_SET(vop2, hdmi0_en, 1);
5273	7728	VOP_CTRL_SET(vop2, hdmi0_mux, vp_data->id);
5274	7729	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
..	..	@@ -5276,11 +7731,29 @@
5276	7731	}
5277	7732
5278	7733	if (vcstate->output_if & VOP_OUTPUT_IF_HDMI1) {
	7734	+ ret = vop2_calc_cru_cfg(crtc, VOP_OUTPUT_IF_HDMI1, &if_pixclk, &if_dclk);
	7735	+ if (ret < 0)
	7736	+ goto out;
	7737	+
	7738	+ if (if_pixclk && if_dclk) {
	7739	+ VOP_CTRL_SET(vop2, hdmi1_pixclk_div, if_pixclk->div_val);
	7740	+ VOP_CTRL_SET(vop2, hdmi1_dclk_div, if_dclk->div_val);
	7741	+ }
	7742	+
	7743	+ if (vcstate->dsc_enable)
	7744	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_dsc_en, 1);
	7745	+
	7746	+ val = vop2_get_hdmi_pol(vop2, adjusted_mode->flags);
	7747	+ VOP_GRF_SET(vop2, grf, grf_hdmi1_en, 1);
	7748	+ VOP_GRF_SET(vop2, vo1_grf, grf_hdmi1_pin_pol, val);
	7749	+
5279	7750	VOP_CTRL_SET(vop2, hdmi1_en, 1);
5280	7751	VOP_CTRL_SET(vop2, hdmi1_mux, vp_data->id);
5281	7752	VOP_CTRL_SET(vop2, hdmi_pin_pol, val);
5282	7753	VOP_CTRL_SET(vop2, hdmi_dclk_pol, 1);
5283	7754	}
	7755	+
	7756	+ VOP_MODULE_SET(vop2, vp, splice_en, splice_en);
5284	7757
5285	7758	VOP_MODULE_SET(vop2, vp, htotal_pw, (htotal << 16) \| hsync_len);
5286	7759	val = hact_st << 16;
..	..	@@ -5318,7 +7791,13 @@
5318	7791	VOP_INTR_SET(vop2, intr, line_flag_num[0], act_end);
5319	7792	VOP_INTR_SET(vop2, intr, line_flag_num[1], act_end);
5320	7793
5321		- VOP_MODULE_SET(vop2, vp, vtotal_pw, vtotal << 16 \| vsync_len);
	7794	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, vtotal);
	7795	+ VOP_MODULE_SET(vop2, vp, dsp_vs_end, vsync_len);
	7796	+ /**
	7797	+ * when display interface support vrr, config vtotal valid immediately
	7798	+ */
	7799	+ if (vcstate->max_refresh_rate && vcstate->min_refresh_rate)
	7800	+ VOP_MODULE_SET(vop2, vp, sw_dsp_vtotal_imd, 1);
5322	7801
5323	7802	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK \|\|
5324	7803	vcstate->output_if & VOP_OUTPUT_IF_BT656)
..	..	@@ -5334,18 +7813,68 @@
5334	7813	VOP_MODULE_SET(vop2, vp, dclk_div2_phase_lock, 0);
5335	7814	}
5336	7815
5337		- /*
5338		- * For RK3528, the path of CVBS output is like:
5339		- * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
5340		- * The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs.
	7816	+ snprintf(clk_name, sizeof(clk_name), "dclk_out%d", vp->id);
	7817	+ dclk_out = vop2_clk_get(vop2, clk_name);
	7818	+ snprintf(clk_name, sizeof(clk_name), "dclk_core%d", vp->id);
	7819	+ dclk_core = vop2_clk_get(vop2, clk_name);
	7820	+ if (dclk_out && dclk_core) {
	7821	+ DRM_DEV_INFO(vop2->dev, "%s div: %d %s div: %d\n",
	7822	+ __clk_get_name(dclk_out->hw.clk), dclk_out->div_val,
	7823	+ __clk_get_name(dclk_core->hw.clk), dclk_core->div_val);
	7824	+ VOP_MODULE_SET(vop2, vp, dclk_src_sel, 0);
	7825	+ VOP_MODULE_SET(vop2, vp, dclk_out_div, dclk_out->div_val);
	7826	+ VOP_MODULE_SET(vop2, vp, dclk_core_div, dclk_core->div_val);
	7827	+ }
	7828	+
	7829	+ snprintf(clk_name, sizeof(clk_name), "dclk%d", vp->id);
	7830	+ dclk = vop2_clk_get(vop2, clk_name);
	7831	+ if (dclk) {
	7832	+ /*
	7833	+ * use HDMI_PHY_PLL as dclk source under 4K@60 if it is available,
	7834	+ * otherwise use system cru as dclk source.
	7835	+ */
	7836	+ ret = vop2_clk_set_parent_extend(vp, vcstate, true);
	7837	+ if (ret < 0)
	7838	+ goto out;
	7839	+
	7840	+ clk_set_rate(vp->dclk, dclk->rate);
	7841	+ DRM_DEV_INFO(vop2->dev, "set %s to %ld, get %ld\n",
	7842	+ __clk_get_name(vp->dclk), dclk->rate, clk_get_rate(vp->dclk));
	7843	+ } else {
	7844	+ /*
	7845	+ * For RK3528, the path of CVBS output is like:
	7846	+ * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
	7847	+ * The vop2 dclk should be four times crtc_clock for CVBS sampling clock needs.
	7848	+ */
	7849	+ if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656)
	7850	+ clk_set_rate(vp->dclk, 4 * adjusted_mode->crtc_clock * 1000);
	7851	+ else
	7852	+ clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
	7853	+ }
	7854	+
	7855	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	7856	+ vop2_post_config(crtc);
	7857	+
	7858	+ VOP_MODULE_SET(vop2, vp, almost_full_or_en, 1);
	7859	+ VOP_MODULE_SET(vop2, vp, line_flag_or_en, 1);
	7860	+ if (vcstate->dsc_enable) {
	7861	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	7862	+ vop2_crtc_enable_dsc(crtc, old_state, 0);
	7863	+ vop2_crtc_enable_dsc(crtc, old_state, 1);
	7864	+ } else {
	7865	+ vop2_crtc_enable_dsc(crtc, old_state, vcstate->dsc_id);
	7866	+ }
	7867	+ }
	7868	+ /* For RK3588, the reset value of background is 0xa0080200,
	7869	+ * which will enable background and output a grey image. But
	7870	+ * the reset value is just valid in first frame and disable
	7871	+ * in follow frames. If the panel backlight is valid before
	7872	+ * follow frames. The screen may flick a grey image. To avoid
	7873	+ * this phenomenon appear, setting black background after
	7874	+ * reset vop
5341	7875	*/
5342		- if (vop2->version == VOP_VERSION_RK3528 && vcstate->output_if & VOP_OUTPUT_IF_BT656)
5343		- clk_set_rate(vp->dclk, 4 * adjusted_mode->crtc_clock * 1000);
5344		- else
5345		- clk_set_rate(vp->dclk, adjusted_mode->crtc_clock * 1000);
5346		-
5347		- vop2_post_config(crtc);
5348		-
	7876	+ if (vop2->version == VOP_VERSION_RK3588)
	7877	+ VOP_MODULE_SET(vop2, vp, dsp_background, 0x80000000);
5349	7878	if (is_vop3(vop2))
5350	7879	vop3_setup_pipe_dly(vp, NULL);
5351	7880
..	..	@@ -5368,14 +7897,22 @@
5368	7897	*/
5369	7898	VOP_MODULE_SET(vop2, vp, standby, 0);
5370	7899
5371		- drm_crtc_vblank_on(crtc);
	7900	+ if (vp->mcu_timing.mcu_pix_total) {
	7901	+ vop3_set_out_mode(crtc, vcstate->output_mode);
	7902	+ vop3_mcu_mode_setup(crtc);
	7903	+ }
5372	7904
	7905	+ if (!vp->loader_protect)
	7906	+ vop2_clk_reset(vp->dclk_rst);
	7907	+ if (vcstate->dsc_enable)
	7908	+ rk3588_vop2_dsc_cfg_done(crtc);
	7909	+ drm_crtc_vblank_on(crtc);
5373	7910	/*
5374	7911	* restore the lut table.
5375	7912	*/
5376	7913	if (vp->gamma_lut_active)
5377	7914	vop2_crtc_load_lut(crtc);
5378		-
	7915	+out:
5379	7916	vop2_unlock(vop2);
5380	7917	}
5381	7918
..	..	@@ -5393,6 +7930,30 @@
5393	7930	static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
5394	7931	struct drm_crtc_state *crtc_state)
5395	7932	{
	7933	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	7934	+ struct vop2_video_port *splice_vp;
	7935	+ struct vop2 *vop2 = vp->vop2;
	7936	+ const struct vop2_data *vop2_data = vop2->data;
	7937	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	7938	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	7939	+ struct rockchip_crtc_state *new_vcstate = to_rockchip_crtc_state(crtc_state);
	7940	+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
	7941	+
	7942	+ if (vop2_has_feature(vop2, VOP_FEATURE_SPLICE)) {
	7943	+ if (adjusted_mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) {
	7944	+ vcstate->splice_mode = true;
	7945	+ splice_vp = &vop2->vps[vp_data->splice_vp_id];
	7946	+ splice_vp->splice_mode_right = true;
	7947	+ splice_vp->left_vp = vp;
	7948	+ }
	7949	+ }
	7950	+
	7951	+ if ((vcstate->request_refresh_rate != new_vcstate->request_refresh_rate) \|\|
	7952	+ crtc_state->active_changed \|\| crtc_state->mode_changed)
	7953	+ vp->refresh_rate_change = true;
	7954	+ else
	7955	+ vp->refresh_rate_change = false;
	7956	+
5396	7957	return 0;
5397	7958	}
5398	7959
..	..	@@ -5427,12 +7988,13 @@
5427	7988	struct drm_plane *plane = &win->base;
5428	7989	struct drm_plane_state *pstate = plane->state;
5429	7990	struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
5430		- struct drm_crtc_state *cstate = vp->crtc.state;
	7991	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
5431	7992	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
5432	7993	unsigned long win_mask = vp->win_mask;
5433	7994	int phys_id;
5434	7995	struct hdrvivid_regs *hdrvivid_data;
5435	7996	struct hdr_extend *hdr_data;
	7997	+ struct rockchip_gem_object *lut_gem_obj;
5436	7998	bool have_sdr_layer = false;
5437	7999	uint32_t hdr_mode;
5438	8000	int i;
..	..	@@ -5463,7 +8025,7 @@
5463	8025	if (hdr_mode == SDR2HLG_USERSPACE)
5464	8026	hdr_mode = SDR2HLG;
5465	8027
5466		- if (hdr_mode <= HDR102SDR && vpstate->eotf != SMPTE_ST2084 && vpstate->eotf != HLG) {
	8028	+ if (hdr_mode <= HDR102SDR && vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 && vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
5467	8029	DRM_ERROR("Invalid HDR mode:%d, mismatch plane eotf:%d\n", hdr_mode,
5468	8030	vpstate->eotf);
5469	8031	return;
..	..	@@ -5493,7 +8055,8 @@
5493	8055	if (!vop2_plane_active(pstate))
5494	8056	continue;
5495	8057
5496		- if (vpstate->eotf != SMPTE_ST2084 && vpstate->eotf != HLG) {
	8058	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084 &&
	8059	+ vpstate->eotf != HDMI_EOTF_BT_2100_HLG) {
5497	8060	have_sdr_layer = true;
5498	8061	break;
5499	8062	}
..	..	@@ -5546,6 +8109,16 @@
5546	8109	vop2_writel(vop2, RK3528_HDR_CSC_COE20_21, hdrvivid_data->hdr_csc_coe20_21);
5547	8110	vop2_writel(vop2, RK3528_HDR_CSC_COE22, hdrvivid_data->hdr_csc_coe22);
5548	8111
	8112	+ if (!vp->hdr_lut_gem_obj) {
	8113	+ lut_gem_obj = rockchip_gem_create_object(vop2->drm_dev,
	8114	+ RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH * 4, true, 0);
	8115	+ if (IS_ERR(lut_gem_obj)) {
	8116	+ DRM_ERROR("create hdr lut obj failed\n");
	8117	+ return;
	8118	+ }
	8119	+ vp->hdr_lut_gem_obj = lut_gem_obj;
	8120	+ }
	8121	+
5549	8122	tone_lut_kvaddr = (u32 *)vp->hdr_lut_gem_obj->kvaddr;
5550	8123	tone_lut_mst = vp->hdr_lut_gem_obj->dma_addr;
5551	8124
..	..	@@ -5583,7 +8156,7 @@
5583	8156
5584	8157	static void vop3_setup_dynamic_hdr(struct vop2_video_port *vp, uint8_t win_phys_id)
5585	8158	{
5586		- struct drm_crtc_state *cstate = vp->crtc.state;
	8159	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
5587	8160	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
5588	8161	struct hdr_extend *hdr_data;
5589	8162	uint32_t hdr_format;
..	..	@@ -5619,13 +8192,13 @@
5619	8192	struct vop2 *vop2 = vp->vop2;
5620	8193	struct vop2_win *win = vop2_find_win_by_phys_id(vop2, win_phys_id);
5621	8194	struct drm_plane *plane = &win->base;
5622		- struct drm_plane_state *pstate = plane->state;
5623		- struct vop2_plane_state *vpstate = to_vop2_plane_state(pstate);
5624		- struct drm_crtc_state *cstate = vp->crtc.state;
5625		- struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(cstate);
	8195	+ struct drm_plane_state *pstate;
	8196	+ struct drm_crtc_state *cstate = vp->rockchip_crtc.crtc.state;
5626	8197	const struct vop2_data *vop2_data = vop2->data;
5627	8198	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
5628	8199	const struct vop_hdr_table *hdr_table = vp_data->hdr_table;
	8200	+ struct rockchip_crtc_state *vcstate;
	8201	+ struct vop2_plane_state *vpstate;
5629	8202	uint32_t lut_mode = VOP2_HDR_LUT_MODE_AHB;
5630	8203	uint32_t sdr2hdr_r2r_mode = 0;
5631	8204	bool hdr_en = 0;
..	..	@@ -5645,14 +8218,27 @@
5645	8218	return;
5646	8219
5647	8220	/*
	8221	+ * right vp share the same crtc/plane state in splice mode
	8222	+ */
	8223	+ if (vp->splice_mode_right) {
	8224	+ vcstate = to_rockchip_crtc_state(vp->left_vp->rockchip_crtc.crtc.state);
	8225	+ pstate = win->left_win->base.state;
	8226	+ } else {
	8227	+ vcstate = to_rockchip_crtc_state(cstate);
	8228	+ pstate = plane->state;
	8229	+ }
	8230	+
	8231	+ vpstate = to_vop2_plane_state(pstate);
	8232	+
	8233	+ /*
5648	8234	* HDR video plane input
5649	8235	*/
5650		- if (vpstate->eotf == SMPTE_ST2084)
	8236	+ if (vpstate->eotf == HDMI_EOTF_SMPTE_ST2084)
5651	8237	hdr_en = 1;
5652	8238
5653	8239	vp->hdr_en = hdr_en;
5654	8240	vp->hdr_in = hdr_en;
5655		- vp->hdr_out = (vcstate->eotf == SMPTE_ST2084) ? true : false;
	8241	+ vp->hdr_out = (vcstate->eotf == HDMI_EOTF_SMPTE_ST2084) ? true : false;
5656	8242
5657	8243	/*
5658	8244	* only laryer0 support hdr2sdr
..	..	@@ -5670,15 +8256,21 @@
5670	8256	*/
5671	8257	for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
5672	8258	win = vop2_find_win_by_phys_id(vop2, phys_id);
5673		- plane = &win->base;
5674		- pstate = plane->state;
5675		- vpstate = to_vop2_plane_state(pstate);
	8259	+ if (vp->splice_mode_right) {
	8260	+ if (win->left_win)
	8261	+ pstate = win->left_win->base.state;
	8262	+ else
	8263	+ pstate = NULL; /* this win is not activated */
	8264	+ } else {
	8265	+ pstate = win->base.state;
	8266	+ }
5676	8267
5677		- /* skip inactive plane */
	8268	+ vpstate = pstate ? to_vop2_plane_state(pstate) : NULL;
	8269	+
5678	8270	if (!vop2_plane_active(pstate))
5679	8271	continue;
5680	8272
5681		- if (vpstate->eotf != SMPTE_ST2084) {
	8273	+ if (vpstate->eotf != HDMI_EOTF_SMPTE_ST2084) {
5682	8274	have_sdr_layer = true;
5683	8275	break;
5684	8276	}
..	..	@@ -5825,7 +8417,15 @@
5825	8417
5826	8418	if (!sub_win) {
5827	8419	/* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
5828		- plane = &main_win->base;
	8420	+
	8421	+ /*
	8422	+ * right cluster share the same plane state in splice mode
	8423	+ */
	8424	+ if (cluster->splice_mode)
	8425	+ plane = &main_win->left_win->base;
	8426	+ else
	8427	+ plane = &main_win->base;
	8428	+
5829	8429	top_win_vpstate = NULL;
5830	8430	bottom_win_vpstate = to_vop2_plane_state(plane->state);
5831	8431	src_glb_alpha_val = 0;
..	..	@@ -5884,25 +8484,35 @@
5884	8484	uint32_t dst_color_ctrl_offset = vop2->data->ctrl->dst_color_ctrl.offset;
5885	8485	uint32_t src_alpha_ctrl_offset = vop2->data->ctrl->src_alpha_ctrl.offset;
5886	8486	uint32_t dst_alpha_ctrl_offset = vop2->data->ctrl->dst_alpha_ctrl.offset;
	8487	+ unsigned long win_mask = vp->win_mask;
5887	8488	const struct vop2_zpos *zpos;
5888		- struct drm_framebuffer *fb;
	8489	+ struct vop2_plane_state *vpstate;
5889	8490	struct vop2_alpha_config alpha_config;
5890	8491	struct vop2_alpha alpha;
5891	8492	struct vop2_win *win;
5892		- struct drm_plane *plane;
5893		- struct vop2_plane_state *vpstate;
	8493	+ struct drm_plane_state *pstate;
	8494	+ struct drm_framebuffer *fb;
5894	8495	int pixel_alpha_en;
5895		- int premulti_en;
	8496	+ int premulti_en = 1;
5896	8497	int mixer_id;
	8498	+ int phys_id;
5897	8499	uint32_t offset;
5898	8500	int i;
5899	8501	bool bottom_layer_alpha_en = false;
5900	8502	u32 dst_global_alpha = 0xff;
5901	8503
5902		- drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
5903		- struct vop2_win *win = to_vop2_win(plane);
	8504	+ for_each_set_bit(phys_id, &win_mask, ROCKCHIP_MAX_LAYER) {
	8505	+ win = vop2_find_win_by_phys_id(vop2, phys_id);
	8506	+ if (win->splice_mode_right)
	8507	+ pstate = win->left_win->base.state;
	8508	+ else
	8509	+ pstate = win->base.state;
5904	8510
5905		- vpstate = to_vop2_plane_state(plane->state);
	8511	+ vpstate = to_vop2_plane_state(pstate);
	8512	+
	8513	+ if (!vop2_plane_active(pstate))
	8514	+ continue;
	8515	+
5906	8516	if (vpstate->zpos == 0 && vpstate->global_alpha != 0xff &&
5907	8517	!vop2_cluster_window(win)) {
5908	8518	/*
..	..	@@ -5912,19 +8522,33 @@
5912	8522	*/
5913	8523	bottom_layer_alpha_en = true;
5914	8524	dst_global_alpha = vpstate->global_alpha;
	8525	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8526	+ premulti_en = 1;
	8527	+ else
	8528	+ premulti_en = 0;
	8529	+
5915	8530	break;
5916	8531	}
5917	8532	}
5918	8533
5919	8534	mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
	8535	+
	8536	+ if (vop2->version == VOP_VERSION_RK3588 &&
	8537	+ vp->hdr10_at_splice_mode && vp->id == 0)
	8538	+ mixer_id++;/* fixed path for rk3588: layer1 -> hdr10_1 */
	8539	+
5920	8540	alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
5921	8541	for (i = 1; i < vp->nr_layers; i++) {
5922	8542	zpos = &vop2_zpos[i];
5923	8543	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
5924		- plane = &win->base;
5925		- vpstate = to_vop2_plane_state(plane->state);
5926		- fb = plane->state->fb;
5927		- if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
	8544	+ if (win->splice_mode_right)
	8545	+ pstate = win->left_win->base.state;
	8546	+ else
	8547	+ pstate = win->base.state;
	8548	+
	8549	+ vpstate = to_vop2_plane_state(pstate);
	8550	+ fb = pstate->fb;
	8551	+ if (pstate->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
5928	8552	premulti_en = 1;
5929	8553	else
5930	8554	premulti_en = 0;
..	..	@@ -5954,29 +8578,27 @@
5954	8578	vop2_writel(vop2, dst_color_ctrl_offset + offset, alpha.dst_color_ctrl.val);
5955	8579	vop2_writel(vop2, src_alpha_ctrl_offset + offset, alpha.src_alpha_ctrl.val);
5956	8580	vop2_writel(vop2, dst_alpha_ctrl_offset + offset, alpha.dst_alpha_ctrl.val);
	8581	+ }
5957	8582
5958		- if (i == 1) {
5959		- if (bottom_layer_alpha_en \|\| vp->hdr_en) {
5960		- /* Transfer pixel alpha to hdr mix */
5961		- alpha_config.src_premulti_en = premulti_en;
5962		- alpha_config.dst_premulti_en = true;
5963		- alpha_config.src_pixel_alpha_en = true;
5964		- alpha_config.src_glb_alpha_value = 0xff;
5965		- alpha_config.dst_glb_alpha_value = 0xff;
5966		- vop2_parse_alpha(&alpha_config, &alpha);
	8583	+ if (bottom_layer_alpha_en \|\| vp->hdr_en) {
	8584	+ /* Transfer pixel alpha to hdr mix */
	8585	+ alpha_config.src_premulti_en = premulti_en;
	8586	+ alpha_config.dst_premulti_en = true;
	8587	+ alpha_config.src_pixel_alpha_en = true;
	8588	+ alpha_config.src_glb_alpha_value = 0xff;
	8589	+ alpha_config.dst_glb_alpha_value = 0xff;
	8590	+ vop2_parse_alpha(&alpha_config, &alpha);
5967	8591
5968		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
5969		- alpha.src_color_ctrl.val);
5970		- VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
5971		- alpha.dst_color_ctrl.val);
5972		- VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
5973		- alpha.src_alpha_ctrl.val);
5974		- VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
5975		- alpha.dst_alpha_ctrl.val);
5976		- } else {
5977		- VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5978		- }
5979		- }
	8592	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl,
	8593	+ alpha.src_color_ctrl.val);
	8594	+ VOP_MODULE_SET(vop2, vp, hdr_dst_color_ctrl,
	8595	+ alpha.dst_color_ctrl.val);
	8596	+ VOP_MODULE_SET(vop2, vp, hdr_src_alpha_ctrl,
	8597	+ alpha.src_alpha_ctrl.val);
	8598	+ VOP_MODULE_SET(vop2, vp, hdr_dst_alpha_ctrl,
	8599	+ alpha.dst_alpha_ctrl.val);
	8600	+ } else {
	8601	+ VOP_MODULE_SET(vop2, vp, hdr_src_color_ctrl, 0);
5980	8602	}
5981	8603
5982	8604	/* Transfer pixel alpha value to next mix */
..	..	@@ -6137,21 +8759,6 @@
6137	8759	VOP_MODULE_SET(vop2, vp, bg_mix_ctrl, bg_alpha_ctrl.val);
6138	8760	}
6139	8761
6140		-static void vop2_setup_port_mux(struct vop2_video_port *vp, uint16_t port_mux_cfg)
6141		-{
6142		- struct vop2 *vop2 = vp->vop2;
6143		-
6144		- spin_lock(&vop2->reg_lock);
6145		- if (vop2->port_mux_cfg != port_mux_cfg) {
6146		- VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
6147		- vp->skip_vsync = true;
6148		- vop2_cfg_done(&vp->crtc);
6149		- vop2->port_mux_cfg = port_mux_cfg;
6150		- vop2_wait_for_port_mux_done(vop2);
6151		- }
6152		- spin_unlock(&vop2->reg_lock);
6153		-}
6154		-
6155	8762	static u32 vop2_layer_cfg_update(struct vop2_layer *layer, u32 old_layer_cfg, u8 win_layer_id)
6156	8763	{
6157	8764	const struct vop_reg *reg = &layer->regs->layer_sel;
..	..	@@ -6174,6 +8781,12 @@
6174	8781	for (i = 0; i < vop2_data->nr_vps - 1; i++) {
6175	8782	prev_vp = &vop2->vps[i];
6176	8783	used_layers += hweight32(prev_vp->win_mask);
	8784	+ if (vop2->version == VOP_VERSION_RK3588) {
	8785	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 0)
	8786	+ used_layers += 1;
	8787	+ if (vop2->vps[0].hdr10_at_splice_mode && i == 1)
	8788	+ used_layers -= 1;
	8789	+ }
6177	8790	/*
6178	8791	* when a window move from vp0 to vp1, or vp0 to vp2,
6179	8792	* it should flow these steps:
..	..	@@ -6199,10 +8812,26 @@
6199	8812	prev_vp->bg_ovl_dly = (vop2_data->nr_mixers - port_mux) << 1;
6200	8813	}
6201	8814
6202		- if (vop2->data->nr_vps >= 1)
6203		- port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
	8815	+ port_mux_cfg \|= 7 << (4 * (vop2->data->nr_vps - 1));
6204	8816
6205	8817	return port_mux_cfg;
	8818	+}
	8819	+
	8820	+static void vop2_setup_port_mux(struct vop2_video_port *vp)
	8821	+{
	8822	+ struct vop2 *vop2 = vp->vop2;
	8823	+ u16 port_mux_cfg;
	8824	+
	8825	+ port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
	8826	+ spin_lock(&vop2->reg_lock);
	8827	+ if (vop2->port_mux_cfg != port_mux_cfg) {
	8828	+ VOP_CTRL_SET(vop2, ovl_port_mux_cfg, port_mux_cfg);
	8829	+ vp->skip_vsync = true;
	8830	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
	8831	+ vop2->port_mux_cfg = port_mux_cfg;
	8832	+ vop2_wait_for_port_mux_done(vop2);
	8833	+ }
	8834	+ spin_unlock(&vop2->reg_lock);
6206	8835	}
6207	8836
6208	8837	static void vop2_setup_layer_mixer_for_vp(struct vop2_video_port *vp,
..	..	@@ -6216,15 +8845,12 @@
6216	8845	struct vop2_win *win;
6217	8846	u8 used_layers = 0;
6218	8847	u8 layer_id, win_phys_id;
6219		- u16 port_mux_cfg;
6220	8848	u32 layer_cfg_reg_offset = layer->regs->layer_sel.offset;
6221	8849	u8 nr_layers = vp->nr_layers;
6222	8850	u32 old_layer_cfg = 0;
6223	8851	u32 new_layer_cfg = 0;
6224	8852	u32 atv_layer_cfg;
6225	8853	int i;
6226		-
6227		- port_mux_cfg = vop2_calc_bg_ovl_and_port_mux(vp);
6228	8854
6229	8855	/*
6230	8856	* Win and layer must map one by one, if a win is selected
..	..	@@ -6240,6 +8866,10 @@
6240	8866
6241	8867	old_layer_cfg = vop2->regsbak[layer_cfg_reg_offset >> 2];
6242	8868	new_layer_cfg = old_layer_cfg;
	8869	+
	8870	+ if (vp->hdr10_at_splice_mode)
	8871	+ nr_layers *= 2;
	8872	+
6243	8873	for (i = 0; i < nr_layers; i++) {
6244	8874	layer = &vop2->layers[used_layers + i];
6245	8875	zpos = &vop2_zpos[i];
..	..	@@ -6253,21 +8883,21 @@
6253	8883	layer = &vop2->layers[layer_id];
6254	8884	win = vop2_find_win_by_phys_id(vop2, win_phys_id);
6255	8885	new_layer_cfg = vop2_layer_cfg_update(layer, new_layer_cfg, win->layer_sel_id[vp->id]);
6256		- win->layer_id = layer->id;
6257	8886	win->layer_id = layer_id;
6258	8887	layer->win_phys_id = win_phys_id;
6259	8888	}
6260	8889
6261	8890	atv_layer_cfg = vop2_read_layer_cfg(vop2);
6262		- if ((new_layer_cfg != old_layer_cfg) &&
6263		- (atv_layer_cfg != old_layer_cfg)) {
	8891	+ if (new_layer_cfg != old_layer_cfg &&
	8892	+ atv_layer_cfg != old_layer_cfg &&
	8893	+ !vp->splice_mode_right) {
6264	8894	dev_dbg(vop2->dev, "wait old_layer_sel: 0x%x\n", old_layer_cfg);
6265	8895	vop2_wait_for_layer_cfg_done(vop2, old_layer_cfg);
6266	8896	}
6267	8897	vop2_writel(vop2, RK3568_OVL_LAYER_SEL, new_layer_cfg);
6268		- VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
	8898	+ if (new_layer_cfg != old_layer_cfg)
	8899	+ VOP_CTRL_SET(vop2, ovl_cfg_done_port, vp->id);
6269	8900	VOP_CTRL_SET(vop2, ovl_port_mux_cfg_done_imd, 0);
6270		- vop2_setup_port_mux(vp, port_mux_cfg);
6271	8901	}
6272	8902
6273	8903	static void vop3_setup_layer_sel_for_vp(struct vop2_video_port *vp,
..	..	@@ -6310,7 +8940,9 @@
6310	8940	struct vop2 *vop2 = vp->vop2;
6311	8941	const struct vop2_data *vop2_data = vop2->data;
6312	8942	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
6313		- struct drm_crtc *crtc = &vp->crtc;
	8943	+ struct vop2_video_port *left_vp = vp->left_vp;
	8944	+ struct drm_crtc *crtc = &vp->rockchip_crtc.crtc;
	8945	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6314	8946	struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
6315	8947	u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
6316	8948	u16 hdisplay = adjusted_mode->crtc_hdisplay;
..	..	@@ -6329,13 +8961,30 @@
6329	8961	}
6330	8962	}
6331	8963
6332		- if (!vp->hdr_in)
	8964	+ if (!vp->hdr_in \|\|
	8965	+ (vop2->version == VOP_VERSION_RK3588 && vp->hdr_out))
6333	8966	bg_dly -= vp->bg_ovl_dly;
6334	8967
6335		- pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
6336		- if (vop2->version >= VOP_VERSION_RK3588 && hsync_len < 8)
	8968	+ /*
	8969	+ * right vp share the same crtc state in splice mode
	8970	+ */
	8971	+ if (vp->splice_mode_right) {
	8972	+ vcstate = to_rockchip_crtc_state(left_vp->rockchip_crtc.crtc.state);
	8973	+ adjusted_mode = &left_vp->rockchip_crtc.crtc.state->adjusted_mode;
	8974	+ hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
	8975	+ hdisplay = adjusted_mode->crtc_hdisplay;
	8976	+ }
	8977	+
	8978	+ if (vcstate->splice_mode)
	8979	+ pre_scan_dly = bg_dly + (hdisplay >> 2) - 1;
	8980	+ else
	8981	+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
	8982	+
	8983	+ if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8)
6337	8984	hsync_len = 8;
	8985	+
6338	8986	pre_scan_dly = (pre_scan_dly << 16) \| hsync_len;
	8987	+
6339	8988	VOP_MODULE_SET(vop2, vp, bg_dly, bg_dly);
6340	8989	VOP_MODULE_SET(vop2, vp, pre_scan_htiming, pre_scan_dly);
6341	8990	}
..	..	@@ -6353,8 +9002,17 @@
6353	9002	for (i = 0; i < vp->nr_layers; i++) {
6354	9003	zpos = &vop2_zpos[i];
6355	9004	win = vop2_find_win_by_phys_id(vop2, zpos->win_phys_id);
6356		- plane = &win->base;
6357		- vpstate = to_vop2_plane_state(plane->state);
	9005	+ /*
	9006	+ * right vp share the same plane state in splice mode
	9007	+ */
	9008	+ if (vp->splice_mode_right) {
	9009	+ plane = &win->left_win->base;
	9010	+ vpstate = to_vop2_plane_state(plane->state);
	9011	+ } else {
	9012	+ plane = &win->base;
	9013	+ vpstate = to_vop2_plane_state(plane->state);
	9014	+ }
	9015	+
6358	9016	if (vp->hdr_in && !vp->hdr_out && !vpstate->hdr_in) {
6359	9017	dly = win->dly[VOP2_DLY_MODE_HISO_S];
6360	9018	dly += vp->bg_ovl_dly;
..	..	@@ -6371,22 +9029,128 @@
6371	9029	}
6372	9030	}
6373	9031
	9032	+static void rk3588_vop2_setup_hdr10_splice_layer_mixer(struct drm_crtc *crtc,
	9033	+ struct vop2_zpos *vop2_zpos,
	9034	+ struct vop2_zpos *vop2_zpos_splice)
	9035	+{
	9036	+ int zpos_id, i;
	9037	+ struct vop2_zpos *vop2_zpos_splice_hdr;
	9038	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9039	+ struct vop2 *vop2 = vp->vop2;
	9040	+
	9041	+ vop2_zpos_splice_hdr = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9042	+ GFP_KERNEL);
	9043	+ if (!vop2_zpos_splice_hdr)
	9044	+ goto out;
	9045	+
	9046	+ zpos_id = 0;
	9047	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9048	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[0].win_phys_id;
	9049	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[0].plane;
	9050	+
	9051	+ zpos_id++;
	9052	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9053	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[0].win_phys_id;
	9054	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[0].plane;
	9055	+
	9056	+ for (i = 1; i < vp->nr_layers; i++) {
	9057	+ zpos_id++;
	9058	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9059	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos[i].win_phys_id;
	9060	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos[i].plane;
	9061	+ }
	9062	+
	9063	+ for (i = 1; i < vp->nr_layers; i++) {
	9064	+ zpos_id++;
	9065	+ vop2_zpos_splice_hdr[zpos_id].zpos = zpos_id;
	9066	+ vop2_zpos_splice_hdr[zpos_id].win_phys_id = vop2_zpos_splice[i].win_phys_id;
	9067	+ vop2_zpos_splice_hdr[zpos_id].plane = vop2_zpos_splice[i].plane;
	9068	+ }
	9069	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos_splice_hdr);
	9070	+
	9071	+out:
	9072	+ kfree(vop2_zpos_splice_hdr);
	9073	+}
	9074	+
	9075	+static void vop2_crtc_update_vrr(struct drm_crtc *crtc)
	9076	+{
	9077	+ struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
	9078	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9079	+ struct vop2 *vop2 = vp->vop2;
	9080	+ struct drm_display_mode *adjust_mode = &crtc->state->adjusted_mode;
	9081	+
	9082	+ unsigned int vrefresh;
	9083	+ unsigned int new_vtotal, vfp, new_vfp;
	9084	+
	9085	+ if (!vp->refresh_rate_change)
	9086	+ return;
	9087	+
	9088	+ if (!vcstate->min_refresh_rate \|\| !vcstate->max_refresh_rate)
	9089	+ return;
	9090	+
	9091	+ if (vcstate->request_refresh_rate < vcstate->min_refresh_rate \|\|
	9092	+ vcstate->request_refresh_rate > vcstate->max_refresh_rate) {
	9093	+ DRM_ERROR("invalid rate:%d\n", vcstate->request_refresh_rate);
	9094	+ return;
	9095	+ }
	9096	+
	9097	+ vrefresh = drm_mode_vrefresh(adjust_mode);
	9098	+
	9099	+ /* calculate new vfp for new refresh rate */
	9100	+ new_vtotal = adjust_mode->vtotal * vrefresh / vcstate->request_refresh_rate;
	9101	+ vfp = adjust_mode->vsync_start - adjust_mode->vdisplay;
	9102	+ new_vfp = vfp + new_vtotal - adjust_mode->vtotal;
	9103	+
	9104	+ /* config vop2 vtotal register */
	9105	+ VOP_MODULE_SET(vop2, vp, dsp_vtotal, new_vtotal);
	9106	+
	9107	+ /* config dsc vtotal register */
	9108	+ if (vcstate->dsc_enable) {
	9109	+ struct vop2_dsc *dsc;
	9110	+
	9111	+ dsc = &vop2->dscs[vcstate->dsc_id];
	9112	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9113	+
	9114	+ if (vcstate->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
	9115	+ dsc = &vop2->dscs[vcstate->dsc_id ? 0 : 1];
	9116	+ VOP_MODULE_SET(vop2, dsc, dsc_vtotal, new_vtotal);
	9117	+ }
	9118	+ }
	9119	+
	9120	+ /* config all connectors attach to this crtc */
	9121	+ rockchip_connector_update_vfp_for_vrr(crtc, adjust_mode, new_vfp);
	9122	+}
	9123	+
6374	9124	static void vop2_crtc_atomic_begin(struct drm_crtc crtc, struct drm_crtc_state old_crtc_state)
6375	9125	{
6376	9126	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6377	9127	struct vop2 *vop2 = vp->vop2;
	9128	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9129	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
6378	9130	struct drm_plane *plane;
6379	9131	struct vop2_plane_state *vpstate;
6380	9132	struct vop2_zpos *vop2_zpos;
	9133	+ struct vop2_zpos *vop2_zpos_splice;
6381	9134	struct vop2_cluster cluster;
6382	9135	uint8_t nr_layers = 0;
	9136	+ uint8_t splice_nr_layers = 0;
	9137	+ bool hdr10_in = false;
	9138	+ bool hdr10_at_splice_mode = false;
6383	9139	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6384		- const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
6385	9140
6386	9141	vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
6387	9142	vop2_zpos = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos), GFP_KERNEL);
6388	9143	if (!vop2_zpos)
6389	9144	return;
	9145	+ if (vcstate->splice_mode) {
	9146	+ vop2_zpos_splice = kmalloc_array(vop2->data->win_size, sizeof(*vop2_zpos),
	9147	+ GFP_KERNEL);
	9148	+ if (!vop2_zpos_splice)
	9149	+ goto out;
	9150	+ }
	9151	+
	9152	+ if (vop2->version == VOP_VERSION_RK3588)
	9153	+ vop2_crtc_update_vrr(crtc);
6390	9154
6391	9155	/* Process cluster sub windows overlay. */
6392	9156	drm_atomic_crtc_for_each_plane(plane, crtc) {
..	..	@@ -6396,9 +9160,13 @@
6396	9160	win->two_win_mode = false;
6397	9161	if (!(win->feature & WIN_FEATURE_CLUSTER_SUB))
6398	9162	continue;
	9163	+ if (vcstate->splice_mode)
	9164	+ DRM_ERROR("vp%d %s not supported two win mode at splice mode\n",
	9165	+ vp->id, win->name);
6399	9166	main_win = vop2_find_win_by_phys_id(vop2, win->phys_id);
6400	9167	cluster.main = main_win;
6401	9168	cluster.sub = win;
	9169	+ cluster.splice_mode = false;
6402	9170	win->two_win_mode = true;
6403	9171	main_win->two_win_mode = true;
6404	9172	vop2_setup_cluster_alpha(vop2, &cluster);
..	..	@@ -6410,6 +9178,7 @@
6410	9178
6411	9179	drm_atomic_crtc_for_each_plane(plane, crtc) {
6412	9180	struct vop2_win *win = to_vop2_win(plane);
	9181	+ struct vop2_win *splice_win;
6413	9182	struct vop2_video_port *old_vp;
6414	9183	uint8_t old_vp_id;
6415	9184
..	..	@@ -6429,35 +9198,93 @@
6429	9198	vop2_zpos[nr_layers].win_phys_id = win->phys_id;
6430	9199	vop2_zpos[nr_layers].zpos = vpstate->zpos;
6431	9200	vop2_zpos[nr_layers].plane = plane;
	9201	+
	9202	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "%s active zpos:%d for vp%d from vp%d\n",
	9203	+ win->name, vpstate->zpos, vp->id, old_vp->id);
	9204	+ /* left and right win may have different number */
	9205	+ if (vcstate->splice_mode) {
	9206	+ splice_win = vop2_find_win_by_phys_id(vop2, win->splice_win_id);
	9207	+ splice_win->splice_mode_right = true;
	9208	+ splice_win->left_win = win;
	9209	+ win->splice_win = splice_win;
	9210	+
	9211	+ old_vp_id = ffs(splice_win->vp_mask);
	9212	+ old_vp_id = (old_vp_id == 0) ? 0 : old_vp_id - 1;
	9213	+ old_vp = &vop2->vps[old_vp_id];
	9214	+ old_vp->win_mask &= ~BIT(splice_win->phys_id);
	9215	+ splice_vp->win_mask \|= BIT(splice_win->phys_id);
	9216	+ splice_win->vp_mask = BIT(splice_vp->id);
	9217	+ hdr10_in \|= vpstate->eotf == HDMI_EOTF_SMPTE_ST2084 ? true : false;
	9218	+ vop2_zpos_splice[splice_nr_layers].win_phys_id = splice_win->phys_id;
	9219	+ vop2_zpos_splice[splice_nr_layers].zpos = vpstate->zpos;
	9220	+ vop2_zpos_splice[splice_nr_layers].plane = &splice_win->base;
	9221	+ splice_nr_layers++;
	9222	+ DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
	9223	+ splice_win->name, vpstate->zpos, splice_vp->id, old_vp->id);
	9224	+ }
6432	9225	nr_layers++;
6433		- DRM_DEV_DEBUG(vop2->dev, "%s active zpos:%d for vp%d from vp%d\n",
6434		- win->name, vpstate->zpos, vp->id, old_vp->id);
6435	9226	}
6436	9227
6437		- DRM_DEV_DEBUG(vop2->dev, "vp%d: %d windows, active layers %d\n",
6438		- vp->id, hweight32(vp->win_mask), nr_layers);
	9228	+ if (vcstate->splice_mode) {
	9229	+ if (hdr10_in)
	9230	+ hdr10_at_splice_mode = true;
	9231	+
	9232	+ splice_vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9233	+ }
	9234	+ vp->hdr10_at_splice_mode = hdr10_at_splice_mode;
	9235	+
	9236	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_OVERLAY, "vp%d: %d windows, active layers %d\n",
	9237	+ vp->id, hweight32(vp->win_mask), nr_layers);
6439	9238	if (nr_layers) {
6440	9239	vp->nr_layers = nr_layers;
6441	9240
6442	9241	sort(vop2_zpos, nr_layers, sizeof(vop2_zpos[0]), vop2_zpos_cmp, NULL);
6443	9242
	9243	+ if (!vp->hdr10_at_splice_mode) {
	9244	+ if (is_vop3(vop2)) {
	9245	+ vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
	9246	+ } else {
	9247	+ vop2_setup_port_mux(vp);
	9248	+ vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
	9249	+ }
	9250	+ }
	9251	+
6444	9252	if (is_vop3(vop2)) {
6445		- vop3_setup_layer_sel_for_vp(vp, vop2_zpos);
6446	9253	if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
6447	9254	vop3_setup_dynamic_hdr(vp, vop2_zpos[0].win_phys_id);
6448	9255	vop3_setup_alpha(vp, vop2_zpos);
6449	9256	vop3_setup_pipe_dly(vp, vop2_zpos);
6450	9257	} else {
6451		- vop2_setup_layer_mixer_for_vp(vp, vop2_zpos);
6452	9258	vop2_setup_hdr10(vp, vop2_zpos[0].win_phys_id);
6453	9259	vop2_setup_alpha(vp, vop2_zpos);
6454	9260	vop2_setup_dly_for_vp(vp);
6455	9261	vop2_setup_dly_for_window(vp, vop2_zpos);
6456	9262	}
	9263	+
	9264	+ if (vcstate->splice_mode) {/* Fixme for VOP3 8K */
	9265	+ splice_vp->nr_layers = splice_nr_layers;
	9266	+
	9267	+ sort(vop2_zpos_splice, splice_nr_layers, sizeof(vop2_zpos_splice[0]),
	9268	+ vop2_zpos_cmp, NULL);
	9269	+
	9270	+ vop2_setup_port_mux(splice_vp);
	9271	+ if (!vp->hdr10_at_splice_mode)
	9272	+ vop2_setup_layer_mixer_for_vp(splice_vp, vop2_zpos_splice);
	9273	+ vop2_setup_hdr10(splice_vp, vop2_zpos_splice[0].win_phys_id);
	9274	+ vop2_setup_alpha(splice_vp, vop2_zpos_splice);
	9275	+ vop2_setup_dly_for_vp(splice_vp);
	9276	+ vop2_setup_dly_for_window(splice_vp, vop2_zpos_splice);
	9277	+
	9278	+ if (vop2->version == VOP_VERSION_RK3588 &&
	9279	+ vp->hdr10_at_splice_mode)
	9280	+ rk3588_vop2_setup_hdr10_splice_layer_mixer(crtc, vop2_zpos, vop2_zpos_splice);
	9281	+ }
6457	9282	} else {
6458	9283	if (!is_vop3(vop2)) {
6459	9284	vop2_calc_bg_ovl_and_port_mux(vp);
6460	9285	vop2_setup_dly_for_vp(vp);
	9286	+ if (vcstate->splice_mode)
	9287	+ vop2_setup_dly_for_vp(splice_vp);
6461	9288	} else {
6462	9289	vop3_setup_pipe_dly(vp, NULL);
6463	9290	}
..	..	@@ -6466,6 +9293,7 @@
6466	9293	/* The pre alpha overlay of Cluster still need process in one win mode. */
6467	9294	drm_atomic_crtc_for_each_plane(plane, crtc) {
6468	9295	struct vop2_win *win = to_vop2_win(plane);
	9296	+ struct vop2_win *splice_win;
6469	9297
6470	9298	if (!(win->feature & WIN_FEATURE_CLUSTER_MAIN))
6471	9299	continue;
..	..	@@ -6473,9 +9301,19 @@
6473	9301	continue;
6474	9302	cluster.main = win;
6475	9303	cluster.sub = NULL;
	9304	+ cluster.splice_mode = false;
6476	9305	vop2_setup_cluster_alpha(vop2, &cluster);
	9306	+ if (vcstate->splice_mode) {
	9307	+ splice_win = win->splice_win;
	9308	+ cluster.main = splice_win;
	9309	+ cluster.splice_mode = true;
	9310	+ vop2_setup_cluster_alpha(vop2, &cluster);
	9311	+ }
6477	9312	}
6478	9313
	9314	+ if (vcstate->splice_mode)
	9315	+ kfree(vop2_zpos_splice);
	9316	+out:
6479	9317	kfree(vop2_zpos);
6480	9318	}
6481	9319
..	..	@@ -6586,6 +9424,12 @@
6586	9424	bcsh_state.cos_hue = cos_hue;
6587	9425
6588	9426	vop2_bcsh_reg_update(vcstate, vp, &bcsh_state);
	9427	+ if (vcstate->splice_mode) {
	9428	+ const struct vop2_video_port_data *vp_data = &vop2->data->vp[vp->id];
	9429	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
	9430	+
	9431	+ vop2_bcsh_reg_update(vcstate, splice_vp, &bcsh_state);
	9432	+ }
6589	9433	}
6590	9434
6591	9435	static void vop3_post_csc_config(struct drm_crtc crtc, struct post_acm acm, struct post_csc *csc)
..	..	@@ -6671,25 +9515,18 @@
6671	9515	u32 value;
6672	9516	int i;
6673	9517
6674		- writel(0, vop2->acm_regs + RK3528_ACM_CTRL);
6675		- VOP_MODULE_SET(vop2, vp, acm_bypass_en, 0);
6676		-
6677		- if (!acm \|\| !acm->acm_enable)
	9518	+ if (!acm) {
	9519	+ writel(0x2, vop2->acm_regs + RK3528_ACM_CTRL);
	9520	+ VOP_MODULE_SET(vop2, vp, acm_bypass_en, 1);
6678	9521	return;
6679		-
6680		- /*
6681		- * If acm update parameters, it need disable acm in the first frame,
6682		- * then update parameters and enable acm in second frame.
6683		- */
6684		- vop2_cfg_done(crtc);
6685		- readx_poll_timeout(readl, vop2->acm_regs + RK3528_ACM_CTRL, value, !value, 200, 50000);
6686		-
6687		- value = RK3528_ACM_ENABLE + ((adjusted_mode->hdisplay & 0xfff) << 8) +
6688		- ((adjusted_mode->vdisplay & 0xfff) << 20);
6689		- writel(value, vop2->acm_regs + RK3528_ACM_CTRL);
6690		-
	9522	+ }
6691	9523
6692	9524	writel(1, vop2->acm_regs + RK3528_ACM_FETCH_START);
	9525	+
	9526	+ value = (acm->acm_enable & 0x1) + ((adjusted_mode->hdisplay & 0xfff) << 8) +
	9527	+ ((adjusted_mode->vdisplay & 0xfff) << 20);
	9528	+ writel(value, vop2->acm_regs + RK3528_ACM_CTRL);
	9529	+ VOP_MODULE_SET(vop2, vp, acm_bypass_en, acm->acm_enable ? 0 : 1);
6693	9530
6694	9531	value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
6695	9532	((acm->s_gain << 20) & 0x3ff00000);
..	..	@@ -6728,23 +9565,14 @@
6728	9565	static void vop3_post_config(struct drm_crtc *crtc)
6729	9566	{
6730	9567	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6731		- struct vop2_video_port *vp = to_vop2_video_port(crtc);
6732	9568	struct post_acm *acm;
6733	9569	struct post_csc *csc;
6734	9570
6735		- csc = vcstate->post_csc_data ? (struct post_csc *)vcstate->post_csc_data->data : NULL;
6736		- if (csc && memcmp(&vp->csc_info, csc, sizeof(struct post_csc)))
6737		- memcpy(&vp->csc_info, csc, sizeof(struct post_csc));
6738		- vop3_post_csc_config(crtc, &vp->acm_info, &vp->csc_info);
6739		-
6740	9571	acm = vcstate->acm_lut_data ? (struct post_acm *)vcstate->acm_lut_data->data : NULL;
	9572	+ vop3_post_acm_config(crtc, acm);
6741	9573
6742		- if (acm && memcmp(&vp->acm_info, acm, sizeof(struct post_acm))) {
6743		- memcpy(&vp->acm_info, acm, sizeof(struct post_acm));
6744		- vop3_post_acm_config(crtc, &vp->acm_info);
6745		- } else if (crtc->state->active_changed) {
6746		- vop3_post_acm_config(crtc, &vp->acm_info);
6747		- }
	9574	+ csc = vcstate->post_csc_data ? (struct post_csc *)vcstate->post_csc_data->data : NULL;
	9575	+ vop3_post_csc_config(crtc, acm, csc);
6748	9576	}
6749	9577
6750	9578	static void vop2_cfg_update(struct drm_crtc *crtc,
..	..	@@ -6755,6 +9583,7 @@
6755	9583	struct vop2 *vop2 = vp->vop2;
6756	9584	const struct vop2_data *vop2_data = vop2->data;
6757	9585	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	9586	+ struct vop2_video_port *splice_vp = &vop2->vps[vp_data->splice_vp_id];
6758	9587	uint32_t val;
6759	9588	uint32_t r, g, b;
6760	9589	uint8_t out_mode;
..	..	@@ -6769,10 +9598,7 @@
6769	9598	out_mode = vcstate->output_mode;
6770	9599	VOP_MODULE_SET(vop2, vp, out_mode, out_mode);
6771	9600
6772		- if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
6773		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, DSP_RB_SWAP);
6774		- else
6775		- VOP_MODULE_SET(vop2, vp, dsp_data_swap, 0);
	9601	+ vop2_post_color_swap(crtc);
6776	9602
6777	9603	vop2_dither_setup(crtc);
6778	9604
..	..	@@ -6797,15 +9623,86 @@
6797	9623	}
6798	9624
6799	9625	VOP_MODULE_SET(vop2, vp, dsp_background, val);
	9626	+ if (vcstate->splice_mode) {
	9627	+ VOP_MODULE_SET(vop2, splice_vp, overlay_mode, vcstate->yuv_overlay);
	9628	+ VOP_MODULE_SET(vop2, splice_vp, dsp_background, val);
	9629	+ }
6800	9630
6801	9631	vop2_tv_config_update(crtc, old_crtc_state);
6802	9632
6803		- vop2_post_config(crtc);
6804		-
6805		- spin_unlock(&vop2->reg_lock);
	9633	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN)
	9634	+ vop2_post_config(crtc);
6806	9635
6807	9636	if (vp_data->feature & (VOP_FEATURE_POST_ACM \| VOP_FEATURE_POST_CSC))
6808	9637	vop3_post_config(crtc);
	9638	+
	9639	+ spin_unlock(&vop2->reg_lock);
	9640	+}
	9641	+
	9642	+static void vop2_sleep_scan_line_time(struct vop2_video_port *vp, int scan_line)
	9643	+{
	9644	+ struct vop2 *vop2 = vp->vop2;
	9645	+ struct drm_display_mode *mode = &vp->rockchip_crtc.crtc.state->adjusted_mode;
	9646	+
	9647	+ if (scan_line <= 0)
	9648	+ return;
	9649	+
	9650	+ if (IS_ENABLED(CONFIG_HIGH_RES_TIMERS) &&
	9651	+ (!IS_ENABLED(CONFIG_NO_GKI) \|\| (hrtimer_resolution != LOW_RES_NSEC))) {
	9652	+ u16 htotal = VOP_MODULE_GET(vop2, vp, htotal_pw) >> 16;
	9653	+ u32 linedur_ns = div_u64((u64) htotal * 1000000, mode->crtc_clock);
	9654	+ u64 sleep_time = linedur_ns * scan_line;
	9655	+
	9656	+ sleep_time = div_u64((sleep_time + 1000), 1000);
	9657	+ if (sleep_time > 200)
	9658	+ usleep_range(sleep_time, sleep_time);
	9659	+ }
	9660	+}
	9661	+
	9662	+/*
	9663	+ * return scan timing from FS to the assigned wait line
	9664	+ */
	9665	+static void vop2_wait_for_scan_timing_max_to_assigned_line(struct vop2_video_port *vp,
	9666	+ u32 current_line,
	9667	+ u32 wait_line)
	9668	+
	9669	+{
	9670	+ struct vop2 *vop2 = vp->vop2;
	9671	+ u32 vcnt;
	9672	+ int ret;
	9673	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	9674	+ int delta_line = vtotal - current_line;
	9675	+
	9676	+ vop2_sleep_scan_line_time(vp, delta_line);
	9677	+ if (vop2_read_vcnt(vp) < wait_line)
	9678	+ return;
	9679	+
	9680	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt < wait_line, 0, 50 * 1000);
	9681	+ if (ret)
	9682	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from FS to the assigned wait line: %d, vcnt:%d, ret:%d\n",
	9683	+ wait_line, vcnt, ret);
	9684	+}
	9685	+
	9686	+/*
	9687	+ * return scan timing from the assigned wait line
	9688	+ */
	9689	+static void vop2_wait_for_scan_timing_from_the_assigned_line(struct vop2_video_port *vp,
	9690	+ u32 current_line,
	9691	+ u32 wait_line)
	9692	+{
	9693	+ struct vop2 *vop2 = vp->vop2;
	9694	+ u32 vcnt;
	9695	+ int ret;
	9696	+ int delta_line = wait_line - current_line;
	9697	+
	9698	+ vop2_sleep_scan_line_time(vp, delta_line);
	9699	+ if (vop2_read_vcnt(vp) > wait_line)
	9700	+ return;
	9701	+
	9702	+ ret = readx_poll_timeout_atomic(vop2_read_vcnt, vp, vcnt, vcnt > wait_line, 0, 50 * 1000);
	9703	+ if (ret)
	9704	+ DRM_DEV_ERROR(vop2->dev, "wait scan timing from the assigned wait line: %d, vcnt:%d, ret:%d\n",
	9705	+ wait_line, vcnt, ret);
6809	9706	}
6810	9707
6811	9708	static void vop2_crtc_atomic_flush(struct drm_crtc crtc, struct drm_crtc_state old_cstate)
..	..	@@ -6813,11 +9710,26 @@
6813	9710	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
6814	9711	struct drm_atomic_state *old_state = old_cstate->state;
6815	9712	struct vop2_video_port *vp = to_vop2_video_port(crtc);
6816		- struct drm_plane_state *old_pstate;
6817	9713	struct vop2 *vop2 = vp->vop2;
	9714	+ struct drm_plane_state *old_pstate;
6818	9715	struct drm_plane *plane;
6819	9716	unsigned long flags;
6820	9717	int i, ret;
	9718	+ struct vop2_wb *wb = &vop2->wb;
	9719	+ struct drm_writeback_connector *wb_conn = &wb->conn;
	9720	+ struct drm_connector_state *conn_state = wb_conn->base.state;
	9721	+
	9722	+ if (conn_state && conn_state->writeback_job && conn_state->writeback_job->fb) {
	9723	+ u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal);
	9724	+ u32 current_line = vop2_read_vcnt(vp);
	9725	+
	9726	+ if (current_line > vtotal * 7 >> 3)
	9727	+ vop2_wait_for_scan_timing_max_to_assigned_line(vp, current_line, vtotal * 7 >> 3);
	9728	+
	9729	+ current_line = vop2_read_vcnt(vp);
	9730	+ if (current_line < vtotal >> 3)
	9731	+ vop2_wait_for_scan_timing_from_the_assigned_line(vp, current_line, vtotal >> 3);
	9732	+ }
6821	9733
6822	9734	vop2_cfg_update(crtc, old_cstate);
6823	9735
..	..	@@ -6843,12 +9755,13 @@
6843	9755	vp->gamma_lut = crtc->state->gamma_lut->data;
6844	9756	vop2_crtc_atomic_gamma_set(crtc, crtc->state);
6845	9757	}
6846		-
	9758	+#if defined(CONFIG_ROCKCHIP_DRM_CUBIC_LUT)
6847	9759	if (crtc->state->cubic_lut \|\| vp->cubic_lut) {
6848	9760	if (crtc->state->cubic_lut)
6849	9761	vp->cubic_lut = crtc->state->cubic_lut->data;
6850	9762	vop2_crtc_atomic_cubic_lut_set(crtc, crtc->state);
6851	9763	}
	9764	+#endif
6852	9765	} else {
6853	9766	VOP_MODULE_SET(vop2, vp, cubic_lut_update_en, 0);
6854	9767	}
..	..	@@ -6861,6 +9774,9 @@
6861	9774	spin_lock_irqsave(&vop2->irq_lock, flags);
6862	9775	vop2_wb_commit(crtc);
6863	9776	vop2_cfg_done(crtc);
	9777	+
	9778	+ if (vp->mcu_timing.mcu_pix_total)
	9779	+ VOP_MODULE_SET(vop2, vp, mcu_hold_mode, 0);
6864	9780
6865	9781	spin_unlock_irqrestore(&vop2->irq_lock, flags);
6866	9782
..	..	@@ -6902,6 +9818,7 @@
6902	9818	}
6903	9819
6904	9820	static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
	9821	+ .mode_valid = vop2_crtc_mode_valid,
6905	9822	.mode_fixup = vop2_crtc_mode_fixup,
6906	9823	.atomic_check = vop2_crtc_atomic_check,
6907	9824	.atomic_begin = vop2_crtc_atomic_begin,
..	..	@@ -6941,6 +9858,9 @@
6941	9858	{
6942	9859	struct rockchip_crtc_state vcstate, old_vcstate;
6943	9860	struct vop2_video_port *vp = to_vop2_video_port(crtc);
	9861	+
	9862	+ if (WARN_ON(!crtc->state))
	9863	+ return NULL;
6944	9864
6945	9865	old_vcstate = to_rockchip_crtc_state(crtc->state);
6946	9866	vcstate = kmemdup(old_vcstate, sizeof(*old_vcstate), GFP_KERNEL);
..	..	@@ -7068,36 +9988,51 @@
7068	9988	return 0;
7069	9989	}
7070	9990
7071		- if (property == private->alpha_scale_prop) {
7072		- *val = (vop2->data->feature & VOP_FEATURE_ALPHA_SCALE) ? 1 : 0;
7073		- return 0;
7074		- }
7075		-
7076		- if (property == vop2->aclk_prop) {
	9991	+ if (property == private->aclk_prop) {
7077	9992	/* KHZ, keep align with mode->clock */
7078	9993	*val = clk_get_rate(vop2->aclk) / 1000;
7079	9994	return 0;
7080	9995	}
7081	9996
7082		-
7083		- if (property == vop2->bg_prop) {
	9997	+ if (property == private->bg_prop) {
7084	9998	*val = vcstate->background;
7085	9999	return 0;
7086	10000	}
7087	10001
7088		- if (property == vop2->line_flag_prop) {
	10002	+ if (property == private->line_flag_prop) {
7089	10003	*val = vcstate->line_flag;
7090	10004	return 0;
7091	10005	}
7092	10006
7093		- if (property == vp->hdr_ext_data_prop)
	10007	+ if (property == vp->variable_refresh_rate_prop) {
	10008	+ *val = vcstate->request_refresh_rate;
7094	10009	return 0;
	10010	+ }
7095	10011
7096		- if (property == vp->acm_lut_data_prop)
	10012	+ if (property == vp->max_refresh_rate_prop) {
	10013	+ *val = vcstate->max_refresh_rate;
7097	10014	return 0;
	10015	+ }
7098	10016
7099		- if (property == vp->post_csc_data_prop)
	10017	+ if (property == vp->min_refresh_rate_prop) {
	10018	+ *val = vcstate->min_refresh_rate;
7100	10019	return 0;
	10020	+ }
	10021	+
	10022	+ if (property == vp->hdr_ext_data_prop) {
	10023	+ *val = vcstate->hdr_ext_data ? vcstate->hdr_ext_data->base.id : 0;
	10024	+ return 0;
	10025	+ }
	10026	+
	10027	+ if (property == vp->acm_lut_data_prop) {
	10028	+ *val = vcstate->acm_lut_data ? vcstate->acm_lut_data->base.id : 0;
	10029	+ return 0;
	10030	+ }
	10031	+
	10032	+ if (property == vp->post_csc_data_prop) {
	10033	+ *val = vcstate->post_csc_data ? vcstate->post_csc_data->base.id : 0;
	10034	+ return 0;
	10035	+ }
7101	10036
7102	10037	DRM_ERROR("failed to get vop2 crtc property: %s\n", property->name);
7103	10038
..	..	@@ -7144,10 +10079,10 @@
7144	10079	uint64_t val)
7145	10080	{
7146	10081	struct drm_device *drm_dev = crtc->dev;
	10082	+ struct rockchip_drm_private *private = drm_dev->dev_private;
7147	10083	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
7148	10084	struct drm_mode_config *mode_config = &drm_dev->mode_config;
7149	10085	struct vop2_video_port *vp = to_vop2_video_port(crtc);
7150		- struct vop2 *vop2 = vp->vop2;
7151	10086	bool replaced = false;
7152	10087	int ret;
7153	10088
..	..	@@ -7172,13 +10107,28 @@
7172	10107	}
7173	10108
7174	10109
7175		- if (property == vop2->bg_prop) {
	10110	+ if (property == private->bg_prop) {
7176	10111	vcstate->background = val;
7177	10112	return 0;
7178	10113	}
7179	10114
7180		- if (property == vop2->line_flag_prop) {
	10115	+ if (property == private->line_flag_prop) {
7181	10116	vcstate->line_flag = val;
	10117	+ return 0;
	10118	+ }
	10119	+
	10120	+ if (property == vp->variable_refresh_rate_prop) {
	10121	+ vcstate->request_refresh_rate = val;
	10122	+ return 0;
	10123	+ }
	10124	+
	10125	+ if (property == vp->max_refresh_rate_prop) {
	10126	+ vcstate->max_refresh_rate = val;
	10127	+ return 0;
	10128	+ }
	10129	+
	10130	+ if (property == vp->min_refresh_rate_prop) {
	10131	+ vcstate->min_refresh_rate = val;
7182	10132	return 0;
7183	10133	}
7184	10134
..	..	@@ -7235,7 +10185,7 @@
7235	10185	struct vop2_video_port *vp = container_of(work, struct vop2_video_port, fb_unref_work);
7236	10186	struct drm_framebuffer *fb = val;
7237	10187
7238		- drm_crtc_vblank_put(&vp->crtc);
	10188	+ drm_crtc_vblank_put(&vp->rockchip_crtc.crtc);
7239	10189	if (!vp->vop2->skip_ref_fb)
7240	10190	drm_framebuffer_put(fb);
7241	10191	}
..	..	@@ -7306,6 +10256,7 @@
7306	10256	struct vop2_wb *wb = &vop2->wb;
7307	10257
7308	10258	VOP_MODULE_SET(vop2, wb, enable, 0);
	10259	+ VOP_CTRL_SET(vop2, wb_dma_finish_and_en, 0);
7309	10260	vop2_wb_cfg_done(vp);
7310	10261	}
7311	10262
..	..	@@ -7344,6 +10295,43 @@
7344	10295	}
7345	10296	}
7346	10297	spin_unlock_irqrestore(&wb->job_lock, flags);
	10298	+}
	10299	+
	10300	+static void vop2_dsc_isr(struct vop2 *vop2)
	10301	+{
	10302	+ const struct vop2_data *vop2_data = vop2->data;
	10303	+ struct vop2_dsc *dsc;
	10304	+ const struct dsc_error_info *dsc_error_ecw = vop2_data->dsc_error_ecw;
	10305	+ const struct dsc_error_info *dsc_error_buffer_flow = vop2_data->dsc_error_buffer_flow;
	10306	+ u32 dsc_error_status = 0, dsc_ecw = 0;
	10307	+ int i = 0, j = 0;
	10308	+
	10309	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	10310	+ dsc = &vop2->dscs[i];
	10311	+
	10312	+ if (!dsc->enabled)
	10313	+ continue;
	10314	+
	10315	+ dsc_error_status = VOP_MODULE_GET(vop2, dsc, dsc_error_status);
	10316	+ if (!dsc_error_status)
	10317	+ continue;
	10318	+ dsc_ecw = VOP_MODULE_GET(vop2, dsc, dsc_ecw);
	10319	+
	10320	+ for (j = 0; j < vop2_data->nr_dsc_ecw; j++) {
	10321	+ if (dsc_ecw == dsc_error_ecw[j].dsc_error_val) {
	10322	+ DRM_ERROR("dsc%d %s\n", dsc->id, dsc_error_ecw[j].dsc_error_info);
	10323	+ break;
	10324	+ }
	10325	+ }
	10326	+
	10327	+ if (dsc_ecw == 0x0120ffff) {
	10328	+ u32 offset = dsc->regs->dsc_status.offset;
	10329	+
	10330	+ for (j = 0; j < vop2_data->nr_dsc_buffer_flow; j++)
	10331	+ DRM_ERROR("dsc%d %s:0x%x\n", dsc->id, dsc_error_buffer_flow[j].dsc_error_info,
	10332	+ vop2_readl(vop2, offset + (j << 2)));
	10333	+ }
	10334	+ }
7347	10335	}
7348	10336
7349	10337	static irqreturn_t vop2_isr(int irq, void *data)
..	..	@@ -7400,7 +10388,7 @@
7400	10388
7401	10389	for (i = 0; i < vp_max; i++) {
7402	10390	vp = &vop2->vps[i];
7403		- crtc = &vp->crtc;
	10391	+ crtc = &vp->rockchip_crtc.crtc;
7404	10392	active_irqs = vp_irqs[i];
7405	10393	if (active_irqs & DSP_HOLD_VALID_INTR) {
7406	10394	complete(&vp->dsp_hold_completion);
..	..	@@ -7431,6 +10419,7 @@
7431	10419	}
7432	10420
7433	10421	if (active_irqs & FS_FIELD_INTR) {
	10422	+ rockchip_drm_dbg(vop2->dev, VOP_DEBUG_VSYNC, "vsync_vp%d\n", vp->id);
7434	10423	vop2_wb_handler(vp);
7435	10424	if (likely(!vp->skip_vsync) \|\| (vp->layer_sel_update == false)) {
7436	10425	drm_crtc_handle_vblank(crtc);
..	..	@@ -7462,6 +10451,9 @@
7462	10451	if (active_irqs)
7463	10452	DRM_ERROR("Unknown axi_bus%d IRQs: %02x\n", i, active_irqs);
7464	10453	}
	10454	+
	10455	+ if (vop2->data->nr_dscs)
	10456	+ vop2_dsc_isr(vop2);
7465	10457
7466	10458	vop2_core_clks_disable(vop2);
7467	10459	out:
..	..	@@ -7714,7 +10706,7 @@
7714	10706
7715	10707	for (i = 0; i < vop2_data->nr_vps; i++) {
7716	10708	vp = &vop2->vps[i];
7717		- crtc = &vp->crtc;
	10709	+ crtc = &vp->rockchip_crtc.crtc;
7718	10710	if (!crtc->dev)
7719	10711	continue;
7720	10712	vp_data = &vop2_data->vp[vp->id];
..	..	@@ -7751,27 +10743,6 @@
7751	10743	return 0;
7752	10744	}
7753	10745
7754		-static void vop2_cubic_lut_init(struct vop2 *vop2)
7755		-{
7756		- const struct vop2_data *vop2_data = vop2->data;
7757		- const struct vop2_video_port_data *vp_data;
7758		- struct vop2_video_port *vp;
7759		- struct drm_crtc *crtc;
7760		- int i;
7761		-
7762		- for (i = 0; i < vop2_data->nr_vps; i++) {
7763		- vp = &vop2->vps[i];
7764		- crtc = &vp->crtc;
7765		- if (!crtc->dev)
7766		- continue;
7767		- vp_data = &vop2_data->vp[vp->id];
7768		- vp->cubic_lut_len = vp_data->cubic_lut_len;
7769		-
7770		- if (vp->cubic_lut_len)
7771		- drm_crtc_enable_cubic_lut(crtc, vp->cubic_lut_len);
7772		- }
7773		-}
7774		-
7775	10746	static int vop2_crtc_create_plane_mask_property(struct vop2 *vop2,
7776	10747	struct drm_crtc *crtc,
7777	10748	uint32_t plane_mask)
..	..	@@ -7803,6 +10774,92 @@
7803	10774
7804	10775	vp->plane_mask_prop = prop;
7805	10776	drm_object_attach_property(&crtc->base, vp->plane_mask_prop, plane_mask);
	10777	+
	10778	+ return 0;
	10779	+}
	10780	+
	10781	+static int vop2_crtc_create_feature_property(struct vop2 vop2, struct drm_crtc crtc)
	10782	+{
	10783	+ const struct vop2_data *vop2_data = vop2->data;
	10784	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	10785	+ const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
	10786	+ struct drm_property *prop;
	10787	+ u64 feature = 0;
	10788	+
	10789	+ static const struct drm_prop_enum_list props[] = {
	10790	+ { ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE, "ALPHA_SCALE" },
	10791	+ { ROCKCHIP_DRM_CRTC_FEATURE_HDR10, "HDR10" },
	10792	+ { ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR, "NEXT_HDR" },
	10793	+ };
	10794	+
	10795	+ if (vp_data->feature & VOP_FEATURE_ALPHA_SCALE)
	10796	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE);
	10797	+ if (vp_data->feature & VOP_FEATURE_HDR10)
	10798	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_HDR10);
	10799	+ if (vp_data->feature & VOP_FEATURE_NEXT_HDR)
	10800	+ feature \|= BIT(ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR);
	10801	+
	10802	+ prop = drm_property_create_bitmask(vop2->drm_dev,
	10803	+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
	10804	+ props, ARRAY_SIZE(props),
	10805	+ 0xffffffff);
	10806	+ if (!prop) {
	10807	+ DRM_DEV_ERROR(vop2->dev, "create FEATURE prop for vp%d failed\n", vp->id);
	10808	+ return -ENOMEM;
	10809	+ }
	10810	+
	10811	+ vp->feature_prop = prop;
	10812	+ drm_object_attach_property(&crtc->base, vp->feature_prop, feature);
	10813	+
	10814	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_WIDTH",
	10815	+ 0, vop2->data->vp[vp->id].max_output.width);
	10816	+ if (!prop) {
	10817	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_WIDTH prop for vp%d failed\n", vp->id);
	10818	+ return -ENOMEM;
	10819	+ }
	10820	+ vp->output_width_prop = prop;
	10821	+ drm_object_attach_property(&crtc->base, vp->output_width_prop, 0);
	10822	+
	10823	+ prop = drm_property_create_range(vop2->drm_dev, DRM_MODE_PROP_IMMUTABLE, "OUTPUT_DCLK",
	10824	+ 0, rockchip_drm_get_dclk_by_width(vop2->data->vp[vp->id].max_output.width) * 1000);
	10825	+ if (!prop) {
	10826	+ DRM_DEV_ERROR(vop2->dev, "create OUTPUT_DCLK prop for vp%d failed\n", vp->id);
	10827	+ return -ENOMEM;
	10828	+ }
	10829	+ vp->output_dclk_prop = prop;
	10830	+ drm_object_attach_property(&crtc->base, vp->output_dclk_prop, 0);
	10831	+
	10832	+ return 0;
	10833	+}
	10834	+
	10835	+static int vop2_crtc_create_vrr_property(struct vop2 vop2, struct drm_crtc crtc)
	10836	+{
	10837	+ struct vop2_video_port *vp = to_vop2_video_port(crtc);
	10838	+ struct drm_property *prop;
	10839	+
	10840	+ prop = drm_property_create_range(vop2->drm_dev, 0, "variable refresh rate", 0, 144);
	10841	+ if (!prop) {
	10842	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	10843	+ return -ENOMEM;
	10844	+ }
	10845	+ vp->variable_refresh_rate_prop = prop;
	10846	+ drm_object_attach_property(&crtc->base, vp->variable_refresh_rate_prop, 0);
	10847	+
	10848	+ prop = drm_property_create_range(vop2->drm_dev, 0, "max refresh rate", 0, 144);
	10849	+ if (!prop) {
	10850	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	10851	+ return -ENOMEM;
	10852	+ }
	10853	+ vp->max_refresh_rate_prop = prop;
	10854	+ drm_object_attach_property(&crtc->base, vp->max_refresh_rate_prop, 0);
	10855	+
	10856	+ prop = drm_property_create_range(vop2->drm_dev, 0, "min refresh rate", 0, 144);
	10857	+ if (!prop) {
	10858	+ DRM_DEV_ERROR(vop2->dev, "create vrr prop for vp%d failed\n", vp->id);
	10859	+ return -ENOMEM;
	10860	+ }
	10861	+ vp->min_refresh_rate_prop = prop;
	10862	+ drm_object_attach_property(&crtc->base, vp->min_refresh_rate_prop, 0);
7806	10863
7807	10864	return 0;
7808	10865	}
..	..	@@ -7877,12 +10934,13 @@
7877	10934	uint64_t soc_id;
7878	10935	uint32_t registered_num_crtcs = 0;
7879	10936	uint32_t plane_mask = 0;
7880		- char dclk_name[9];
	10937	+ char clk_name[16];
7881	10938	int i = 0, j = 0, k = 0;
7882	10939	int ret = 0;
7883	10940	bool be_used_for_primary_plane = false;
7884	10941	bool find_primary_plane = false;
7885	10942	bool bootloader_initialized = false;
	10943	+ struct rockchip_drm_private *private = drm_dev->dev_private;
7886	10944
7887	10945	/* all planes can attach to any crtc */
7888	10946	possible_crtcs = (1 << vop2_data->nr_vps) - 1;
..	..	@@ -7932,14 +10990,27 @@
7932	10990	else
7933	10991	soc_id = vp_data->soc_id[0];
7934	10992
7935		- snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
7936		- vp->dclk = devm_clk_get(vop2->dev, dclk_name);
	10993	+ snprintf(clk_name, sizeof(clk_name), "dclk_vp%d", vp->id);
	10994	+ vp->dclk_rst = devm_reset_control_get_optional(vop2->dev, clk_name);
	10995	+ if (IS_ERR(vp->dclk_rst)) {
	10996	+ DRM_DEV_ERROR(vop2->dev, "failed to get dclk reset\n");
	10997	+ return PTR_ERR(vp->dclk_rst);
	10998	+ }
	10999	+
	11000	+ vp->dclk = devm_clk_get(vop2->dev, clk_name);
7937	11001	if (IS_ERR(vp->dclk)) {
7938		- DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", dclk_name);
	11002	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
7939	11003	return PTR_ERR(vp->dclk);
7940	11004	}
7941	11005
7942		- crtc = &vp->crtc;
	11006	+ snprintf(clk_name, sizeof(clk_name), "dclk_src_vp%d", vp->id);
	11007	+ vp->dclk_parent = devm_clk_get_optional(vop2->dev, clk_name);
	11008	+ if (IS_ERR(vp->dclk)) {
	11009	+ DRM_DEV_ERROR(vop2->dev, "failed to get %s\n", clk_name);
	11010	+ return PTR_ERR(vp->dclk);
	11011	+ }
	11012	+
	11013	+ crtc = &vp->rockchip_crtc.crtc;
7943	11014
7944	11015	port = of_graph_get_port_by_id(dev->of_node, i);
7945	11016	if (!port) {
..	..	@@ -8057,31 +11128,34 @@
8057	11128	init_completion(&vp->line_flag_completion);
8058	11129	rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
8059	11130	soc_id = vop2_soc_id_fixup(soc_id);
8060		- drm_object_attach_property(&crtc->base, vop2->soc_id_prop, soc_id);
8061		- drm_object_attach_property(&crtc->base, vop2->vp_id_prop, vp->id);
8062		- drm_object_attach_property(&crtc->base, vop2->aclk_prop, 0);
8063		- drm_object_attach_property(&crtc->base, vop2->bg_prop, 0);
8064		- drm_object_attach_property(&crtc->base, vop2->line_flag_prop, 0);
8065		- drm_object_attach_property(&crtc->base,
8066		- drm_dev->mode_config.tv_left_margin_property, 100);
8067		- drm_object_attach_property(&crtc->base,
8068		- drm_dev->mode_config.tv_right_margin_property, 100);
8069		- drm_object_attach_property(&crtc->base,
8070		- drm_dev->mode_config.tv_top_margin_property, 100);
8071		- drm_object_attach_property(&crtc->base,
8072		- drm_dev->mode_config.tv_bottom_margin_property, 100);
	11131	+ drm_object_attach_property(&crtc->base, private->soc_id_prop, soc_id);
	11132	+ drm_object_attach_property(&crtc->base, private->port_id_prop, vp->id);
	11133	+ drm_object_attach_property(&crtc->base, private->aclk_prop, 0);
	11134	+ drm_object_attach_property(&crtc->base, private->bg_prop, 0);
	11135	+ drm_object_attach_property(&crtc->base, private->line_flag_prop, 0);
	11136	+ if (vp_data->feature & VOP_FEATURE_OVERSCAN) {
	11137	+ drm_object_attach_property(&crtc->base,
	11138	+ drm_dev->mode_config.tv_left_margin_property, 100);
	11139	+ drm_object_attach_property(&crtc->base,
	11140	+ drm_dev->mode_config.tv_right_margin_property, 100);
	11141	+ drm_object_attach_property(&crtc->base,
	11142	+ drm_dev->mode_config.tv_top_margin_property, 100);
	11143	+ drm_object_attach_property(&crtc->base,
	11144	+ drm_dev->mode_config.tv_bottom_margin_property, 100);
	11145	+ }
8073	11146	if (plane_mask)
8074	11147	vop2_crtc_create_plane_mask_property(vop2, crtc, plane_mask);
	11148	+ vop2_crtc_create_feature_property(vop2, crtc);
	11149	+ vop2_crtc_create_vrr_property(vop2, crtc);
8075	11150
8076		- if (vp_data->feature & VOP_FEATURE_VIVID_HDR) {
	11151	+ ret = drm_self_refresh_helper_init(crtc);
	11152	+ if (ret)
	11153	+ DRM_DEV_DEBUG_KMS(vop2->dev,
	11154	+ "Failed to init %s with SR helpers %d, ignoring\n",
	11155	+ crtc->name, ret);
	11156	+
	11157	+ if (vp_data->feature & VOP_FEATURE_VIVID_HDR)
8077	11158	vop2_crtc_create_hdr_property(vop2, crtc);
8078		- vp->hdr_lut_gem_obj = rockchip_gem_create_object(vop2->drm_dev,
8079		- RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH * 4, true, 0);
8080		- if (IS_ERR(vp->hdr_lut_gem_obj)) {
8081		- DRM_ERROR("create hdr lut obj failed\n");
8082		- return -ENOMEM;
8083		- }
8084		- }
8085	11159	if (vp_data->feature & VOP_FEATURE_POST_ACM)
8086	11160	vop2_crtc_create_post_acm_property(vop2, crtc);
8087	11161	if (vp_data->feature & VOP_FEATURE_POST_CSC)
..	..	@@ -8141,7 +11215,7 @@
8141	11215
8142	11216	ret = vop2_plane_init(vop2, win, possible_crtcs);
8143	11217	if (ret)
8144		- DRM_WARN("failed to init overlay plane %s, ret:%d\n", win->name, ret);
	11218	+ DRM_WARN("failed to init overlay plane %s\n", win->name);
8145	11219	}
8146	11220
8147	11221	if (is_vop3(vop2))
..	..	@@ -8154,6 +11228,7 @@
8154	11228	{
8155	11229	struct vop2_video_port *vp = to_vop2_video_port(crtc);
8156	11230
	11231	+ drm_self_refresh_helper_cleanup(crtc);
8157	11232	if (vp->hdr_lut_gem_obj)
8158	11233	rockchip_gem_free_object(&vp->hdr_lut_gem_obj->base);
8159	11234
..	..	@@ -8167,6 +11242,59 @@
8167	11242	drm_flip_work_cleanup(&vp->fb_unref_work);
8168	11243	}
8169	11244
	11245	+static int vop2_pd_data_init(struct vop2 *vop2)
	11246	+{
	11247	+ const struct vop2_data *vop2_data = vop2->data;
	11248	+ const struct vop2_power_domain_data *pd_data;
	11249	+ struct vop2_power_domain *pd;
	11250	+ int i;
	11251	+
	11252	+ INIT_LIST_HEAD(&vop2->pd_list_head);
	11253	+
	11254	+ for (i = 0; i < vop2_data->nr_pds; i++) {
	11255	+ pd_data = &vop2_data->pd[i];
	11256	+ pd = devm_kzalloc(vop2->dev, sizeof(*pd), GFP_KERNEL);
	11257	+ if (!pd)
	11258	+ return -ENOMEM;
	11259	+ pd->vop2 = vop2;
	11260	+ pd->data = pd_data;
	11261	+ pd->vp_mask = 0;
	11262	+ spin_lock_init(&pd->lock);
	11263	+ list_add_tail(&pd->list, &vop2->pd_list_head);
	11264	+ INIT_DELAYED_WORK(&pd->power_off_work, vop2_power_domain_off_work);
	11265	+ if (pd_data->parent_id) {
	11266	+ pd->parent = vop2_find_pd_by_id(vop2, pd_data->parent_id);
	11267	+ if (!pd->parent) {
	11268	+ DRM_DEV_ERROR(vop2->dev, "no parent pd find for pd%d\n", pd->data->id);
	11269	+ return -EINVAL;
	11270	+ }
	11271	+ }
	11272	+ }
	11273	+
	11274	+ return 0;
	11275	+}
	11276	+
	11277	+static void vop2_dsc_data_init(struct vop2 *vop2)
	11278	+{
	11279	+ const struct vop2_data *vop2_data = vop2->data;
	11280	+ const struct vop2_dsc_data *dsc_data;
	11281	+ struct vop2_dsc *dsc;
	11282	+ int i;
	11283	+
	11284	+ for (i = 0; i < vop2_data->nr_dscs; i++) {
	11285	+ dsc = &vop2->dscs[i];
	11286	+ dsc_data = &vop2_data->dsc[i];
	11287	+ dsc->id = dsc_data->id;
	11288	+ dsc->max_slice_num = dsc_data->max_slice_num;
	11289	+ dsc->max_linebuf_depth = dsc_data->max_linebuf_depth;
	11290	+ dsc->min_bits_per_pixel = dsc_data->min_bits_per_pixel;
	11291	+ dsc->regs = dsc_data->regs;
	11292	+ dsc->attach_vp_id = -1;
	11293	+ if (dsc_data->pd_id)
	11294	+ dsc->pd = vop2_find_pd_by_id(vop2, dsc_data->pd_id);
	11295	+ }
	11296	+}
	11297	+
8170	11298	static int vop2_win_init(struct vop2 *vop2)
8171	11299	{
8172	11300	const struct vop2_data *vop2_data = vop2->data;
..	..	@@ -8174,7 +11302,6 @@
8174	11302	struct drm_prop_enum_list *plane_name_list;
8175	11303	struct vop2_win *win;
8176	11304	struct vop2_layer *layer;
8177		- struct drm_property *prop;
8178	11305	char name[DRM_PROP_NAME_LEN];
8179	11306	unsigned int num_wins = 0;
8180	11307	uint8_t plane_id = 0;
..	..	@@ -8203,6 +11330,7 @@
8203	11330	win->dly = win_data->dly;
8204	11331	win->feature = win_data->feature;
8205	11332	win->phys_id = win_data->phys_id;
	11333	+ win->splice_win_id = win_data->splice_win_id;
8206	11334	win->layer_sel_id = win_data->layer_sel_id;
8207	11335	win->win_id = i;
8208	11336	win->plane_id = plane_id++;
..	..	@@ -8213,6 +11341,9 @@
8213	11341	win->axi_yrgb_id = win_data->axi_yrgb_id;
8214	11342	win->axi_uv_id = win_data->axi_uv_id;
8215	11343	win->possible_crtcs = win_data->possible_crtcs;
	11344	+
	11345	+ if (win_data->pd_id)
	11346	+ win->pd = vop2_find_pd_by_id(vop2, win_data->pd_id);
8216	11347
8217	11348	num_wins++;
8218	11349
..	..	@@ -8253,6 +11384,7 @@
8253	11384	num_wins++;
8254	11385	}
8255	11386	}
	11387	+
8256	11388	vop2->registered_num_wins = num_wins;
8257	11389
8258	11390	if (!is_vop3(vop2)) {
..	..	@@ -8280,30 +11412,10 @@
8280	11412
8281	11413	vop2->plane_name_list = plane_name_list;
8282	11414
8283		- prop = drm_property_create_object(vop2->drm_dev,
8284		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
8285		- "SOC_ID", DRM_MODE_OBJECT_CRTC);
8286		- vop2->soc_id_prop = prop;
8287		-
8288		- prop = drm_property_create_object(vop2->drm_dev,
8289		- DRM_MODE_PROP_ATOMIC \| DRM_MODE_PROP_IMMUTABLE,
8290		- "PORT_ID", DRM_MODE_OBJECT_CRTC);
8291		- vop2->vp_id_prop = prop;
8292		-
8293		- vop2->aclk_prop = drm_property_create_range(vop2->drm_dev, 0, "ACLK", 0, UINT_MAX);
8294		- vop2->bg_prop = drm_property_create_range(vop2->drm_dev, 0, "BACKGROUND", 0, UINT_MAX);
8295		-
8296		- vop2->line_flag_prop = drm_property_create_range(vop2->drm_dev, 0, "LINE_FLAG1", 0, UINT_MAX);
8297		-
8298		- if (!vop2->soc_id_prop \|\| !vop2->vp_id_prop \|\| !vop2->aclk_prop \|\| !vop2->bg_prop \|\|
8299		- !vop2->line_flag_prop) {
8300		- DRM_DEV_ERROR(vop2->dev, "failed to create soc_id/vp_id/aclk property\n");
8301		- return -ENOMEM;
8302		- }
8303		-
8304	11415	return 0;
8305	11416	}
8306	11417
	11418	+#include "rockchip_vop2_clk.c"
8307	11419	static void post_buf_empty_work_event(struct work_struct *work)
8308	11420	{
8309	11421	struct vop2 *vop2 = container_of(work, struct vop2, post_buf_empty_work);
..	..	@@ -8323,7 +11435,7 @@
8323	11435	mutex_lock(&private->ovl_lock);
8324	11436	vop2_wait_for_fs_by_done_bit_status(vp);
8325	11437	VOP_MODULE_SET(vop2, vp, p2i_en, 0);
8326		- vop2_cfg_done(&vp->crtc);
	11438	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
8327	11439	vop2_wait_for_fs_by_done_bit_status(vp);
8328	11440	mutex_unlock(&private->ovl_lock);
8329	11441
..	..	@@ -8332,11 +11444,102 @@
8332	11444	mutex_lock(&private->ovl_lock);
8333	11445	vop2_wait_for_fs_by_done_bit_status(vp);
8334	11446	VOP_MODULE_SET(vop2, vp, p2i_en, 1);
8335		- vop2_cfg_done(&vp->crtc);
	11447	+ vop2_cfg_done(&vp->rockchip_crtc.crtc);
8336	11448	vop2_wait_for_fs_by_done_bit_status(vp);
8337	11449	mutex_unlock(&private->ovl_lock);
8338	11450
8339	11451	vp->need_reset_p2i_flag = false;
	11452	+ }
	11453	+ }
	11454	+}
	11455	+
	11456	+static bool vop2_plane_mask_check(struct vop2 *vop2)
	11457	+{
	11458	+ const struct vop2_data *vop2_data = vop2->data;
	11459	+ u32 plane_mask = 0;
	11460	+ int i;
	11461	+
	11462	+ /*
	11463	+ * For RK3568 and RK3588, all windows need to be assigned to
	11464	+ * one of all vps, and two of vps can not share the same window.
	11465	+ */
	11466	+ if (vop2->version != VOP_VERSION_RK3568 && vop2->version != VOP_VERSION_RK3588)
	11467	+ return true;
	11468	+
	11469	+ for (i = 0; i < vop2_data->nr_vps; i++) {
	11470	+ if (plane_mask & vop2->vps[i].plane_mask) {
	11471	+ DRM_WARN("the same window can't be assigned to two vp\n");
	11472	+ return false;
	11473	+ }
	11474	+ plane_mask \|= vop2->vps[i].plane_mask;
	11475	+ }
	11476	+
	11477	+ if (hweight32(plane_mask) != vop2_data->nr_layers \|\|
	11478	+ plane_mask != vop2_data->plane_mask_base) {
	11479	+ DRM_WARN("all windows should be assigned, full plane mask: 0x%x, current plane mask: 0x%x\n",
	11480	+ vop2_data->plane_mask_base, plane_mask);
	11481	+ return false;
	11482	+ }
	11483	+
	11484	+ return true;
	11485	+}
	11486	+
	11487	+static uint32_t vop2_vp_plane_mask_to_bitmap(const struct vop2_vp_plane_mask *vp_plane_mask)
	11488	+{
	11489	+ int layer_phy_id = 0;
	11490	+ int plane_mask = 0;
	11491	+ int i;
	11492	+
	11493	+ for (i = 0; i < vp_plane_mask->attached_layers_nr; i++) {
	11494	+ layer_phy_id = vp_plane_mask->attached_layers[i];
	11495	+ plane_mask \|= BIT(layer_phy_id);
	11496	+ }
	11497	+
	11498	+ return plane_mask;
	11499	+}
	11500	+
	11501	+static bool vop2_get_vp_of_status(struct device_node *vp_node)
	11502	+{
	11503	+ struct device_node *vp_sub_node;
	11504	+ struct device_node *remote_node;
	11505	+ bool vp_enable = false;
	11506	+
	11507	+ for_each_child_of_node(vp_node, vp_sub_node) {
	11508	+ remote_node = of_graph_get_remote_endpoint(vp_sub_node);
	11509	+ vp_enable \|= of_device_is_available(remote_node);
	11510	+ }
	11511	+
	11512	+ return vp_enable;
	11513	+}
	11514	+
	11515	+static void vop2_plane_mask_assign(struct vop2 vop2, struct device_node vop_out_node)
	11516	+{
	11517	+ const struct vop2_data *vop2_data = vop2->data;
	11518	+ const struct vop2_vp_plane_mask *plane_mask;
	11519	+ struct device_node *child;
	11520	+ int active_vp_num = 0;
	11521	+ int vp_id;
	11522	+ int i = 0;
	11523	+
	11524	+ for_each_child_of_node(vop_out_node, child) {
	11525	+ if (vop2_get_vp_of_status(child))
	11526	+ active_vp_num++;
	11527	+ }
	11528	+
	11529	+ if (vop2_soc_is_rk3566() && active_vp_num > 2)
	11530	+ DRM_WARN("RK3566 only support 2 vps\n");
	11531	+ plane_mask = vop2_data->plane_mask;
	11532	+ plane_mask += (active_vp_num - 1) * ROCKCHIP_MAX_CRTC;
	11533	+
	11534	+ for_each_child_of_node(vop_out_node, child) {
	11535	+ of_property_read_u32(child, "reg", &vp_id);
	11536	+ if (vop2_get_vp_of_status(child)) {
	11537	+ vop2->vps[vp_id].plane_mask = vop2_vp_plane_mask_to_bitmap(&plane_mask[i]);
	11538	+ vop2->vps[vp_id].primary_plane_phy_id = plane_mask[i].primary_plane_id;
	11539	+ i++;
	11540	+ } else {
	11541	+ vop2->vps[vp_id].plane_mask = 0;
	11542	+ vop2->vps[vp_id].primary_plane_phy_id = ROCKCHIP_VOP2_PHY_ID_INVALID;
8340	11543	}
8341	11544	}
8342	11545	}
..	..	@@ -8353,6 +11556,7 @@
8353	11556	int num_wins = 0;
8354	11557	int registered_num_crtcs;
8355	11558	struct device_node *vop_out_node;
	11559	+ struct device_node *mcu_timing_node;
8356	11560
8357	11561	vop2_data = of_device_get_match_data(dev);
8358	11562	if (!vop2_data)
..	..	@@ -8382,6 +11586,9 @@
8382	11586	vop2->disable_win_move = of_property_read_bool(dev->of_node, "disable-win-move");
8383	11587	vop2->skip_ref_fb = of_property_read_bool(dev->of_node, "skip-ref-fb");
8384	11588
	11589	+ ret = vop2_pd_data_init(vop2);
	11590	+ if (ret)
	11591	+ return ret;
8385	11592	/*
8386	11593	* esmart lb mode default config at vop2_reg.c vop2_data.esmart_lb_mode,
8387	11594	* you can rewrite at dts vop node:
..	..	@@ -8432,7 +11639,10 @@
8432	11639	return PTR_ERR(vop2->acm_regs);
8433	11640	}
8434	11641
8435		- vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11642	+ vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
	11643	+ vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf");
	11644	+ vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf");
	11645	+ vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu");
8436	11646
8437	11647	vop2->hclk = devm_clk_get(vop2->dev, "hclk_vop");
8438	11648	if (IS_ERR(vop2->hclk)) {
..	..	@@ -8443,6 +11653,24 @@
8443	11653	if (IS_ERR(vop2->aclk)) {
8444	11654	DRM_DEV_ERROR(vop2->dev, "failed to get aclk source\n");
8445	11655	return PTR_ERR(vop2->aclk);
	11656	+ }
	11657	+
	11658	+ vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop");
	11659	+ if (IS_ERR(vop2->pclk)) {
	11660	+ DRM_DEV_ERROR(vop2->dev, "failed to get pclk source\n");
	11661	+ return PTR_ERR(vop2->pclk);
	11662	+ }
	11663	+
	11664	+ vop2->ahb_rst = devm_reset_control_get_optional(vop2->dev, "ahb");
	11665	+ if (IS_ERR(vop2->ahb_rst)) {
	11666	+ DRM_DEV_ERROR(vop2->dev, "failed to get ahb reset\n");
	11667	+ return PTR_ERR(vop2->ahb_rst);
	11668	+ }
	11669	+
	11670	+ vop2->axi_rst = devm_reset_control_get_optional(vop2->dev, "axi");
	11671	+ if (IS_ERR(vop2->axi_rst)) {
	11672	+ DRM_DEV_ERROR(vop2->dev, "failed to get axi reset\n");
	11673	+ return PTR_ERR(vop2->axi_rst);
8446	11674	}
8447	11675
8448	11676	vop2->irq = platform_get_irq(pdev, 0);
..	..	@@ -8459,6 +11687,7 @@
8459	11687	u32 plane_mask = 0;
8460	11688	u32 primary_plane_phy_id = 0;
8461	11689	u32 vp_id = 0;
	11690	+ u32 val = 0;
8462	11691
8463	11692	of_property_read_u32(child, "rockchip,plane-mask", &plane_mask);
8464	11693	of_property_read_u32(child, "rockchip,primary-plane", &primary_plane_phy_id);
..	..	@@ -8472,12 +11701,42 @@
8472	11701
8473	11702	vop2->vps[vp_id].xmirror_en = of_property_read_bool(child, "xmirror-enable");
8474	11703
	11704	+ ret = of_clk_set_defaults(child, false);
	11705	+ if (ret) {
	11706	+ DRM_DEV_ERROR(dev, "Failed to set clock defaults %d\n", ret);
	11707	+ return ret;
	11708	+ }
	11709	+
	11710	+ mcu_timing_node = of_get_child_by_name(child, "mcu-timing");
	11711	+ if (mcu_timing_node) {
	11712	+ if (!of_property_read_u32(mcu_timing_node, "mcu-pix-total", &val))
	11713	+ vop2->vps[vp_id].mcu_timing.mcu_pix_total = val;
	11714	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pst", &val))
	11715	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pst = val;
	11716	+ if (!of_property_read_u32(mcu_timing_node, "mcu-cs-pend", &val))
	11717	+ vop2->vps[vp_id].mcu_timing.mcu_cs_pend = val;
	11718	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pst", &val))
	11719	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pst = val;
	11720	+ if (!of_property_read_u32(mcu_timing_node, "mcu-rw-pend", &val))
	11721	+ vop2->vps[vp_id].mcu_timing.mcu_rw_pend = val;
	11722	+ if (!of_property_read_u32(mcu_timing_node, "mcu-hold-mode", &val))
	11723	+ vop2->vps[vp_id].mcu_timing.mcu_hold_mode = val;
	11724	+ }
	11725	+ }
	11726	+
	11727	+ if (!vop2_plane_mask_check(vop2)) {
	11728	+ DRM_WARN("use default plane mask\n");
	11729	+ vop2_plane_mask_assign(vop2, vop_out_node);
	11730	+ }
	11731	+
	11732	+ for (i = 0; i < vop2->data->nr_vps; i++) {
8475	11733	DRM_DEV_INFO(dev, "vp%d assign plane mask: 0x%x, primary plane phy id: %d\n",
8476		- vp_id, vop2->vps[vp_id].plane_mask,
8477		- vop2->vps[vp_id].primary_plane_phy_id);
	11734	+ i, vop2->vps[i].plane_mask,
	11735	+ vop2->vps[i].primary_plane_phy_id);
8478	11736	}
8479	11737	}
8480	11738
	11739	+ vop2_extend_clk_init(vop2);
8481	11740	spin_lock_init(&vop2->reg_lock);
8482	11741	spin_lock_init(&vop2->irq_lock);
8483	11742	mutex_init(&vop2->vop2_lock);
..	..	@@ -8492,12 +11751,16 @@
8492	11751	if (ret)
8493	11752	return ret;
8494	11753
	11754	+ vop2_dsc_data_init(vop2);
	11755	+
8495	11756	registered_num_crtcs = vop2_create_crtc(vop2);
8496	11757	if (registered_num_crtcs <= 0)
8497	11758	return -ENODEV;
	11759	+
8498	11760	ret = vop2_gamma_init(vop2);
8499	11761	if (ret)
8500	11762	return ret;
	11763	+ vop2_clk_init(vop2);
8501	11764	vop2_cubic_lut_init(vop2);
8502	11765	vop2_wb_connector_init(vop2, registered_num_crtcs);
8503	11766	pm_runtime_enable(&pdev->dev);