forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
....@@ -1,87 +1,120 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
34  * Author:Mark Yao <mark.yao@rock-chips.com>
45  *
56  * based on exynos_drm_drv.h
6
- *
7
- * This software is licensed under the terms of the GNU General Public
8
- * License version 2, as published by the Free Software Foundation, and
9
- * may be copied, distributed, and modified under those terms.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
- * GNU General Public License for more details.
157  */
168 
179 #ifndef _ROCKCHIP_DRM_DRV_H
1810 #define _ROCKCHIP_DRM_DRV_H
1911 
20
-#include <drm/drm_crtc.h>
21
-#include <drm/drm_fb_helper.h>
2212 #include <drm/drm_atomic_helper.h>
13
+#include <drm/drm_dsc.h>
14
+#include <drm/drm_fb_helper.h>
15
+#include <drm/drm_fourcc.h>
2316 #include <drm/drm_gem.h>
2417 #include <drm/rockchip_drm.h>
25
-
2618 #include <linux/module.h>
2719 #include <linux/component.h>
28
-#include <linux/dmabuf_page_pool.h>
20
+
21
+#include <soc/rockchip/rockchip_dmc.h>
22
+
23
+#include "../panel/panel-simple.h"
24
+
25
+#include "rockchip_drm_debugfs.h"
2926 
3027 #define ROCKCHIP_MAX_FB_BUFFER	3
3128 #define ROCKCHIP_MAX_CONNECTOR	2
3229 #define ROCKCHIP_MAX_CRTC	4
3330 #define ROCKCHIP_MAX_LAYER	16
3431 
32
+
3533 struct drm_device;
3634 struct drm_connector;
3735 struct iommu_domain;
36
+
37
+#define VOP_COLOR_KEY_NONE	(0 << 31)
38
+#define VOP_COLOR_KEY_MASK	(1 << 31)
39
+
40
+#define VOP_OUTPUT_IF_RGB	BIT(0)
41
+#define VOP_OUTPUT_IF_BT1120	BIT(1)
42
+#define VOP_OUTPUT_IF_BT656	BIT(2)
43
+#define VOP_OUTPUT_IF_LVDS0	BIT(3)
44
+#define VOP_OUTPUT_IF_LVDS1	BIT(4)
45
+#define VOP_OUTPUT_IF_MIPI0	BIT(5)
46
+#define VOP_OUTPUT_IF_MIPI1	BIT(6)
47
+#define VOP_OUTPUT_IF_eDP0	BIT(7)
48
+#define VOP_OUTPUT_IF_eDP1	BIT(8)
49
+#define VOP_OUTPUT_IF_DP0	BIT(9)
50
+#define VOP_OUTPUT_IF_DP1	BIT(10)
51
+#define VOP_OUTPUT_IF_HDMI0	BIT(11)
52
+#define VOP_OUTPUT_IF_HDMI1	BIT(12)
53
+
54
+#ifndef DRM_FORMAT_NV20
55
+#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
56
+#endif
57
+
58
+#ifndef DRM_FORMAT_NV30
59
+#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
60
+#endif
61
+
62
+#define RK_IF_PROP_COLOR_DEPTH		"color_depth"
63
+#define RK_IF_PROP_COLOR_FORMAT		"color_format"
64
+#define RK_IF_PROP_COLOR_DEPTH_CAPS	"color_depth_caps"
65
+#define RK_IF_PROP_COLOR_FORMAT_CAPS	"color_format_caps"
66
+#define RK_IF_PROP_ENCRYPTED		"hdcp_encrypted"
67
+
68
+enum rockchip_drm_debug_category {
69
+	VOP_DEBUG_PLANE		= BIT(0),
70
+	VOP_DEBUG_OVERLAY	= BIT(1),
71
+	VOP_DEBUG_WB		= BIT(2),
72
+	VOP_DEBUG_CFG_DONE	= BIT(3),
73
+	VOP_DEBUG_VSYNC		= BIT(7),
74
+};
75
+
76
+enum rk_if_color_depth {
77
+	RK_IF_DEPTH_8,
78
+	RK_IF_DEPTH_10,
79
+	RK_IF_DEPTH_12,
80
+	RK_IF_DEPTH_16,
81
+	RK_IF_DEPTH_420_10,
82
+	RK_IF_DEPTH_420_12,
83
+	RK_IF_DEPTH_420_16,
84
+	RK_IF_DEPTH_6,
85
+	RK_IF_DEPTH_MAX,
86
+};
87
+
88
+enum rk_if_color_format {
89
+	RK_IF_FORMAT_RGB, /* default RGB */
90
+	RK_IF_FORMAT_YCBCR444, /* YCBCR 444 */
91
+	RK_IF_FORMAT_YCBCR422, /* YCBCR 422 */
92
+	RK_IF_FORMAT_YCBCR420, /* YCBCR 420 */
93
+	RK_IF_FORMAT_YCBCR_HQ, /* Highest subsampled YUV */
94
+	RK_IF_FORMAT_YCBCR_LQ, /* Lowest subsampled YUV */
95
+	RK_IF_FORMAT_MAX,
96
+};
97
+
98
+enum rockchip_hdcp_encrypted {
99
+	RK_IF_HDCP_ENCRYPTED_NONE = 0,
100
+	RK_IF_HDCP_ENCRYPTED_LEVEL1,
101
+	RK_IF_HDCP_ENCRYPTED_LEVEL2,
102
+};
103
+
104
+enum rockchip_color_bar_mode {
105
+	ROCKCHIP_COLOR_BAR_OFF = 0,
106
+	ROCKCHIP_COLOR_BAR_HORIZONTAL = 1,
107
+	ROCKCHIP_COLOR_BAR_VERTICAL = 2,
108
+};
38109 
39110 struct rockchip_drm_sub_dev {
40111 	struct list_head list;
41112 	struct drm_connector *connector;
42113 	struct device_node *of_node;
43
-};
44
-
45
-/*
46
- * Rockchip drm private crtc funcs.
47
- * @loader_protect: protect loader logo crtc's power
48
- * @enable_vblank: enable crtc vblank irq.
49
- * @disable_vblank: disable crtc vblank irq.
50
- * @bandwidth: report present crtc bandwidth consume.
51
- */
52
-struct rockchip_crtc_funcs {
53
-	int (*loader_protect)(struct drm_crtc *crtc, bool on);
54
-	int (*enable_vblank)(struct drm_crtc *crtc);
55
-	void (*disable_vblank)(struct drm_crtc *crtc);
56
-	size_t (*bandwidth)(struct drm_crtc *crtc,
57
-			    struct drm_crtc_state *crtc_state,
58
-			    size_t *frame_bw_mbyte,
59
-			    unsigned int *plane_num_total);
60
-	void (*cancel_pending_vblank)(struct drm_crtc *crtc,
61
-				      struct drm_file *file_priv);
62
-	int (*debugfs_init)(struct drm_minor *minor, struct drm_crtc *crtc);
63
-	int (*debugfs_dump)(struct drm_crtc *crtc, struct seq_file *s);
64
-	void (*regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
65
-	void (*active_regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
66
-	enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc,
67
-					   const struct drm_display_mode *mode,
68
-					   int output_type);
69
-	void (*crtc_close)(struct drm_crtc *crtc);
70
-	void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
71
-	void (*te_handler)(struct drm_crtc *crtc);
72
-};
73
-
74
-struct rockchip_atomic_commit {
75
-	struct drm_atomic_state *state;
76
-	struct drm_device *dev;
77
-	size_t line_bw_mbyte;
78
-	size_t frame_bw_mbyte;
79
-	unsigned int plane_num;
80
-};
81
-
82
-struct rockchip_dclk_pll {
83
-	struct clk *pll;
84
-	unsigned int use_count;
114
+	int (*loader_protect)(struct drm_encoder *encoder, bool on);
115
+	void (*oob_hotplug_event)(struct drm_connector *connector);
116
+	void (*update_vfp_for_vrr)(struct drm_connector *connector, struct drm_display_mode *mode,
117
+				   int vfp);
85118 };
86119 
87120 struct rockchip_sdr2hdr_state {
....@@ -104,9 +137,6 @@
104137 	struct rockchip_sdr2hdr_state sdr2hdr_state;
105138 };
106139 
107
-#define VOP_COLOR_KEY_NONE	(0 << 31)
108
-#define VOP_COLOR_KEY_MASK	(1 << 31)
109
-
110140 struct rockchip_bcsh_state {
111141 	int brightness;
112142 	int contrast;
....@@ -115,56 +145,57 @@
115145 	int cos_hue;
116146 };
117147 
118
-#define ACM_GAIN_LUT_HY_LENGTH		(9*17)
119
-#define ACM_GAIN_LUT_HY_TOTAL_LENGTH	(ACM_GAIN_LUT_HY_LENGTH * 3)
120
-#define ACM_GAIN_LUT_HS_LENGTH		(13*17)
121
-#define ACM_GAIN_LUT_HS_TOTAL_LENGTH	(ACM_GAIN_LUT_HS_LENGTH * 3)
122
-#define ACM_DELTA_LUT_H_LENGTH		65
123
-#define ACM_DELTA_LUT_H_TOTAL_LENGTH	(ACM_DELTA_LUT_H_LENGTH * 3)
124
-
125
-struct post_acm {
126
-	s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
127
-	s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
128
-	s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
129
-	u16 y_gain;
130
-	u16 h_gain;
131
-	u16 s_gain;
132
-	u16 acm_enable;
148
+struct rockchip_crtc {
149
+	struct drm_crtc crtc;
150
+#if defined(CONFIG_ROCKCHIP_DRM_DEBUG)
151
+	/**
152
+	 * @vop_dump_status the status of vop dump control
153
+	 * @vop_dump_list_head the list head of vop dump list
154
+	 * @vop_dump_list_init_flag init once
155
+	 * @vop_dump_times control the dump times
156
+	 * @frme_count the frame of dump buf
157
+	 */
158
+	enum vop_dump_status vop_dump_status;
159
+	struct list_head vop_dump_list_head;
160
+	bool vop_dump_list_init_flag;
161
+	int vop_dump_times;
162
+	int frame_count;
163
+#endif
133164 };
134165 
135
-struct post_csc {
136
-	u16 hue;
137
-	u16 saturation;
138
-	u16 contrast;
139
-	u16 brightness;
140
-	u16 r_gain;
141
-	u16 g_gain;
142
-	u16 b_gain;
143
-	u16 r_offset;
144
-	u16 g_offset;
145
-	u16 b_offset;
146
-	u16 csc_enable;
166
+struct rockchip_dsc_sink_cap {
167
+	/**
168
+	 * @slice_width: the number of pixel columns that comprise the slice width
169
+	 * @slice_height: the number of pixel rows that comprise the slice height
170
+	 * @block_pred: Does block prediction
171
+	 * @native_420: Does sink support DSC with 4:2:0 compression
172
+	 * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc
173
+	 * @version_major: DSC major version
174
+	 * @version_minor: DSC minor version
175
+	 * @target_bits_per_pixel_x16: bits num after compress and multiply 16
176
+	 */
177
+	u16 slice_width;
178
+	u16 slice_height;
179
+	bool block_pred;
180
+	bool native_420;
181
+	u8 bpc_supported;
182
+	u8 version_major;
183
+	u8 version_minor;
184
+	u16 target_bits_per_pixel_x16;
147185 };
148
-
149
-#define VOP_OUTPUT_IF_RGB	BIT(0)
150
-#define VOP_OUTPUT_IF_BT1120	BIT(1)
151
-#define VOP_OUTPUT_IF_BT656	BIT(2)
152
-#define VOP_OUTPUT_IF_LVDS0	BIT(3)
153
-#define VOP_OUTPUT_IF_LVDS1	BIT(4)
154
-#define VOP_OUTPUT_IF_MIPI0	BIT(5)
155
-#define VOP_OUTPUT_IF_MIPI1	BIT(6)
156
-#define VOP_OUTPUT_IF_eDP0	BIT(7)
157
-#define VOP_OUTPUT_IF_eDP1	BIT(8)
158
-#define VOP_OUTPUT_IF_DP0	BIT(9)
159
-#define VOP_OUTPUT_IF_DP1	BIT(10)
160
-#define VOP_OUTPUT_IF_HDMI0	BIT(11)
161
-#define VOP_OUTPUT_IF_HDMI1	BIT(12)
162
-#define VOP_OUTPUT_IF_TV	BIT(13)
163186 
164187 struct rockchip_crtc_state {
165188 	struct drm_crtc_state base;
166
-
167189 	int vp_id;
190
+	int output_type;
191
+	int output_mode;
192
+	int output_bpc;
193
+	int output_flags;
194
+	bool enable_afbc;
195
+	/**
196
+	 * @splice_mode: enabled when display a hdisplay > 4096 on rk3588
197
+	 */
198
+	bool splice_mode;
168199 
169200 	/**
170201 	 * @hold_mode: enabled when it's:
....@@ -195,10 +226,6 @@
195226 	int afbdc_win_xoffset;
196227 	int afbdc_win_yoffset;
197228 	int dsp_layer_sel;
198
-	int output_type;
199
-	int output_mode;
200
-	int output_bpc;
201
-	int output_flags;
202229 	u32 output_if;
203230 	u32 bus_format;
204231 	u32 bus_flags;
....@@ -212,11 +239,28 @@
212239 	u32 background;
213240 	u32 line_flag;
214241 	u8 mode_update;
242
+	u8 dsc_id;
243
+	u8 dsc_enable;
244
+
245
+	u8 dsc_slice_num;
246
+	u8 dsc_pixel_num;
247
+
248
+	u64 dsc_txp_clk_rate;
249
+	u64 dsc_pxl_clk_rate;
250
+	u64 dsc_cds_clk_rate;
251
+
252
+	struct drm_dsc_picture_parameter_set pps;
253
+	struct rockchip_dsc_sink_cap dsc_sink_cap;
215254 	struct rockchip_hdr_state hdr;
216255 	struct drm_property_blob *hdr_ext_data;
217256 	struct drm_property_blob *acm_lut_data;
218257 	struct drm_property_blob *post_csc_data;
258
+
259
+	int request_refresh_rate;
260
+	int max_refresh_rate;
261
+	int min_refresh_rate;
219262 };
263
+
220264 #define to_rockchip_crtc_state(s) \
221265 		container_of(s, struct rockchip_crtc_state, base)
222266 
....@@ -228,15 +272,159 @@
228272 
229273 struct rockchip_logo {
230274 	dma_addr_t dma_addr;
275
+	struct drm_mm_node logo_reserved_node;
231276 	void *kvaddr;
232277 	phys_addr_t start;
233278 	phys_addr_t size;
234279 	int count;
235280 };
236281 
282
+struct rockchip_mcu_timing {
283
+	int mcu_pix_total;
284
+	int mcu_cs_pst;
285
+	int mcu_cs_pend;
286
+	int mcu_rw_pst;
287
+	int mcu_rw_pend;
288
+	int mcu_hold_mode;
289
+};
290
+
237291 struct loader_cubic_lut {
238292 	bool enable;
239293 	u32 offset;
294
+};
295
+
296
+struct rockchip_drm_dsc_cap {
297
+	bool v_1p2;
298
+	bool native_420;
299
+	bool all_bpp;
300
+	u8 bpc_supported;
301
+	u8 max_slices;
302
+	u8 max_lanes;
303
+	u8 max_frl_rate_per_lane;
304
+	u8 total_chunk_kbytes;
305
+	int clk_per_slice;
306
+};
307
+
308
+struct ver_26_v0 {
309
+	u8 yuv422_12bit;
310
+	u8 support_2160p_60;
311
+	u8 global_dimming;
312
+	u8 dm_major_ver;
313
+	u8 dm_minor_ver;
314
+	u16 t_min_pq;
315
+	u16 t_max_pq;
316
+	u16 rx;
317
+	u16 ry;
318
+	u16 gx;
319
+	u16 gy;
320
+	u16 bx;
321
+	u16 by;
322
+	u16 wx;
323
+	u16 wy;
324
+} __packed;
325
+
326
+struct ver_15_v1 {
327
+	u8 yuv422_12bit;
328
+	u8 support_2160p_60;
329
+	u8 global_dimming;
330
+	u8 dm_version;
331
+	u8 colorimetry;
332
+	u8 t_max_lum;
333
+	u8 t_min_lum;
334
+	u8 rx;
335
+	u8 ry;
336
+	u8 gx;
337
+	u8 gy;
338
+	u8 bx;
339
+	u8 by;
340
+} __packed;
341
+
342
+struct ver_12_v1 {
343
+	u8 yuv422_12bit;
344
+	u8 support_2160p_60;
345
+	u8 global_dimming;
346
+	u8 dm_version;
347
+	u8 colorimetry;
348
+	u8 low_latency;
349
+	u8 t_max_lum;
350
+	u8 t_min_lum;
351
+	u8 unique_rx;
352
+	u8 unique_ry;
353
+	u8 unique_gx;
354
+	u8 unique_gy;
355
+	u8 unique_bx;
356
+	u8 unique_by;
357
+} __packed;
358
+
359
+struct ver_12_v2 {
360
+	u8 yuv422_12bit;
361
+	u8 backlt_ctrl;
362
+	u8 global_dimming;
363
+	u8 dm_version;
364
+	u8 backlt_min_luma;
365
+	u8 interface;
366
+	u8 yuv444_10b_12b;
367
+	u8 t_min_pq_v2;
368
+	u8 t_max_pq_v2;
369
+	u8 unique_rx;
370
+	u8 unique_ry;
371
+	u8 unique_gx;
372
+	u8 unique_gy;
373
+	u8 unique_bx;
374
+	u8 unique_by;
375
+} __packed;
376
+
377
+struct next_hdr_sink_data {
378
+	u8 version;
379
+	struct ver_26_v0 ver_26_v0;
380
+	struct ver_15_v1 ver_15_v1;
381
+	struct ver_12_v1 ver_12_v1;
382
+	struct ver_12_v2 ver_12_v2;
383
+} __packed;
384
+
385
+/*
386
+ * Rockchip drm private crtc funcs.
387
+ * @loader_protect: protect loader logo crtc's power
388
+ * @enable_vblank: enable crtc vblank irq.
389
+ * @disable_vblank: disable crtc vblank irq.
390
+ * @bandwidth: report present crtc bandwidth consume.
391
+ * @cancel_pending_vblank: cancel pending vblank.
392
+ * @debugfs_init: init crtc debugfs.
393
+ * @debugfs_dump: debugfs to dump crtc and plane state.
394
+ * @regs_dump: dump vop current register config.
395
+ * @mode_valid: verify that the current mode is supported.
396
+ * @crtc_close: close vop.
397
+ * @crtc_send_mcu_cmd: send mcu panel init cmd.
398
+ * @te_handler: soft te hand for cmd mode panel.
399
+ * @wait_vact_end: wait the last active line.
400
+ */
401
+struct rockchip_crtc_funcs {
402
+	int (*loader_protect)(struct drm_crtc *crtc, bool on);
403
+	int (*enable_vblank)(struct drm_crtc *crtc);
404
+	void (*disable_vblank)(struct drm_crtc *crtc);
405
+	size_t (*bandwidth)(struct drm_crtc *crtc,
406
+			    struct drm_crtc_state *crtc_state,
407
+			    struct dmcfreq_vop_info *vop_bw_info);
408
+	void (*cancel_pending_vblank)(struct drm_crtc *crtc,
409
+				      struct drm_file *file_priv);
410
+	int (*debugfs_init)(struct drm_minor *minor, struct drm_crtc *crtc);
411
+	int (*debugfs_dump)(struct drm_crtc *crtc, struct seq_file *s);
412
+	void (*regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
413
+	void (*active_regs_dump)(struct drm_crtc *crtc, struct seq_file *s);
414
+	enum drm_mode_status (*mode_valid)(struct drm_crtc *crtc,
415
+					   const struct drm_display_mode *mode,
416
+					   int output_type);
417
+	void (*crtc_close)(struct drm_crtc *crtc);
418
+	void (*crtc_send_mcu_cmd)(struct drm_crtc *crtc, u32 type, u32 value);
419
+	void (*te_handler)(struct drm_crtc *crtc);
420
+	int (*wait_vact_end)(struct drm_crtc *crtc, unsigned int mstimeout);
421
+	void (*crtc_standby)(struct drm_crtc *crtc, bool standby);
422
+	int (*crtc_set_color_bar)(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode);
423
+};
424
+
425
+struct rockchip_dclk_pll {
426
+	struct clk *pll;
427
+	unsigned int use_count;
240428 };
241429 
242430 /*
....@@ -248,42 +436,44 @@
248436  */
249437 struct rockchip_drm_private {
250438 	struct rockchip_logo *logo;
251
-	struct dmabuf_page_pool *page_pools;
252
-	struct drm_property *eotf_prop;
253
-	struct drm_property *color_space_prop;
254
-	struct drm_property *global_alpha_prop;
255
-	struct drm_property *blend_mode_prop;
256
-	struct drm_property *alpha_scale_prop;
257
-	struct drm_property *async_commit_prop;
258
-	struct drm_property *share_id_prop;
259
-	struct drm_property *connector_id_prop;
260439 	struct drm_fb_helper *fbdev_helper;
261440 	struct drm_gem_object *fbdev_bo;
262
-	const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
263
-	struct drm_atomic_state *state;
264
-
265
-	struct rockchip_atomic_commit *commit;
266
-	/* protect async commit */
441
+	struct iommu_domain *domain;
442
+	struct gen_pool *secure_buffer_pool;
443
+	struct mutex mm_lock;
444
+	struct drm_mm mm;
445
+	struct list_head psr_list;
446
+	struct mutex psr_list_lock;
267447 	struct mutex commit_lock;
448
+
449
+	/* private crtc prop */
450
+	struct drm_property *soc_id_prop;
451
+	struct drm_property *port_id_prop;
452
+	struct drm_property *aclk_prop;
453
+	struct drm_property *bg_prop;
454
+	struct drm_property *line_flag_prop;
455
+
456
+	/* private plane prop */
457
+	struct drm_property *eotf_prop;
458
+	struct drm_property *color_space_prop;
459
+	struct drm_property *async_commit_prop;
460
+	struct drm_property *share_id_prop;
461
+
462
+	/* private connector prop */
463
+	struct drm_property *connector_id_prop;
464
+
465
+	const struct rockchip_crtc_funcs *crtc_funcs[ROCKCHIP_MAX_CRTC];
466
+
467
+	struct rockchip_dclk_pll default_pll;
468
+	struct rockchip_dclk_pll hdmi_pll;
469
+
268470 	/*
269471 	 * protect some shared overlay resource
270472 	 * OVL_LAYER_SEL/OVL_PORT_SEL
271473 	 */
272474 	struct mutex ovl_lock;
273
-	struct work_struct commit_work;
274
-	struct iommu_domain *domain;
275
-	struct gen_pool *secure_buffer_pool;
276
-	/* protect drm_mm on multi-threads */
277
-	struct mutex mm_lock;
278
-	struct drm_mm mm;
279
-	struct rockchip_dclk_pll default_pll;
280
-	struct rockchip_dclk_pll hdmi_pll;
281
-	struct devfreq *devfreq;
282
-	u8 dmc_support;
283
-	struct list_head psr_list;
284
-	struct mutex psr_list_lock;
285
-	struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC];
286475 
476
+	struct rockchip_drm_vcnt vcnt[ROCKCHIP_MAX_CRTC];
287477 	/**
288478 	 * @loader_protect
289479 	 * ignore restore_fbdev_mode_atomic when in logo on state
....@@ -292,58 +482,75 @@
292482 
293483 	dma_addr_t cubic_lut_dma_addr;
294484 	void *cubic_lut_kvaddr;
485
+	struct drm_mm_node *clut_reserved_node;
295486 	struct loader_cubic_lut cubic_lut[ROCKCHIP_MAX_CRTC];
296487 };
297488 
298
-#ifndef MODULE
299
-void rockchip_free_loader_memory(struct drm_device *drm);
300
-#endif
301
-void rockchip_drm_atomic_work(struct work_struct *work);
489
+void rockchip_connector_update_vfp_for_vrr(struct drm_crtc *crtc, struct drm_display_mode *mode,
490
+					   int vfp);
302491 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
303492 				   struct device *dev);
304493 void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
305494 				    struct device *dev);
495
+int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
306496 int rockchip_register_crtc_funcs(struct drm_crtc *crtc,
307497 				 const struct rockchip_crtc_funcs *crtc_funcs);
308498 void rockchip_unregister_crtc_funcs(struct drm_crtc *crtc);
309
-int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout);
499
+void rockchip_drm_crtc_standby(struct drm_crtc *crtc, bool standby);
310500 
311501 void rockchip_drm_register_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
312502 void rockchip_drm_unregister_sub_dev(struct rockchip_drm_sub_dev *sub_dev);
313503 struct rockchip_drm_sub_dev *rockchip_drm_get_sub_dev(struct device_node *node);
314504 int rockchip_drm_add_modes_noedid(struct drm_connector *connector);
315505 void rockchip_drm_te_handle(struct drm_crtc *crtc);
316
-#if IS_ENABLED(CONFIG_DRM_ROCKCHIP)
506
+void drm_mode_convert_to_split_mode(struct drm_display_mode *mode);
507
+void drm_mode_convert_to_origin_mode(struct drm_display_mode *mode);
508
+u32 rockchip_drm_get_dclk_by_width(int width);
509
+#if IS_REACHABLE(CONFIG_DRM_ROCKCHIP)
317510 int rockchip_drm_get_sub_dev_type(void);
511
+u32 rockchip_drm_get_scan_line_time_ns(void);
318512 #else
319513 static inline int rockchip_drm_get_sub_dev_type(void)
320514 {
321515 	return DRM_MODE_CONNECTOR_Unknown;
322516 }
323
-#endif
324517 
325
-#if IS_ENABLED(CONFIG_DRM_ROCKCHIP)
326
-int rockchip_drm_crtc_send_mcu_cmd(struct drm_device *drm_dev,
327
-				   struct device_node *np_crtc,
328
-				   u32 type, u32 value);
329
-#else
330
-static inline int rockchip_drm_crtc_send_mcu_cmd(struct drm_device *drm_dev,
331
-						 struct device_node *np_crtc,
332
-						 u32 type, u32 value)
518
+static inline u32 rockchip_drm_get_scan_line_time_ns(void)
333519 {
334520 	return 0;
335521 }
336522 #endif
337523 
524
+int rockchip_drm_endpoint_is_subdriver(struct device_node *ep);
525
+uint32_t rockchip_drm_of_find_possible_crtcs(struct drm_device *dev,
526
+					     struct device_node *port);
527
+uint32_t rockchip_drm_get_bpp(const struct drm_format_info *info);
528
+int rockchip_drm_get_yuv422_format(struct drm_connector *connector,
529
+				   struct edid *edid);
530
+int rockchip_drm_parse_cea_ext(struct rockchip_drm_dsc_cap *dsc_cap,
531
+			       u8 *max_frl_rate_per_lane, u8 *max_lanes, u8 *add_func,
532
+			       const struct edid *edid);
533
+int rockchip_drm_parse_next_hdr(struct next_hdr_sink_data *sink_data,
534
+				const struct edid *edid);
535
+int rockchip_drm_parse_colorimetry_data_block(u8 *colorimetry, const struct edid *edid);
536
+
537
+__printf(3, 4)
538
+void rockchip_drm_dbg(const struct device *dev, enum rockchip_drm_debug_category category,
539
+		      const char *format, ...);
540
+
338541 extern struct platform_driver cdn_dp_driver;
339542 extern struct platform_driver dw_hdmi_rockchip_pltfm_driver;
340
-extern struct platform_driver dw_mipi_dsi_driver;
543
+extern struct platform_driver dw_mipi_dsi_rockchip_driver;
544
+extern struct platform_driver dw_mipi_dsi2_rockchip_driver;
341545 extern struct platform_driver inno_hdmi_driver;
342546 extern struct platform_driver rockchip_dp_driver;
343547 extern struct platform_driver rockchip_lvds_driver;
344
-extern struct platform_driver rockchip_tve_driver;
345548 extern struct platform_driver vop_platform_driver;
346549 extern struct platform_driver vop2_platform_driver;
347
-extern struct platform_driver vvop_platform_driver;
550
+extern struct platform_driver rk3066_hdmi_driver;
348551 extern struct platform_driver rockchip_rgb_driver;
552
+extern struct platform_driver rockchip_tve_driver;
553
+extern struct platform_driver dw_dp_driver;
554
+extern struct platform_driver vconn_platform_driver;
555
+extern struct platform_driver vvop_platform_driver;
349556 #endif /* _ROCKCHIP_DRM_DRV_H_ */