forked from ~ljy/RK356X_SDK_RELEASE

hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87
kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.c
....@@ -1,15 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
34 * Author: Chris Zhong <zyw@rock-chips.com>
4
- *
5
- * This software is licensed under the terms of the GNU General Public
6
- * License version 2, as published by the Free Software Foundation, and
7
- * may be copied, distributed, and modified under those terms.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
- * GNU General Public License for more details.
135 */
146
157 #include <linux/clk.h>
....@@ -189,7 +181,7 @@
189181 return 0;
190182 }
191183
192
-int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
184
+static int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val)
193185 {
194186 u8 msg[6];
195187
....@@ -221,12 +213,7 @@
221213 sizeof(field), field);
222214 }
223215
224
-/*
225
- * Returns the number of bytes transferred on success, or a negative
226
- * error code on failure. -ETIMEDOUT is returned if mailbox message was
227
- * not send successfully;
228
- */
229
-ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len)
216
+int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len)
230217 {
231218 u8 msg[5], reg[5];
232219 int ret;
....@@ -252,41 +239,24 @@
252239 goto err_dpcd_read;
253240
254241 ret = cdn_dp_mailbox_read_receive(dp, data, len);
255
- if (!ret)
256
- return len;
257242
258243 err_dpcd_read:
259
- DRM_DEV_ERROR(dp->dev, "dpcd read failed: %d\n", ret);
260244 return ret;
261245 }
262246
263
-#define CDN_AUX_HEADER_SIZE 5
264
-#define CDN_AUX_MSG_SIZE 20
265
-/*
266
- * Returns the number of bytes transferred on success, or a negative error
267
- * code on failure. -ETIMEDOUT is returned if mailbox message was not send
268
- * success; -EINVAL is returned if get the wrong data size after message
269
- * is sent
270
- */
271
-ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len)
247
+int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value)
272248 {
273
- u8 msg[CDN_AUX_MSG_SIZE + CDN_AUX_HEADER_SIZE];
274
- u8 reg[CDN_AUX_HEADER_SIZE];
249
+ u8 msg[6], reg[5];
275250 int ret;
276251
277
- if (WARN_ON(len > CDN_AUX_MSG_SIZE) || WARN_ON(len <= 0))
278
- return -EINVAL;
279
-
280
- msg[0] = (len >> 8) & 0xff;
281
- msg[1] = len & 0xff;
252
+ msg[0] = 0;
253
+ msg[1] = 1;
282254 msg[2] = (addr >> 16) & 0xff;
283255 msg[3] = (addr >> 8) & 0xff;
284256 msg[4] = addr & 0xff;
285
-
286
- memcpy(msg + CDN_AUX_HEADER_SIZE, data, len);
287
-
257
+ msg[5] = value;
288258 ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX, DPTX_WRITE_DPCD,
289
- CDN_AUX_HEADER_SIZE + len, msg);
259
+ sizeof(msg), msg);
290260 if (ret)
291261 goto err_dpcd_write;
292262
....@@ -299,43 +269,12 @@
299269 if (ret)
300270 goto err_dpcd_write;
301271
302
- if ((len != (reg[0] << 8 | reg[1])) ||
303
- (addr != (reg[2] << 16 | reg[3] << 8 | reg[4]))) {
272
+ if (addr != (reg[2] << 16 | reg[3] << 8 | reg[4]))
304273 ret = -EINVAL;
305
- } else {
306
- return len;
307
- }
308274
309275 err_dpcd_write:
310276 if (ret)
311277 DRM_DEV_ERROR(dp->dev, "dpcd write failed: %d\n", ret);
312
- return ret;
313
-}
314
-
315
-int cdn_dp_get_aux_status(struct cdn_dp_device *dp)
316
-{
317
- u8 status;
318
- int ret;
319
-
320
- ret = cdn_dp_mailbox_send(dp, MB_MODULE_ID_DP_TX,
321
- DPTX_GET_LAST_AUX_STAUS, 0, NULL);
322
- if (ret)
323
- goto err_get_hpd;
324
-
325
- ret = cdn_dp_mailbox_validate_receive(dp, MB_MODULE_ID_DP_TX,
326
- DPTX_GET_LAST_AUX_STAUS,
327
- sizeof(status));
328
- if (ret)
329
- goto err_get_hpd;
330
-
331
- ret = cdn_dp_mailbox_read_receive(dp, &status, sizeof(status));
332
- if (ret)
333
- goto err_get_hpd;
334
-
335
- return status;
336
-
337
-err_get_hpd:
338
- DRM_DEV_ERROR(dp->dev, "get aux status failed: %d\n", ret);
339278 return ret;
340279 }
341280
....@@ -596,8 +535,8 @@
596535 if (ret)
597536 goto err_get_training_status;
598537
599
- dp->link.rate = status[0];
600
- dp->link.num_lanes = status[1];
538
+ dp->max_rate = drm_dp_bw_code_to_link_rate(status[0]);
539
+ dp->max_lanes = status[1];
601540
602541 err_get_training_status:
603542 if (ret)
....@@ -609,31 +548,6 @@
609548 {
610549 int ret;
611550
612
- /*
613
- * DP firmware uses fixed phy config values to do training, but some
614
- * boards need to adjust these values to fit for their unique hardware
615
- * design. So if the phy is using custom config values, do software
616
- * link training instead of relying on firmware, if software training
617
- * fail, keep firmware training as a fallback if sw training fails.
618
- */
619
- ret = cdn_dp_software_train_link(dp);
620
- if (ret) {
621
- DRM_DEV_ERROR(dp->dev,
622
- "Failed to do software training %d\n", ret);
623
- goto do_fw_training;
624
- }
625
- ret = cdn_dp_reg_write(dp, SOURCE_HDTX_CAR, 0xf);
626
- if (ret) {
627
- DRM_DEV_ERROR(dp->dev,
628
- "Failed to write SOURCE_HDTX_CAR register %d\n", ret);
629
- goto do_fw_training;
630
- }
631
- dp->use_fw_training = false;
632
- return 0;
633
-
634
-do_fw_training:
635
- dp->use_fw_training = true;
636
- DRM_DEV_DEBUG_KMS(dp->dev, "use fw training\n");
637551 ret = cdn_dp_training_start(dp);
638552 if (ret) {
639553 DRM_DEV_ERROR(dp->dev, "Failed to start training %d\n", ret);
....@@ -646,9 +560,9 @@
646560 return ret;
647561 }
648562
649
- DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->link.rate,
650
- dp->link.num_lanes);
651
- return 0;
563
+ DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->max_rate,
564
+ dp->max_lanes);
565
+ return ret;
652566 }
653567
654568 int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active)
....@@ -687,7 +601,7 @@
687601 case YCBCR_4_2_0:
688602 val[0] = 5;
689603 break;
690
- };
604
+ }
691605
692606 switch (video->color_depth) {
693607 case 6:
....@@ -705,7 +619,7 @@
705619 case 16:
706620 val[1] = 4;
707621 break;
708
- };
622
+ }
709623
710624 msa_misc = 2 * val[0] + 32 * val[1] +
711625 ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0);
....@@ -725,7 +639,7 @@
725639 bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ?
726640 (video->color_depth * 2) : (video->color_depth * 3);
727641
728
- link_rate = drm_dp_bw_code_to_link_rate(dp->link.rate) / 1000;
642
+ link_rate = dp->max_rate / 1000;
729643
730644 ret = cdn_dp_reg_write(dp, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE);
731645 if (ret)
....@@ -744,15 +658,14 @@
744658 */
745659 do {
746660 tu_size_reg += 2;
747
- symbol = tu_size_reg * mode->clock * bit_per_pix;
748
- do_div(symbol, dp->link.num_lanes * link_rate * 8);
661
+ symbol = (u64)tu_size_reg * mode->clock * bit_per_pix;
662
+ do_div(symbol, dp->max_lanes * link_rate * 8);
749663 rem = do_div(symbol, 1000);
750664 if (tu_size_reg > 64) {
751665 ret = -EINVAL;
752666 DRM_DEV_ERROR(dp->dev,
753667 "tu error, clk:%d, lanes:%d, rate:%d\n",
754
- mode->clock, dp->link.num_lanes,
755
- link_rate);
668
+ mode->clock, dp->max_lanes, link_rate);
756669 goto err_config_video;
757670 }
758671 } while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
....@@ -766,7 +679,7 @@
766679
767680 /* set the FIFO Buffer size */
768681 val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
769
- val /= (dp->link.num_lanes * link_rate);
682
+ val /= (dp->max_lanes * link_rate);
770683 val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
771684 val += 2;
772685 ret = cdn_dp_reg_write(dp, DP_VC_TABLE(15), val);
....@@ -787,7 +700,7 @@
787700 case 16:
788701 val = BCS_16;
789702 break;
790
- };
703
+ }
791704
792705 val += video->color_fmt << 8;
793706 ret = cdn_dp_reg_write(dp, DP_FRAMER_PXL_REPR, val);
....@@ -919,7 +832,7 @@
919832 u32 val;
920833
921834 if (audio->channels == 2) {
922
- if (dp->link.num_lanes == 1)
835
+ if (dp->max_lanes == 1)
923836 sub_pckt_num = 2;
924837 else
925838 sub_pckt_num = 4;
....@@ -998,23 +911,13 @@
998911 writel(I2S_DEC_START, dp->regs + AUDIO_SRC_CNTL);
999912 }
1000913
1001
-static void cdn_dp_audio_config_spdif(struct cdn_dp_device *dp,
1002
- struct audio_info *audio)
914
+static void cdn_dp_audio_config_spdif(struct cdn_dp_device *dp)
1003915 {
1004916 u32 val;
1005
- int sub_pckt_num = 1;
1006917
1007
- if (audio->channels == 2) {
1008
- if (dp->link.num_lanes == 1)
1009
- sub_pckt_num = 2;
1010
- else
1011
- sub_pckt_num = 4;
1012
- }
1013918 writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL);
1014919
1015
- val = MAX_NUM_CH(audio->channels);
1016
- val |= AUDIO_TYPE_LPCM;
1017
- val |= CFG_SUB_PCKT_NUM(sub_pckt_num);
920
+ val = MAX_NUM_CH(2) | AUDIO_TYPE_LPCM | CFG_SUB_PCKT_NUM(4);
1018921 writel(val, dp->regs + SMPL2PKT_CNFG);
1019922 writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL);
1020923
....@@ -1023,24 +926,6 @@
1023926
1024927 clk_prepare_enable(dp->spdif_clk);
1025928 clk_set_rate(dp->spdif_clk, CDN_DP_SPDIF_CLK);
1026
-}
1027
-
1028
-void cdn_dp_infoframe_set(struct cdn_dp_device *dp, int entry_id,
1029
- u8 *buf, u32 len, int type)
1030
-{
1031
- unsigned int idx;
1032
- u32 *packet = (u32 *)buf;
1033
- u32 length = len / 4;
1034
-
1035
- for (idx = 0; idx < length; idx++)
1036
- writel(cpu_to_le32(*packet++), dp->regs + SOURCE_PIF_DATA_WR);
1037
-
1038
- writel(entry_id, dp->regs + SOURCE_PIF_WR_ADDR);
1039
- writel(HOST_WR, dp->regs + SOURCE_PIF_WR_REQ);
1040
- writel(ACTIVE_IDLE_TYPE(1) | TYPE_VALID |
1041
- PACKET_TYPE(type) | PKT_ALLOC_ADDRESS(entry_id),
1042
- dp->regs + SOURCE_PIF_PKT_ALLOC_REG);
1043
- writel(PKT_ALLOC_WR_EN, dp->regs + SOURCE_PIF_PKT_ALLOC_WR_EN);
1044929 }
1045930
1046931 int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio)
....@@ -1064,7 +949,7 @@
1064949 if (audio->format == AFMT_I2S)
1065950 cdn_dp_audio_config_i2s(dp, audio);
1066951 else if (audio->format == AFMT_SPDIF)
1067
- cdn_dp_audio_config_spdif(dp, audio);
952
+ cdn_dp_audio_config_spdif(dp);
1068953
1069954 ret = cdn_dp_reg_write(dp, AUDIO_PACK_CONTROL, AUDIO_PACK_EN);
1070955