enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c
..
..
@@ -1,19 +1,10 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2013 Red Hat
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  * Author: Rob Clark <robdclark@gmail.com>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published by
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- * the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License along with
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- * this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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+
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+#include <linux/delay.h>
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8
 
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 #include "hdmi.h"
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10
 
..
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@@ -40,7 +31,7 @@
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 	for (i = 0; i < config->pwr_reg_cnt; i++) {
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 		ret = regulator_enable(hdmi->pwr_regs[i]);
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 		if (ret) {
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-			dev_err(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
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+			DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %s (%d)\n",
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 					config->pwr_reg_names[i], ret);
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 		}
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 	}
..
..
@@ -49,7 +40,7 @@
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 		DBG("pixclock: %lu", hdmi->pixclock);
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 		ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
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 		if (ret) {
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-			dev_err(dev->dev, "failed to set pixel clk: %s (%d)\n",
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+			DRM_DEV_ERROR(dev->dev, "failed to set pixel clk: %s (%d)\n",
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 					config->pwr_clk_names[0], ret);
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 		}
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 	}
..
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@@ -57,7 +48,7 @@
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 	for (i = 0; i < config->pwr_clk_cnt; i++) {
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 		ret = clk_prepare_enable(hdmi->pwr_clks[i]);
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 		if (ret) {
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-			dev_err(dev->dev, "failed to enable pwr clk: %s (%d)\n",
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+			DRM_DEV_ERROR(dev->dev, "failed to enable pwr clk: %s (%d)\n",
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 					config->pwr_clk_names[i], ret);
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 		}
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 	}
..
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@@ -82,7 +73,7 @@
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 	for (i = 0; i < config->pwr_reg_cnt; i++) {
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 		ret = regulator_disable(hdmi->pwr_regs[i]);
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 		if (ret) {
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-			dev_err(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
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+			DRM_DEV_ERROR(dev->dev, "failed to disable pwr regulator: %s (%d)\n",
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 					config->pwr_reg_names[i], ret);
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 		}
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 	}
..
..
@@ -101,11 +92,12 @@
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 	u32 val;
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 	int len;
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-	drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false);
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+	drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
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+						 hdmi->connector, mode);
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 	len = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
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 	if (len < 0) {
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-		dev_err(&hdmi->pdev->dev,
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+		DRM_DEV_ERROR(&hdmi->pdev->dev,
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 			"failed to configure avi infoframe\n");
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 		return;
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 	}
..
..
@@ -207,8 +199,8 @@
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 }
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 static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
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-		 struct drm_display_mode *mode,
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-		 struct drm_display_mode *adjusted_mode)
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+		 const struct drm_display_mode *mode,
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+		 const struct drm_display_mode *adjusted_mode)
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 {
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 	struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
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 	struct hdmi *hdmi = hdmi_bridge->hdmi;
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@@ -295,7 +287,7 @@
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 	bridge = &hdmi_bridge->base;
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 	bridge->funcs = &msm_hdmi_bridge_funcs;
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-	ret = drm_bridge_attach(hdmi->encoder, bridge, NULL);
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+	ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, 0);
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 	if (ret)
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 		goto fail;
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