enable docker ppp

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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
..
..
@@ -1,17 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * Copyright (c) 2015 MediaTek Inc.
3
4
  * Authors:
4
5
  *	YT Shen <yt.shen@mediatek.com>
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6
  *	CK Hu <ck.hu@mediatek.com>
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- *
7
- * This program is free software; you can redistribute it and/or modify
8
- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
10
- *
11
- * This program is distributed in the hope that it will be useful,
12
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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7
  */
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8
 
17
9
 #include <linux/clk.h>
..
..
@@ -20,7 +12,9 @@
20
12
 #include <linux/of_irq.h>
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13
 #include <linux/of_platform.h>
22
14
 #include <linux/platform_device.h>
23
-#include <drm/drmP.h>
15
+#include <linux/soc/mediatek/mtk-cmdq.h>
16
+#include <drm/drm_print.h>
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+
24
18
 #include "mtk_drm_drv.h"
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19
 #include "mtk_drm_plane.h"
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20
 #include "mtk_drm_ddp_comp.h"
..
..
@@ -40,6 +34,27 @@
40
34
 
41
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 #define DISP_AAL_EN				0x0000
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36
 #define DISP_AAL_SIZE				0x0030
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+#define DISP_AAL_OUTPUT_SIZE			0x04d8
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+
39
+#define DISP_CCORR_EN				0x0000
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+#define CCORR_EN				BIT(0)
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+#define DISP_CCORR_CFG				0x0020
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+#define CCORR_RELAY_MODE			BIT(0)
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+#define CCORR_ENGINE_EN				BIT(1)
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+#define CCORR_GAMMA_OFF				BIT(2)
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+#define CCORR_WGAMUT_SRC_CLIP			BIT(3)
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+#define DISP_CCORR_SIZE				0x0030
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+#define DISP_CCORR_COEF_0			0x0080
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+#define DISP_CCORR_COEF_1			0x0084
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+#define DISP_CCORR_COEF_2			0x0088
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+#define DISP_CCORR_COEF_3			0x008C
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+#define DISP_CCORR_COEF_4			0x0090
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+
53
+#define DISP_DITHER_EN				0x0000
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+#define DITHER_EN				BIT(0)
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+#define DISP_DITHER_CFG				0x0020
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+#define DITHER_RELAY_MODE			BIT(0)
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+#define DISP_DITHER_SIZE			0x0030
43
58
 
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 #define DISP_GAMMA_EN				0x0000
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60
 #define DISP_GAMMA_CFG				0x0020
..
..
@@ -72,36 +87,84 @@
72
87
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
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88
 #define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)
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89
 
90
+void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
91
+		   struct mtk_ddp_comp *comp, unsigned int offset)
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+{
93
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
94
+	if (cmdq_pkt)
95
+		cmdq_pkt_write(cmdq_pkt, comp->subsys,
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+			       comp->regs_pa + offset, value);
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+	else
98
+#endif
99
+		writel(value, comp->regs + offset);
100
+}
101
+
102
+void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
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+			   struct mtk_ddp_comp *comp,
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+			   unsigned int offset)
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+{
106
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
107
+	if (cmdq_pkt)
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+		cmdq_pkt_write(cmdq_pkt, comp->subsys,
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+			       comp->regs_pa + offset, value);
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+	else
111
+#endif
112
+		writel_relaxed(value, comp->regs + offset);
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+}
114
+
115
+void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt,
116
+			unsigned int value,
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+			struct mtk_ddp_comp *comp,
118
+			unsigned int offset,
119
+			unsigned int mask)
120
+{
121
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
122
+	if (cmdq_pkt) {
123
+		cmdq_pkt_write_mask(cmdq_pkt, comp->subsys,
124
+				    comp->regs_pa + offset, value, mask);
125
+	} else {
126
+#endif
127
+		u32 tmp = readl(comp->regs + offset);
128
+
129
+		tmp = (tmp & ~mask) | (value & mask);
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+		writel(tmp, comp->regs + offset);
131
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
132
+	}
133
+#endif
134
+}
135
+
75
136
 void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
76
-		    unsigned int CFG)
137
+		    unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
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138
 {
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139
 	/* If bpc equal to 0, the dithering function didn't be enabled */
79
140
 	if (bpc == 0)
80
141
 		return;
81
142
 
82
143
 	if (bpc >= MTK_MIN_BPC) {
83
-		writel(0, comp->regs + DISP_DITHER_5);
84
-		writel(0, comp->regs + DISP_DITHER_7);
85
-		writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
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-		       DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
87
-		       DITHER_NEW_BIT_MODE,
88
-		       comp->regs + DISP_DITHER_15);
89
-		writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
90
-		       DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
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-		       DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
92
-		       DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
93
-		       comp->regs + DISP_DITHER_16);
94
-		writel(DISP_DITHERING, comp->regs + CFG);
144
+		mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
145
+		mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
146
+		mtk_ddp_write(cmdq_pkt,
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+			      DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
148
+			      DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
149
+			      DITHER_NEW_BIT_MODE,
150
+			      comp, DISP_DITHER_15);
151
+		mtk_ddp_write(cmdq_pkt,
152
+			      DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
153
+			      DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
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+			      DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
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+			      DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
156
+			      comp, DISP_DITHER_16);
157
+		mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
95
158
 	}
96
159
 }
97
160
 
98
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 static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
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162
 			  unsigned int h, unsigned int vrefresh,
100
-			  unsigned int bpc)
163
+			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
101
164
 {
102
-	writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
103
-	writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
104
-	mtk_dither_set(comp, bpc, DISP_OD_CFG);
165
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
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+	mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
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+	mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
105
168
 }
106
169
 
107
170
 static void mtk_od_start(struct mtk_ddp_comp *comp)
..
..
@@ -116,9 +179,10 @@
116
179
 
117
180
 static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
118
181
 			   unsigned int h, unsigned int vrefresh,
119
-			   unsigned int bpc)
182
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
120
183
 {
121
-	writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
184
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
185
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE);
122
186
 }
123
187
 
124
188
 static void mtk_aal_start(struct mtk_ddp_comp *comp)
..
..
@@ -131,12 +195,99 @@
131
195
 	writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
132
196
 }
133
197
 
198
+static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
199
+			     unsigned int h, unsigned int vrefresh,
200
+			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
201
+{
202
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
203
+	mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
204
+}
205
+
206
+static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
207
+{
208
+	writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
209
+}
210
+
211
+static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
212
+{
213
+	writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
214
+}
215
+
216
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
217
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
218
+{
219
+	u16 r;
220
+
221
+	/* Sign bit. */
222
+	r = in & BIT_ULL(63) ? BIT(11) : 0;
223
+
224
+	if ((in & GENMASK_ULL(62, 33)) > 0) {
225
+		/* identity value 0x100000000 -> 0x400, */
226
+		/* if bigger this, set it to max 0x7ff. */
227
+		r |= GENMASK(10, 0);
228
+	} else {
229
+		/* take the 11 most important bits. */
230
+		r |= (in >> 22) & GENMASK(10, 0);
231
+	}
232
+
233
+	return r;
234
+}
235
+
236
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
237
+			      struct drm_crtc_state *state)
238
+{
239
+	struct drm_property_blob *blob = state->ctm;
240
+	struct drm_color_ctm *ctm;
241
+	const u64 *input;
242
+	uint16_t coeffs[9] = { 0 };
243
+	int i;
244
+	struct cmdq_pkt *cmdq_pkt = NULL;
245
+
246
+	if (!blob)
247
+		return;
248
+
249
+	ctm = (struct drm_color_ctm *)blob->data;
250
+	input = ctm->matrix;
251
+
252
+	for (i = 0; i < ARRAY_SIZE(coeffs); i++)
253
+		coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
254
+
255
+	mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
256
+		      comp, DISP_CCORR_COEF_0);
257
+	mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
258
+		      comp, DISP_CCORR_COEF_1);
259
+	mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
260
+		      comp, DISP_CCORR_COEF_2);
261
+	mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
262
+		      comp, DISP_CCORR_COEF_3);
263
+	mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
264
+		      comp, DISP_CCORR_COEF_4);
265
+}
266
+
267
+static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
268
+			      unsigned int h, unsigned int vrefresh,
269
+			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
270
+{
271
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
272
+	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
273
+}
274
+
275
+static void mtk_dither_start(struct mtk_ddp_comp *comp)
276
+{
277
+	writel(DITHER_EN, comp->regs + DISP_DITHER_EN);
278
+}
279
+
280
+static void mtk_dither_stop(struct mtk_ddp_comp *comp)
281
+{
282
+	writel_relaxed(0x0, comp->regs + DISP_DITHER_EN);
283
+}
284
+
134
285
 static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
135
286
 			     unsigned int h, unsigned int vrefresh,
136
-			     unsigned int bpc)
287
+			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
137
288
 {
138
-	writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
139
-	mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
289
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
290
+	mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
140
291
 }
141
292
 
142
293
 static void mtk_gamma_start(struct mtk_ddp_comp *comp)
..
..
@@ -179,6 +330,19 @@
179
330
 	.stop = mtk_aal_stop,
180
331
 };
181
332
 
333
+static const struct mtk_ddp_comp_funcs ddp_ccorr = {
334
+	.config = mtk_ccorr_config,
335
+	.start = mtk_ccorr_start,
336
+	.stop = mtk_ccorr_stop,
337
+	.ctm_set = mtk_ccorr_ctm_set,
338
+};
339
+
340
+static const struct mtk_ddp_comp_funcs ddp_dither = {
341
+	.config = mtk_dither_config,
342
+	.start = mtk_dither_start,
343
+	.stop = mtk_dither_stop,
344
+};
345
+
182
346
 static const struct mtk_ddp_comp_funcs ddp_gamma = {
183
347
 	.gamma_set = mtk_gamma_set,
184
348
 	.config = mtk_gamma_config,
..
..
@@ -197,11 +361,14 @@
197
361
 
198
362
 static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
199
363
 	[MTK_DISP_OVL] = "ovl",
364
+	[MTK_DISP_OVL_2L] = "ovl-2l",
200
365
 	[MTK_DISP_RDMA] = "rdma",
201
366
 	[MTK_DISP_WDMA] = "wdma",
202
367
 	[MTK_DISP_COLOR] = "color",
368
+	[MTK_DISP_CCORR] = "ccorr",
203
369
 	[MTK_DISP_AAL] = "aal",
204
370
 	[MTK_DISP_GAMMA] = "gamma",
371
+	[MTK_DISP_DITHER] = "dither",
205
372
 	[MTK_DISP_UFOE] = "ufoe",
206
373
 	[MTK_DSI] = "dsi",
207
374
 	[MTK_DPI] = "dpi",
..
..
@@ -221,8 +388,10 @@
221
388
 	[DDP_COMPONENT_AAL0]	= { MTK_DISP_AAL,	0, &ddp_aal },
222
389
 	[DDP_COMPONENT_AAL1]	= { MTK_DISP_AAL,	1, &ddp_aal },
223
390
 	[DDP_COMPONENT_BLS]	= { MTK_DISP_BLS,	0, NULL },
391
+	[DDP_COMPONENT_CCORR]	= { MTK_DISP_CCORR,	0, &ddp_ccorr },
224
392
 	[DDP_COMPONENT_COLOR0]	= { MTK_DISP_COLOR,	0, NULL },
225
393
 	[DDP_COMPONENT_COLOR1]	= { MTK_DISP_COLOR,	1, NULL },
394
+	[DDP_COMPONENT_DITHER]	= { MTK_DISP_DITHER,	0, &ddp_dither },
226
395
 	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, NULL },
227
396
 	[DDP_COMPONENT_DPI1]	= { MTK_DPI,		1, NULL },
228
397
 	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, NULL },
..
..
@@ -234,6 +403,8 @@
234
403
 	[DDP_COMPONENT_OD1]	= { MTK_DISP_OD,	1, &ddp_od },
235
404
 	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, NULL },
236
405
 	[DDP_COMPONENT_OVL1]	= { MTK_DISP_OVL,	1, NULL },
406
+	[DDP_COMPONENT_OVL_2L0]	= { MTK_DISP_OVL_2L,	0, NULL },
407
+	[DDP_COMPONENT_OVL_2L1]	= { MTK_DISP_OVL_2L,	1, NULL },
237
408
 	[DDP_COMPONENT_PWM0]	= { MTK_DISP_PWM,	0, NULL },
238
409
 	[DDP_COMPONENT_PWM1]	= { MTK_DISP_PWM,	1, NULL },
239
410
 	[DDP_COMPONENT_PWM2]	= { MTK_DISP_PWM,	2, NULL },
..
..
@@ -244,6 +415,22 @@
244
415
 	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
245
416
 	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
246
417
 };
418
+
419
+static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp,
420
+				     const enum mtk_ddp_comp_id *path,
421
+				     unsigned int path_len)
422
+{
423
+	unsigned int i;
424
+
425
+	if (path == NULL)
426
+		return false;
427
+
428
+	for (i = 0U; i < path_len; i++)
429
+		if (ddp_comp.id == path[i])
430
+			return true;
431
+
432
+	return false;
433
+}
247
434
 
248
435
 int mtk_ddp_comp_get_id(struct device_node *node,
249
436
 			enum mtk_ddp_comp_type comp_type)
..
..
@@ -260,6 +447,26 @@
260
447
 	return -EINVAL;
261
448
 }
262
449
 
450
+unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
451
+						struct mtk_ddp_comp ddp_comp)
452
+{
453
+	struct mtk_drm_private *private = drm->dev_private;
454
+	unsigned int ret = 0;
455
+
456
+	if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->main_path, private->data->main_len))
457
+		ret = BIT(0);
458
+	else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->ext_path,
459
+					  private->data->ext_len))
460
+		ret = BIT(1);
461
+	else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->third_path,
462
+					  private->data->third_len))
463
+		ret = BIT(2);
464
+	else
465
+		DRM_INFO("Failed to find comp in ddp table\n");
466
+
467
+	return ret;
468
+}
469
+
263
470
 int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
264
471
 		      struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
265
472
 		      const struct mtk_ddp_comp_funcs *funcs)
..
..
@@ -267,6 +474,11 @@
267
474
 	enum mtk_ddp_comp_type type;
268
475
 	struct device_node *larb_node;
269
476
 	struct platform_device *larb_pdev;
477
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
478
+	struct resource res;
479
+	struct cmdq_client_reg cmdq_reg;
480
+	int ret;
481
+#endif
270
482
 
271
483
 	if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
272
484
 		return -EINVAL;
..
..
@@ -294,11 +506,12 @@
294
506
 	comp->irq = of_irq_get(node, 0);
295
507
 	comp->clk = of_clk_get(node, 0);
296
508
 	if (IS_ERR(comp->clk))
297
-		comp->clk = NULL;
509
+		return PTR_ERR(comp->clk);
298
510
 
299
511
 	/* Only DMA capable components need the LARB property */
300
512
 	comp->larb_dev = NULL;
301
513
 	if (type != MTK_DISP_OVL &&
514
+	    type != MTK_DISP_OVL_2L &&
302
515
 	    type != MTK_DISP_RDMA &&
303
516
 	    type != MTK_DISP_WDMA)
304
517
 		return 0;
..
..
@@ -320,6 +533,20 @@
320
533
 
321
534
 	comp->larb_dev = &larb_pdev->dev;
322
535
 
536
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
537
+	if (of_address_to_resource(node, 0, &res) != 0) {
538
+		dev_err(dev, "Missing reg in %s node\n", node->full_name);
539
+		put_device(&larb_pdev->dev);
540
+		return -EINVAL;
541
+	}
542
+	comp->regs_pa = res.start;
543
+
544
+	ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0);
545
+	if (ret)
546
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
547
+	else
548
+		comp->subsys = cmdq_reg.subsys;
549
+#endif
323
550
 	return 0;
324
551
 }
325
552