enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/gpu/drm/i915/gvt/fb_decoder.c
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@@ -146,14 +146,12 @@
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 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
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 	u32 tiled, int stride_mask, int bpp)
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 {
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-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
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 	u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
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 	u32 stride = stride_reg;
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-	if (IS_SKYLAKE(dev_priv)
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-		|| IS_KABYLAKE(dev_priv)
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-		|| IS_BROXTON(dev_priv)) {
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+	if (INTEL_GEN(dev_priv) >= 9) {
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 		switch (tiled) {
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 		case PLANE_CTL_TILED_LINEAR:
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 			stride = stride_reg * 64;
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@@ -204,8 +202,8 @@
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 int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
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 	struct intel_vgpu_primary_plane_format *plane)
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 {
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+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
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 	u32 val, fmt;
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-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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 	int pipe;
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 	pipe = get_active_pipe(vgpu);
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@@ -217,9 +215,7 @@
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 	if (!plane->enabled)
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 		return -ENODEV;
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-	if (IS_SKYLAKE(dev_priv)
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-		|| IS_KABYLAKE(dev_priv)
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-		|| IS_BROXTON(dev_priv)) {
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+	if (INTEL_GEN(dev_priv) >= 9) {
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 		plane->tiled = val & PLANE_CTL_TILED_MASK;
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 		fmt = skl_format_to_drm(
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 			val & PLANE_CTL_FORMAT_MASK,
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@@ -249,7 +245,7 @@
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 	plane->hw_format = fmt;
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 	plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK;
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-	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
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+	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
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 		return  -EINVAL;
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 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
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@@ -260,9 +256,7 @@
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 	}
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 	plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled,
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-		(IS_SKYLAKE(dev_priv)
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-		|| IS_KABYLAKE(dev_priv)
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-		|| IS_BROXTON(dev_priv)) ?
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+		(INTEL_GEN(dev_priv) >= 9) ?
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 			(_PRI_PLANE_STRIDE_MASK >> 6) :
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 				_PRI_PLANE_STRIDE_MASK, plane->bpp);
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@@ -338,9 +332,9 @@
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 int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
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 	struct intel_vgpu_cursor_plane_format *plane)
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 {
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+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
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 	u32 val, mode, index;
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 	u32 alpha_plane, alpha_force;
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-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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 	int pipe;
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 	pipe = get_active_pipe(vgpu);
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@@ -374,7 +368,7 @@
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 			alpha_plane, alpha_force);
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 	plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK;
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-	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
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+	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
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 		return  -EINVAL;
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 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
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@@ -478,7 +472,7 @@
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 	plane->drm_format = drm_format;
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 	plane->base = vgpu_vreg_t(vgpu, SPRSURF(pipe)) & I915_GTT_PAGE_MASK;
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-	if (!intel_gvt_ggtt_validate_range(vgpu, plane->base, 0))
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+	if (!vgpu_gmadr_is_valid(vgpu, plane->base))
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 		return  -EINVAL;
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 	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);