forked from ~ljy/RK356X_SDK_RELEASE

hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87
kernel/drivers/gpu/drm/armada/armada_overlay.c
....@@ -1,16 +1,16 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (C) 2012 Russell King
34 * Rewritten from the dovefb driver, and Armada510 manuals.
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
85 */
9
-#include <drm/drmP.h>
6
+
7
+#include <drm/armada_drm.h>
108 #include <drm/drm_atomic.h>
119 #include <drm/drm_atomic_helper.h>
10
+#include <drm/drm_atomic_uapi.h>
11
+#include <drm/drm_fourcc.h>
1212 #include <drm/drm_plane_helper.h>
13
-#include <drm/armada_drm.h>
13
+
1414 #include "armada_crtc.h"
1515 #include "armada_drm.h"
1616 #include "armada_fb.h"
....@@ -26,7 +26,7 @@
2626 #define DEFAULT_ENCODING DRM_COLOR_YCBCR_BT601
2727
2828 struct armada_overlay_state {
29
- struct drm_plane_state base;
29
+ struct armada_plane_state base;
3030 u32 colorkey_yr;
3131 u32 colorkey_ug;
3232 u32 colorkey_vb;
....@@ -37,7 +37,7 @@
3737 u16 saturation;
3838 };
3939 #define drm_to_overlay_state(s) \
40
- container_of(s, struct armada_overlay_state, base)
40
+ container_of(s, struct armada_overlay_state, base.base)
4141
4242 static inline u32 armada_spu_contrast(struct drm_plane_state *state)
4343 {
....@@ -93,41 +93,39 @@
9393 armada_reg_queue_mod(regs, idx,
9494 0, CFG_PDWN16x66 | CFG_PDWN32x66,
9595 LCD_SPU_SRAM_PARA1);
96
- val = armada_rect_hw_fp(&state->src);
97
- if (armada_rect_hw_fp(&old_state->src) != val)
96
+ val = armada_src_hw(state);
97
+ if (armada_src_hw(old_state) != val)
9898 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);
99
- val = armada_rect_yx(&state->dst);
100
- if (armada_rect_yx(&old_state->dst) != val)
99
+ val = armada_dst_yx(state);
100
+ if (armada_dst_yx(old_state) != val)
101101 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);
102
- val = armada_rect_hw(&state->dst);
103
- if (armada_rect_hw(&old_state->dst) != val)
102
+ val = armada_dst_hw(state);
103
+ if (armada_dst_hw(old_state) != val)
104104 armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);
105105 /* FIXME: overlay on an interlaced display */
106106 if (old_state->src.x1 != state->src.x1 ||
107107 old_state->src.y1 != state->src.y1 ||
108
- old_state->fb != state->fb) {
108
+ old_state->fb != state->fb ||
109
+ state->crtc->state->mode_changed) {
109110 const struct drm_format_info *format;
110
- u16 src_x, pitches[3];
111
- u32 addrs[2][3];
111
+ u16 src_x;
112112
113
- armada_drm_plane_calc(state, addrs, pitches, false);
114
-
115
- armada_reg_queue_set(regs, idx, addrs[0][0],
113
+ armada_reg_queue_set(regs, idx, armada_addr(state, 0, 0),
116114 LCD_SPU_DMA_START_ADDR_Y0);
117
- armada_reg_queue_set(regs, idx, addrs[0][1],
115
+ armada_reg_queue_set(regs, idx, armada_addr(state, 0, 1),
118116 LCD_SPU_DMA_START_ADDR_U0);
119
- armada_reg_queue_set(regs, idx, addrs[0][2],
117
+ armada_reg_queue_set(regs, idx, armada_addr(state, 0, 2),
120118 LCD_SPU_DMA_START_ADDR_V0);
121
- armada_reg_queue_set(regs, idx, addrs[1][0],
119
+ armada_reg_queue_set(regs, idx, armada_addr(state, 1, 0),
122120 LCD_SPU_DMA_START_ADDR_Y1);
123
- armada_reg_queue_set(regs, idx, addrs[1][1],
121
+ armada_reg_queue_set(regs, idx, armada_addr(state, 1, 1),
124122 LCD_SPU_DMA_START_ADDR_U1);
125
- armada_reg_queue_set(regs, idx, addrs[1][2],
123
+ armada_reg_queue_set(regs, idx, armada_addr(state, 1, 2),
126124 LCD_SPU_DMA_START_ADDR_V1);
127125
128
- val = pitches[0] << 16 | pitches[0];
126
+ val = armada_pitch(state, 0) << 16 | armada_pitch(state, 0);
129127 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);
130
- val = pitches[1] << 16 | pitches[2];
128
+ val = armada_pitch(state, 1) << 16 | armada_pitch(state, 2);
131129 armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);
132130
133131 cfg = CFG_DMA_FMT(drm_fb_to_armada_fb(state->fb)->fmt) |
....@@ -145,6 +143,8 @@
145143 src_x = state->src.x1 >> 16;
146144 if (format->num_planes == 1 && src_x & (format->hsub - 1))
147145 cfg ^= CFG_DMA_MOD(CFG_SWAPUV);
146
+ if (to_armada_plane_state(state)->interlace)
147
+ cfg |= CFG_DMA_FTOGGLE;
148148 cfg_mask = CFG_CBSH_ENA | CFG_DMAFORMAT |
149149 CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV |
150150 CFG_SWAPYU | CFG_YUV2RGB) |
....@@ -306,13 +306,10 @@
306306 if (plane->state)
307307 __drm_atomic_helper_plane_destroy_state(plane->state);
308308 kfree(plane->state);
309
+ plane->state = NULL;
309310
310311 state = kzalloc(sizeof(*state), GFP_KERNEL);
311312 if (state) {
312
- state->base.plane = plane;
313
- state->base.color_encoding = DEFAULT_ENCODING;
314
- state->base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
315
- state->base.rotation = DRM_MODE_ROTATE_0;
316313 state->colorkey_yr = 0xfefefe00;
317314 state->colorkey_ug = 0x01010100;
318315 state->colorkey_vb = 0x01010100;
....@@ -322,8 +319,10 @@
322319 state->brightness = DEFAULT_BRIGHTNESS;
323320 state->contrast = DEFAULT_CONTRAST;
324321 state->saturation = DEFAULT_SATURATION;
322
+ __drm_atomic_helper_plane_reset(plane, &state->base.base);
323
+ state->base.base.color_encoding = DEFAULT_ENCODING;
324
+ state->base.base.color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
325325 }
326
- plane->state = &state->base;
327326 }
328327
329328 struct drm_plane_state *
....@@ -336,15 +335,16 @@
336335
337336 state = kmemdup(plane->state, sizeof(*state), GFP_KERNEL);
338337 if (state)
339
- __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
340
- return &state->base;
338
+ __drm_atomic_helper_plane_duplicate_state(plane,
339
+ &state->base.base);
340
+ return &state->base.base;
341341 }
342342
343343 static int armada_overlay_set_property(struct drm_plane *plane,
344344 struct drm_plane_state *state, struct drm_property *property,
345345 uint64_t val)
346346 {
347
- struct armada_private *priv = plane->dev->dev_private;
347
+ struct armada_private *priv = drm_to_armada_dev(plane->dev);
348348
349349 #define K2R(val) (((val) >> 0) & 0xff)
350350 #define K2G(val) (((val) >> 8) & 0xff)
....@@ -412,7 +412,7 @@
412412 const struct drm_plane_state *state, struct drm_property *property,
413413 uint64_t *val)
414414 {
415
- struct armada_private *priv = plane->dev->dev_private;
415
+ struct armada_private *priv = drm_to_armada_dev(plane->dev);
416416
417417 #define C2K(c,s) (((c) >> (s)) & 0xff)
418418 #define R2BGR(r,g,b,s) (C2K(r,s) << 0 | C2K(g,s) << 8 | C2K(b,s) << 16)
....@@ -505,7 +505,7 @@
505505
506506 static int armada_overlay_create_properties(struct drm_device *dev)
507507 {
508
- struct armada_private *priv = dev->dev_private;
508
+ struct armada_private *priv = drm_to_armada_dev(dev);
509509
510510 if (priv->colorkey_prop)
511511 return 0;
....@@ -539,7 +539,7 @@
539539
540540 int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
541541 {
542
- struct armada_private *priv = dev->dev_private;
542
+ struct armada_private *priv = drm_to_armada_dev(dev);
543543 struct drm_mode_object *mobj;
544544 struct drm_plane *overlay;
545545 int ret;