~hc/RK356X_SDK_RELEASE.git

..	..	@@ -9,10 +9,12 @@
9	9	#include <linux/ctype.h>
10	10	#include <linux/delay.h>
11	11	#include <linux/edac.h>
	12	+#include <linux/firmware/intel/stratix10-smc.h>
12	13	#include <linux/genalloc.h>
13	14	#include <linux/interrupt.h>
14	15	#include <linux/irqchip/chained_irq.h>
15	16	#include <linux/kernel.h>
	17	+#include <linux/mfd/altera-sysmgr.h>
16	18	#include <linux/mfd/syscon.h>
17	19	#include <linux/notifier.h>
18	20	#include <linux/of_address.h>
..	..	@@ -29,6 +31,7 @@
29	31	#define EDAC_MOD_STR "altera_edac"
30	32	#define EDAC_DEVICE "Altera"
31	33
	34	+#ifdef CONFIG_EDAC_ALTERA_SDRAM
32	35	static const struct altr_sdram_prv_data c5_data = {
33	36	.ecc_ctrl_offset = CV_CTLCFG_OFST,
34	37	.ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
..	..	@@ -65,25 +68,6 @@
65	68	.ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
66	69	.ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
67	70	.ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
68		- .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
69		- .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
70		-};
71		-
72		-static const struct altr_sdram_prv_data s10_data = {
73		- .ecc_ctrl_offset = S10_ECCCTRL1_OFST,
74		- .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
75		- .ecc_stat_offset = S10_INTSTAT_OFST,
76		- .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
77		- .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
78		- .ecc_saddr_offset = S10_SERRADDR_OFST,
79		- .ecc_daddr_offset = S10_DERRADDR_OFST,
80		- .ecc_irq_en_offset = S10_ERRINTEN_OFST,
81		- .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
82		- .ecc_irq_clr_offset = S10_INTSTAT_OFST,
83		- .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR \| A10_INTSTAT_DBEERR),
84		- .ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
85		- .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
86		- .ce_ue_trgr_offset = S10_DIAGINTTEST_OFST,
87	71	.ce_set_mask = A10_DIAGINT_TSERRA_MASK,
88	72	.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
89	73	};
..	..	@@ -239,7 +223,6 @@
239	223	static const struct of_device_id altr_sdram_ctrl_of_match[] = {
240	224	{ .compatible = "altr,sdram-edac", .data = &c5_data},
241	225	{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
242		- { .compatible = "altr,sdram-edac-s10", .data = &s10_data},
243	226	{},
244	227	};
245	228	MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
..	..	@@ -416,7 +399,7 @@
416	399	goto err;
417	400
418	401	/* Only the Arria10 has separate IRQs */
419		- if (irq2 > 0) {
	402	+ if (of_machine_is_compatible("altr,socfpga-arria10")) {
420	403	/* Arria10 specific initialization */
421	404	res = a10_init(mc_vbase);
422	405	if (res < 0)
..	..	@@ -486,293 +469,6 @@
486	469	return 0;
487	470	}
488	471
489		-/************** Stratix 10 EDAC Memory Controller Functions **********/
490		-
491		-/**
492		- * s10_protected_reg_write
493		- * Write to a protected SMC register.
494		- * @context: Not used.
495		- * @reg: Address of register
496		- * @value: Value to write
497		- * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
498		- * INTEL_SIP_SMC_REG_ERROR on error
499		- * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
500		- */
501		-static int s10_protected_reg_write(void *context, unsigned int reg,
502		- unsigned int val)
503		-{
504		- struct arm_smccc_res result;
505		-
506		- arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
507		- 0, 0, 0, &result);
508		-
509		- return (int)result.a0;
510		-}
511		-
512		-/**
513		- * s10_protected_reg_read
514		- * Read the status of a protected SMC register
515		- * @context: Not used.
516		- * @reg: Address of register
517		- * @value: Value read.
518		- * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
519		- * INTEL_SIP_SMC_REG_ERROR on error
520		- * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
521		- */
522		-static int s10_protected_reg_read(void *context, unsigned int reg,
523		- unsigned int *val)
524		-{
525		- struct arm_smccc_res result;
526		-
527		- arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0,
528		- 0, 0, 0, &result);
529		-
530		- *val = (unsigned int)result.a1;
531		-
532		- return (int)result.a0;
533		-}
534		-
535		-static bool s10_sdram_writeable_reg(struct device *dev, unsigned int reg)
536		-{
537		- switch (reg) {
538		- case S10_ECCCTRL1_OFST:
539		- case S10_ERRINTEN_OFST:
540		- case S10_INTMODE_OFST:
541		- case S10_INTSTAT_OFST:
542		- case S10_DIAGINTTEST_OFST:
543		- case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
544		- case S10_SYSMGR_ECC_INTMASK_SET_OFST:
545		- case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
546		- return true;
547		- }
548		- return false;
549		-}
550		-
551		-static bool s10_sdram_readable_reg(struct device *dev, unsigned int reg)
552		-{
553		- switch (reg) {
554		- case S10_ECCCTRL1_OFST:
555		- case S10_ERRINTEN_OFST:
556		- case S10_INTMODE_OFST:
557		- case S10_INTSTAT_OFST:
558		- case S10_DERRADDR_OFST:
559		- case S10_SERRADDR_OFST:
560		- case S10_DIAGINTTEST_OFST:
561		- case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
562		- case S10_SYSMGR_ECC_INTMASK_SET_OFST:
563		- case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
564		- case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
565		- case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
566		- return true;
567		- }
568		- return false;
569		-}
570		-
571		-static bool s10_sdram_volatile_reg(struct device *dev, unsigned int reg)
572		-{
573		- switch (reg) {
574		- case S10_ECCCTRL1_OFST:
575		- case S10_ERRINTEN_OFST:
576		- case S10_INTMODE_OFST:
577		- case S10_INTSTAT_OFST:
578		- case S10_DERRADDR_OFST:
579		- case S10_SERRADDR_OFST:
580		- case S10_DIAGINTTEST_OFST:
581		- case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
582		- case S10_SYSMGR_ECC_INTMASK_SET_OFST:
583		- case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
584		- case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
585		- case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
586		- return true;
587		- }
588		- return false;
589		-}
590		-
591		-static const struct regmap_config s10_sdram_regmap_cfg = {
592		- .name = "s10_ddr",
593		- .reg_bits = 32,
594		- .reg_stride = 4,
595		- .val_bits = 32,
596		- .max_register = 0xffffffff,
597		- .writeable_reg = s10_sdram_writeable_reg,
598		- .readable_reg = s10_sdram_readable_reg,
599		- .volatile_reg = s10_sdram_volatile_reg,
600		- .reg_read = s10_protected_reg_read,
601		- .reg_write = s10_protected_reg_write,
602		- .use_single_rw = true,
603		-};
604		-
605		-static int altr_s10_sdram_probe(struct platform_device *pdev)
606		-{
607		- const struct of_device_id *id;
608		- struct edac_mc_layer layers[2];
609		- struct mem_ctl_info *mci;
610		- struct altr_sdram_mc_data *drvdata;
611		- const struct altr_sdram_prv_data *priv;
612		- struct regmap *regmap;
613		- struct dimm_info *dimm;
614		- u32 read_reg;
615		- int irq, ret = 0;
616		- unsigned long mem_size;
617		-
618		- id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
619		- if (!id)
620		- return -ENODEV;
621		-
622		- /* Grab specific offsets and masks for Stratix10 */
623		- priv = of_match_node(altr_sdram_ctrl_of_match,
624		- pdev->dev.of_node)->data;
625		-
626		- regmap = devm_regmap_init(&pdev->dev, NULL, (void *)priv,
627		- &s10_sdram_regmap_cfg);
628		- if (IS_ERR(regmap))
629		- return PTR_ERR(regmap);
630		-
631		- /* Validate the SDRAM controller has ECC enabled */
632		- if (regmap_read(regmap, priv->ecc_ctrl_offset, &read_reg) \|\|
633		- ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
634		- edac_printk(KERN_ERR, EDAC_MC,
635		- "No ECC/ECC disabled [0x%08X]\n", read_reg);
636		- return -ENODEV;
637		- }
638		-
639		- /* Grab memory size from device tree. */
640		- mem_size = get_total_mem();
641		- if (!mem_size) {
642		- edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
643		- return -ENODEV;
644		- }
645		-
646		- /* Ensure the SDRAM Interrupt is disabled */
647		- if (regmap_update_bits(regmap, priv->ecc_irq_en_offset,
648		- priv->ecc_irq_en_mask, 0)) {
649		- edac_printk(KERN_ERR, EDAC_MC,
650		- "Error disabling SDRAM ECC IRQ\n");
651		- return -ENODEV;
652		- }
653		-
654		- /* Toggle to clear the SDRAM Error count */
655		- if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
656		- priv->ecc_cnt_rst_mask,
657		- priv->ecc_cnt_rst_mask)) {
658		- edac_printk(KERN_ERR, EDAC_MC,
659		- "Error clearing SDRAM ECC count\n");
660		- return -ENODEV;
661		- }
662		-
663		- if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
664		- priv->ecc_cnt_rst_mask, 0)) {
665		- edac_printk(KERN_ERR, EDAC_MC,
666		- "Error clearing SDRAM ECC count\n");
667		- return -ENODEV;
668		- }
669		-
670		- irq = platform_get_irq(pdev, 0);
671		- if (irq < 0) {
672		- edac_printk(KERN_ERR, EDAC_MC,
673		- "No irq %d in DT\n", irq);
674		- return -ENODEV;
675		- }
676		-
677		- layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
678		- layers[0].size = 1;
679		- layers[0].is_virt_csrow = true;
680		- layers[1].type = EDAC_MC_LAYER_CHANNEL;
681		- layers[1].size = 1;
682		- layers[1].is_virt_csrow = false;
683		- mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
684		- sizeof(struct altr_sdram_mc_data));
685		- if (!mci)
686		- return -ENOMEM;
687		-
688		- mci->pdev = &pdev->dev;
689		- drvdata = mci->pvt_info;
690		- drvdata->mc_vbase = regmap;
691		- drvdata->data = priv;
692		- platform_set_drvdata(pdev, mci);
693		-
694		- if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
695		- edac_printk(KERN_ERR, EDAC_MC,
696		- "Unable to get managed device resource\n");
697		- ret = -ENOMEM;
698		- goto free;
699		- }
700		-
701		- mci->mtype_cap = MEM_FLAG_DDR3;
702		- mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
703		- mci->edac_cap = EDAC_FLAG_SECDED;
704		- mci->mod_name = EDAC_MOD_STR;
705		- mci->ctl_name = dev_name(&pdev->dev);
706		- mci->scrub_mode = SCRUB_SW_SRC;
707		- mci->dev_name = dev_name(&pdev->dev);
708		-
709		- dimm = *mci->dimms;
710		- dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
711		- dimm->grain = 8;
712		- dimm->dtype = DEV_X8;
713		- dimm->mtype = MEM_DDR3;
714		- dimm->edac_mode = EDAC_SECDED;
715		-
716		- ret = edac_mc_add_mc(mci);
717		- if (ret < 0)
718		- goto err;
719		-
720		- ret = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
721		- IRQF_SHARED, dev_name(&pdev->dev), mci);
722		- if (ret < 0) {
723		- edac_mc_printk(mci, KERN_ERR,
724		- "Unable to request irq %d\n", irq);
725		- ret = -ENODEV;
726		- goto err2;
727		- }
728		-
729		- if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
730		- S10_DDR0_IRQ_MASK)) {
731		- edac_printk(KERN_ERR, EDAC_MC,
732		- "Error clearing SDRAM ECC count\n");
733		- ret = -ENODEV;
734		- goto err2;
735		- }
736		-
737		- if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
738		- priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
739		- edac_mc_printk(mci, KERN_ERR,
740		- "Error enabling SDRAM ECC IRQ\n");
741		- ret = -ENODEV;
742		- goto err2;
743		- }
744		-
745		- altr_sdr_mc_create_debugfs_nodes(mci);
746		-
747		- devres_close_group(&pdev->dev, NULL);
748		-
749		- return 0;
750		-
751		-err2:
752		- edac_mc_del_mc(&pdev->dev);
753		-err:
754		- devres_release_group(&pdev->dev, NULL);
755		-free:
756		- edac_mc_free(mci);
757		- edac_printk(KERN_ERR, EDAC_MC,
758		- "EDAC Probe Failed; Error %d\n", ret);
759		-
760		- return ret;
761		-}
762		-
763		-static int altr_s10_sdram_remove(struct platform_device *pdev)
764		-{
765		- struct mem_ctl_info *mci = platform_get_drvdata(pdev);
766		-
767		- edac_mc_del_mc(&pdev->dev);
768		- edac_mc_free(mci);
769		- platform_set_drvdata(pdev, NULL);
770		-
771		- return 0;
772		-}
773		-
774		-/************ </Stratix10 EDAC Memory Controller Functions> *********/
775		-
776	472	/*
777	473	* If you want to suspend, need to disable EDAC by removing it
778	474	* from the device tree or defconfig.
..	..	@@ -804,19 +500,7 @@
804	500
805	501	module_platform_driver(altr_sdram_edac_driver);
806	502
807		-static struct platform_driver altr_s10_sdram_edac_driver = {
808		- .probe = altr_s10_sdram_probe,
809		- .remove = altr_s10_sdram_remove,
810		- .driver = {
811		- .name = "altr_s10_sdram_edac",
812		-#ifdef CONFIG_PM
813		- .pm = &altr_sdram_pm_ops,
814		-#endif
815		- .of_match_table = altr_sdram_ctrl_of_match,
816		- },
817		-};
818		-
819		-module_platform_driver(altr_s10_sdram_edac_driver);
	503	+#endif /* CONFIG_EDAC_ALTERA_SDRAM */
820	504
821	505	/*********************** EDAC Parent Probe ***********************/
822	506
..	..	@@ -968,6 +652,16 @@
968	652	static const struct file_operations altr_edac_a10_device_inject_fops = {
969	653	.open = simple_open,
970	654	.write = altr_edac_a10_device_trig,
	655	+ .llseek = generic_file_llseek,
	656	+};
	657	+
	658	+static ssize_t altr_edac_a10_device_trig2(struct file *file,
	659	+ const char __user *user_buf,
	660	+ size_t count, loff_t *ppos);
	661	+
	662	+static const struct file_operations altr_edac_a10_device_inject2_fops = {
	663	+ .open = simple_open,
	664	+ .write = altr_edac_a10_device_trig2,
971	665	.llseek = generic_file_llseek,
972	666	};
973	667
..	..	@@ -1266,8 +960,11 @@
1266	960
1267	961	/* Get the ECC Manager - parent of the device EDACs */
1268	962	np_eccmgr = of_get_parent(np);
1269		- ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
1270		- "altr,sysmgr-syscon");
	963	+
	964	+ ecc_mgr_map =
	965	+ altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
	966	+ "altr,sysmgr-syscon");
	967	+
1271	968	of_node_put(np_eccmgr);
1272	969	if (IS_ERR(ecc_mgr_map)) {
1273	970	edac_printk(KERN_ERR, EDAC_DEVICE,
..	..	@@ -1325,20 +1022,12 @@
1325	1022	return ret;
1326	1023	}
1327	1024
1328		-static int socfpga_is_a10(void)
1329		-{
1330		- return of_machine_is_compatible("altr,socfpga-arria10");
1331		-}
1332		-
1333	1025	static int validate_parent_available(struct device_node *np);
1334	1026	static const struct of_device_id altr_edac_a10_device_of_match[];
1335	1027	static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1336	1028	{
1337	1029	int irq;
1338	1030	struct device_node child, np;
1339		-
1340		- if (!socfpga_is_a10())
1341		- return -ENODEV;
1342	1031
1343	1032	np = of_find_compatible_node(NULL, NULL,
1344	1033	"altr,socfpga-a10-ecc-manager");
..	..	@@ -1380,6 +1069,24 @@
1380	1069	of_node_put(np);
1381	1070	return 0;
1382	1071	}
	1072	+
	1073	+/********************* SDRAM EDAC Device Functions *******************/
	1074	+
	1075	+#ifdef CONFIG_EDAC_ALTERA_SDRAM
	1076	+
	1077	+static const struct edac_device_prv_data s10_sdramecc_data = {
	1078	+ .setup = altr_check_ecc_deps,
	1079	+ .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
	1080	+ .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
	1081	+ .ecc_enable_mask = ALTR_S10_ECC_EN,
	1082	+ .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
	1083	+ .ce_set_mask = ALTR_S10_ECC_TSERRA,
	1084	+ .ue_set_mask = ALTR_S10_ECC_TDERRA,
	1085	+ .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
	1086	+ .ecc_irq_handler = altr_edac_a10_ecc_irq,
	1087	+ .inject_fops = &altr_edac_a10_device_inject_fops,
	1088	+};
	1089	+#endif /* CONFIG_EDAC_ALTERA_SDRAM */
1383	1090
1384	1091	/********************* OCRAM EDAC Device Functions *******************/
1385	1092
..	..	@@ -1434,8 +1141,31 @@
1434	1141	.inject_fops = &altr_edac_device_inject_fops,
1435	1142	};
1436	1143
	1144	+static int __maybe_unused
	1145	+altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
	1146	+{
	1147	+ void __iomem *base = device->base;
	1148	+ int ret;
	1149	+
	1150	+ ret = altr_check_ecc_deps(device);
	1151	+ if (ret)
	1152	+ return ret;
	1153	+
	1154	+ /* Verify OCRAM has been initialized */
	1155	+ if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
	1156	+ (base + ALTR_A10_ECC_INITSTAT_OFST)))
	1157	+ return -ENODEV;
	1158	+
	1159	+ /* Enable IRQ on Single Bit Error */
	1160	+ writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
	1161	+ /* Ensure all writes complete */
	1162	+ wmb();
	1163	+
	1164	+ return 0;
	1165	+}
	1166	+
1437	1167	static const struct edac_device_prv_data a10_ocramecc_data = {
1438		- .setup = altr_check_ecc_deps,
	1168	+ .setup = altr_check_ocram_deps_init,
1439	1169	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1440	1170	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1441	1171	.irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
..	..	@@ -1445,7 +1175,7 @@
1445	1175	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1446	1176	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1447	1177	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1448		- .inject_fops = &altr_edac_a10_device_inject_fops,
	1178	+ .inject_fops = &altr_edac_a10_device_inject2_fops,
1449	1179	/*
1450	1180	* OCRAM panic on uncorrectable error because sleep/resume
1451	1181	* functions and FPGA contents are stored in OCRAM. Prefer
..	..	@@ -1573,8 +1303,19 @@
1573	1303
1574	1304	#ifdef CONFIG_EDAC_ALTERA_ETHERNET
1575	1305
	1306	+static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
	1307	+{
	1308	+ int ret;
	1309	+
	1310	+ ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
	1311	+ if (ret)
	1312	+ return ret;
	1313	+
	1314	+ return altr_check_ecc_deps(dev);
	1315	+}
	1316	+
1576	1317	static const struct edac_device_prv_data a10_enetecc_data = {
1577		- .setup = altr_check_ecc_deps,
	1318	+ .setup = socfpga_init_ethernet_ecc,
1578	1319	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1579	1320	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1580	1321	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
..	..	@@ -1583,15 +1324,8 @@
1583	1324	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1584	1325	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1585	1326	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1586		- .inject_fops = &altr_edac_a10_device_inject_fops,
	1327	+ .inject_fops = &altr_edac_a10_device_inject2_fops,
1587	1328	};
1588		-
1589		-static int __init socfpga_init_ethernet_ecc(void)
1590		-{
1591		- return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1592		-}
1593		-
1594		-early_initcall(socfpga_init_ethernet_ecc);
1595	1329
1596	1330	#endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1597	1331
..	..	@@ -1599,8 +1333,19 @@
1599	1333
1600	1334	#ifdef CONFIG_EDAC_ALTERA_NAND
1601	1335
	1336	+static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
	1337	+{
	1338	+ int ret;
	1339	+
	1340	+ ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
	1341	+ if (ret)
	1342	+ return ret;
	1343	+
	1344	+ return altr_check_ecc_deps(device);
	1345	+}
	1346	+
1602	1347	static const struct edac_device_prv_data a10_nandecc_data = {
1603		- .setup = altr_check_ecc_deps,
	1348	+ .setup = socfpga_init_nand_ecc,
1604	1349	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1605	1350	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1606	1351	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
..	..	@@ -1611,13 +1356,6 @@
1611	1356	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1612	1357	.inject_fops = &altr_edac_a10_device_inject_fops,
1613	1358	};
1614		-
1615		-static int __init socfpga_init_nand_ecc(void)
1616		-{
1617		- return altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1618		-}
1619		-
1620		-early_initcall(socfpga_init_nand_ecc);
1621	1359
1622	1360	#endif /* CONFIG_EDAC_ALTERA_NAND */
1623	1361
..	..	@@ -1625,8 +1363,19 @@
1625	1363
1626	1364	#ifdef CONFIG_EDAC_ALTERA_DMA
1627	1365
	1366	+static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
	1367	+{
	1368	+ int ret;
	1369	+
	1370	+ ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
	1371	+ if (ret)
	1372	+ return ret;
	1373	+
	1374	+ return altr_check_ecc_deps(device);
	1375	+}
	1376	+
1628	1377	static const struct edac_device_prv_data a10_dmaecc_data = {
1629		- .setup = altr_check_ecc_deps,
	1378	+ .setup = socfpga_init_dma_ecc,
1630	1379	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1631	1380	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1632	1381	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
..	..	@@ -1637,13 +1386,6 @@
1637	1386	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1638	1387	.inject_fops = &altr_edac_a10_device_inject_fops,
1639	1388	};
1640		-
1641		-static int __init socfpga_init_dma_ecc(void)
1642		-{
1643		- return altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1644		-}
1645		-
1646		-early_initcall(socfpga_init_dma_ecc);
1647	1389
1648	1390	#endif /* CONFIG_EDAC_ALTERA_DMA */
1649	1391
..	..	@@ -1651,8 +1393,19 @@
1651	1393
1652	1394	#ifdef CONFIG_EDAC_ALTERA_USB
1653	1395
	1396	+static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
	1397	+{
	1398	+ int ret;
	1399	+
	1400	+ ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
	1401	+ if (ret)
	1402	+ return ret;
	1403	+
	1404	+ return altr_check_ecc_deps(device);
	1405	+}
	1406	+
1654	1407	static const struct edac_device_prv_data a10_usbecc_data = {
1655		- .setup = altr_check_ecc_deps,
	1408	+ .setup = socfpga_init_usb_ecc,
1656	1409	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1657	1410	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1658	1411	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
..	..	@@ -1661,15 +1414,8 @@
1661	1414	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1662	1415	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1663	1416	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1664		- .inject_fops = &altr_edac_a10_device_inject_fops,
	1417	+ .inject_fops = &altr_edac_a10_device_inject2_fops,
1665	1418	};
1666		-
1667		-static int __init socfpga_init_usb_ecc(void)
1668		-{
1669		- return altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1670		-}
1671		-
1672		-early_initcall(socfpga_init_usb_ecc);
1673	1419
1674	1420	#endif /* CONFIG_EDAC_ALTERA_USB */
1675	1421
..	..	@@ -1677,8 +1423,19 @@
1677	1423
1678	1424	#ifdef CONFIG_EDAC_ALTERA_QSPI
1679	1425
	1426	+static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
	1427	+{
	1428	+ int ret;
	1429	+
	1430	+ ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
	1431	+ if (ret)
	1432	+ return ret;
	1433	+
	1434	+ return altr_check_ecc_deps(device);
	1435	+}
	1436	+
1680	1437	static const struct edac_device_prv_data a10_qspiecc_data = {
1681		- .setup = altr_check_ecc_deps,
	1438	+ .setup = socfpga_init_qspi_ecc,
1682	1439	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1683	1440	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1684	1441	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
..	..	@@ -1689,13 +1446,6 @@
1689	1446	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1690	1447	.inject_fops = &altr_edac_a10_device_inject_fops,
1691	1448	};
1692		-
1693		-static int __init socfpga_init_qspi_ecc(void)
1694		-{
1695		- return altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1696		-}
1697		-
1698		-early_initcall(socfpga_init_qspi_ecc);
1699	1449
1700	1450	#endif /* CONFIG_EDAC_ALTERA_QSPI */
1701	1451
..	..	@@ -1751,8 +1501,12 @@
1751	1501	dci->mod_name = ecc_name;
1752	1502	dci->dev_name = ecc_name;
1753	1503
1754		- /* Update the IRQs for PortB */
	1504	+ /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */
	1505	+#ifdef CONFIG_ARCH_STRATIX10
	1506	+ altdev->sb_irq = irq_of_parse_and_map(np, 1);
	1507	+#else
1755	1508	altdev->sb_irq = irq_of_parse_and_map(np, 2);
	1509	+#endif
1756	1510	if (!altdev->sb_irq) {
1757	1511	edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1758	1512	rc = -ENODEV;
..	..	@@ -1767,6 +1521,15 @@
1767	1521	goto err_release_group_1;
1768	1522	}
1769	1523
	1524	+#ifdef CONFIG_ARCH_STRATIX10
	1525	+ /* Use IRQ to determine SError origin instead of assigning IRQ */
	1526	+ rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
	1527	+ if (rc) {
	1528	+ edac_printk(KERN_ERR, EDAC_DEVICE,
	1529	+ "Error PortB DBIRQ alloc\n");
	1530	+ goto err_release_group_1;
	1531	+ }
	1532	+#else
1770	1533	altdev->db_irq = irq_of_parse_and_map(np, 3);
1771	1534	if (!altdev->db_irq) {
1772	1535	edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
..	..	@@ -1781,6 +1544,7 @@
1781	1544	edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1782	1545	goto err_release_group_1;
1783	1546	}
	1547	+#endif
1784	1548
1785	1549	rc = edac_device_add_device(dci);
1786	1550	if (rc) {
..	..	@@ -1802,6 +1566,35 @@
1802	1566	devres_release_group(&altdev->ddev, altr_portb_setup);
1803	1567	edac_printk(KERN_ERR, EDAC_DEVICE,
1804	1568	"%s:Error setting up EDAC device: %d\n", ecc_name, rc);
	1569	+ return rc;
	1570	+}
	1571	+
	1572	+static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
	1573	+{
	1574	+ int rc = -ENODEV;
	1575	+ struct device_node *child;
	1576	+
	1577	+ child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
	1578	+ if (!child)
	1579	+ return -ENODEV;
	1580	+
	1581	+ if (!of_device_is_available(child))
	1582	+ goto exit;
	1583	+
	1584	+ if (validate_parent_available(child))
	1585	+ goto exit;
	1586	+
	1587	+ /* Init portB */
	1588	+ rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
	1589	+ a10_sdmmceccb_data.ecc_enable_mask, 1);
	1590	+ if (rc)
	1591	+ goto exit;
	1592	+
	1593	+ /* Setup portB */
	1594	+ return altr_portb_setup(device);
	1595	+
	1596	+exit:
	1597	+ of_node_put(child);
1805	1598	return rc;
1806	1599	}
1807	1600
..	..	@@ -1829,7 +1622,7 @@
1829	1622	}
1830	1623
1831	1624	static const struct edac_device_prv_data a10_sdmmcecca_data = {
1832		- .setup = altr_portb_setup,
	1625	+ .setup = socfpga_init_sdmmc_ecc,
1833	1626	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1834	1627	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1835	1628	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
..	..	@@ -1842,7 +1635,7 @@
1842	1635	};
1843	1636
1844	1637	static const struct edac_device_prv_data a10_sdmmceccb_data = {
1845		- .setup = altr_portb_setup,
	1638	+ .setup = socfpga_init_sdmmc_ecc,
1846	1639	.ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1847	1640	.ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1848	1641	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
..	..	@@ -1853,35 +1646,6 @@
1853	1646	.ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1854	1647	.inject_fops = &altr_edac_a10_device_inject_fops,
1855	1648	};
1856		-
1857		-static int __init socfpga_init_sdmmc_ecc(void)
1858		-{
1859		- int rc = -ENODEV;
1860		- struct device_node *child;
1861		-
1862		- if (!socfpga_is_a10())
1863		- return -ENODEV;
1864		-
1865		- child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1866		- if (!child) {
1867		- edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1868		- return -ENODEV;
1869		- }
1870		-
1871		- if (!of_device_is_available(child))
1872		- goto exit;
1873		-
1874		- if (validate_parent_available(child))
1875		- goto exit;
1876		-
1877		- rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1878		- a10_sdmmcecca_data.ecc_enable_mask, 1);
1879		-exit:
1880		- of_node_put(child);
1881		- return rc;
1882		-}
1883		-
1884		-early_initcall(socfpga_init_sdmmc_ecc);
1885	1649
1886	1650	#endif /* CONFIG_EDAC_ALTERA_SDMMC */
1887	1651
..	..	@@ -1913,6 +1677,9 @@
1913	1677	#ifdef CONFIG_EDAC_ALTERA_SDMMC
1914	1678	{ .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1915	1679	#endif
	1680	+#ifdef CONFIG_EDAC_ALTERA_SDRAM
	1681	+ { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
	1682	+#endif
1916	1683	{},
1917	1684	};
1918	1685	MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
..	..	@@ -1943,6 +1710,70 @@
1943	1710	writel(priv->ue_set_mask, set_addr);
1944	1711	else
1945	1712	writel(priv->ce_set_mask, set_addr);
	1713	+
	1714	+ /* Ensure the interrupt test bits are set */
	1715	+ wmb();
	1716	+ local_irq_restore(flags);
	1717	+
	1718	+ return count;
	1719	+}
	1720	+
	1721	+/*
	1722	+ * The Stratix10 EDAC Error Injection Functions differ from Arria10
	1723	+ * slightly. A few Arria10 peripherals can use this injection function.
	1724	+ * Inject the error into the memory and then readback to trigger the IRQ.
	1725	+ */
	1726	+static ssize_t altr_edac_a10_device_trig2(struct file *file,
	1727	+ const char __user *user_buf,
	1728	+ size_t count, loff_t *ppos)
	1729	+{
	1730	+ struct edac_device_ctl_info *edac_dci = file->private_data;
	1731	+ struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
	1732	+ const struct edac_device_prv_data *priv = drvdata->data;
	1733	+ void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
	1734	+ unsigned long flags;
	1735	+ u8 trig_type;
	1736	+
	1737	+ if (!user_buf \|\| get_user(trig_type, user_buf))
	1738	+ return -EFAULT;
	1739	+
	1740	+ local_irq_save(flags);
	1741	+ if (trig_type == ALTR_UE_TRIGGER_CHAR) {
	1742	+ writel(priv->ue_set_mask, set_addr);
	1743	+ } else {
	1744	+ /* Setup read/write of 4 bytes */
	1745	+ writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
	1746	+ /* Setup Address to 0 */
	1747	+ writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
	1748	+ /* Setup accctrl to read & ecc & data override */
	1749	+ writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
	1750	+ /* Kick it. */
	1751	+ writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
	1752	+ /* Setup write for single bit change */
	1753	+ writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
	1754	+ drvdata->base + ECC_BLK_WDATA0_OFST);
	1755	+ writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
	1756	+ drvdata->base + ECC_BLK_WDATA1_OFST);
	1757	+ writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
	1758	+ drvdata->base + ECC_BLK_WDATA2_OFST);
	1759	+ writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
	1760	+ drvdata->base + ECC_BLK_WDATA3_OFST);
	1761	+
	1762	+ /* Copy Read ECC to Write ECC */
	1763	+ writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
	1764	+ drvdata->base + ECC_BLK_WECC0_OFST);
	1765	+ writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
	1766	+ drvdata->base + ECC_BLK_WECC1_OFST);
	1767	+ /* Setup accctrl to write & ecc override & data override */
	1768	+ writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
	1769	+ /* Kick it. */
	1770	+ writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
	1771	+ /* Setup accctrl to read & ecc overwrite & data overwrite */
	1772	+ writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
	1773	+ /* Kick it. */
	1774	+ writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
	1775	+ }
	1776	+
1946	1777	/* Ensure the interrupt test bits are set */
1947	1778	wmb();
1948	1779	local_irq_restore(flags);
..	..	@@ -1981,12 +1812,32 @@
1981	1812	struct device_node *parent;
1982	1813	int ret = 0;
1983	1814
	1815	+ /* SDRAM must be present for Linux (implied parent) */
	1816	+ if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
	1817	+ return 0;
	1818	+
1984	1819	/* Ensure parent device is enabled if parent node exists */
1985	1820	parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1986	1821	if (parent && !of_device_is_available(parent))
1987	1822	ret = -ENODEV;
1988	1823
1989	1824	of_node_put(parent);
	1825	+ return ret;
	1826	+}
	1827	+
	1828	+static int get_s10_sdram_edac_resource(struct device_node *np,
	1829	+ struct resource *res)
	1830	+{
	1831	+ struct device_node *parent;
	1832	+ int ret;
	1833	+
	1834	+ parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
	1835	+ if (!parent)
	1836	+ return -ENODEV;
	1837	+
	1838	+ ret = of_address_to_resource(parent, 0, res);
	1839	+ of_node_put(parent);
	1840	+
1990	1841	return ret;
1991	1842	}
1992	1843
..	..	@@ -2017,7 +1868,11 @@
2017	1868	if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
2018	1869	return -ENOMEM;
2019	1870
2020		- rc = of_address_to_resource(np, 0, &res);
	1871	+ if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
	1872	+ rc = get_s10_sdram_edac_resource(np, &res);
	1873	+ else
	1874	+ rc = of_address_to_resource(np, 0, &res);
	1875	+
2021	1876	if (rc < 0) {
2022	1877	edac_printk(KERN_ERR, EDAC_DEVICE,
2023	1878	"%s: no resource address\n", ecc_name);
..	..	@@ -2076,6 +1931,15 @@
2076	1931	goto err_release_group1;
2077	1932	}
2078	1933
	1934	+#ifdef CONFIG_ARCH_STRATIX10
	1935	+ /* Use IRQ to determine SError origin instead of assigning IRQ */
	1936	+ rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
	1937	+ if (rc) {
	1938	+ edac_printk(KERN_ERR, EDAC_DEVICE,
	1939	+ "Unable to parse DB IRQ index\n");
	1940	+ goto err_release_group1;
	1941	+ }
	1942	+#else
2079	1943	altdev->db_irq = irq_of_parse_and_map(np, 1);
2080	1944	if (!altdev->db_irq) {
2081	1945	edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
..	..	@@ -2089,6 +1953,7 @@
2089	1953	edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
2090	1954	goto err_release_group1;
2091	1955	}
	1956	+#endif
2092	1957
2093	1958	rc = edac_device_add_device(dci);
2094	1959	if (rc) {
..	..	@@ -2148,6 +2013,59 @@
2148	2013	.xlate = irq_domain_xlate_twocell,
2149	2014	};
2150	2015
	2016	+/************ Stratix 10 EDAC Double Bit Error Handler **********/
	2017	+#define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
	2018	+
	2019	+#ifdef CONFIG_ARCH_STRATIX10
	2020	+/* panic routine issues reboot on non-zero panic_timeout */
	2021	+extern int panic_timeout;
	2022	+
	2023	+/*
	2024	+ * The double bit error is handled through SError which is fatal. This is
	2025	+ * called as a panic notifier to printout ECC error info as part of the panic.
	2026	+ */
	2027	+static int s10_edac_dberr_handler(struct notifier_block *this,
	2028	+ unsigned long event, void *ptr)
	2029	+{
	2030	+ struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
	2031	+ int err_addr, dberror;
	2032	+
	2033	+ regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
	2034	+ &dberror);
	2035	+ regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
	2036	+ if (dberror & S10_DBE_IRQ_MASK) {
	2037	+ struct list_head *position;
	2038	+ struct altr_edac_device_dev *ed;
	2039	+ struct arm_smccc_res result;
	2040	+
	2041	+ /* Find the matching DBE in the list of devices */
	2042	+ list_for_each(position, &edac->a10_ecc_devices) {
	2043	+ ed = list_entry(position, struct altr_edac_device_dev,
	2044	+ next);
	2045	+ if (!(BIT(ed->db_irq) & dberror))
	2046	+ continue;
	2047	+
	2048	+ writel(ALTR_A10_ECC_DERRPENA,
	2049	+ ed->base + ALTR_A10_ECC_INTSTAT_OFST);
	2050	+ err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
	2051	+ regmap_write(edac->ecc_mgr_map,
	2052	+ S10_SYSMGR_UE_ADDR_OFST, err_addr);
	2053	+ edac_printk(KERN_ERR, EDAC_DEVICE,
	2054	+ "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
	2055	+ ed->edac_dev_name, err_addr);
	2056	+ break;
	2057	+ }
	2058	+ /* Notify the System through SMC. Reboot delay = 1 second */
	2059	+ panic_timeout = 1;
	2060	+ arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
	2061	+ 0, 0, &result);
	2062	+ }
	2063	+
	2064	+ return NOTIFY_DONE;
	2065	+}
	2066	+#endif
	2067	+
	2068	+/**************** Arria 10 EDAC Probe Function *******************/
2151	2069	static int altr_edac_a10_probe(struct platform_device *pdev)
2152	2070	{
2153	2071	struct altr_arria10_edac *edac;
..	..	@@ -2161,8 +2079,10 @@
2161	2079	platform_set_drvdata(pdev, edac);
2162	2080	INIT_LIST_HEAD(&edac->a10_ecc_devices);
2163	2081
2164		- edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2165		- "altr,sysmgr-syscon");
	2082	+ edac->ecc_mgr_map =
	2083	+ altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
	2084	+ "altr,sysmgr-syscon");
	2085	+
2166	2086	if (IS_ERR(edac->ecc_mgr_map)) {
2167	2087	edac_printk(KERN_ERR, EDAC_DEVICE,
2168	2088	"Unable to get syscon altr,sysmgr-syscon\n");
..	..	@@ -2189,34 +2109,53 @@
2189	2109	altr_edac_a10_irq_handler,
2190	2110	edac);
2191	2111
	2112	+#ifdef CONFIG_ARCH_STRATIX10
	2113	+ {
	2114	+ int dberror, err_addr;
	2115	+
	2116	+ edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
	2117	+ atomic_notifier_chain_register(&panic_notifier_list,
	2118	+ &edac->panic_notifier);
	2119	+
	2120	+ /* Printout a message if uncorrectable error previously. */
	2121	+ regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
	2122	+ &dberror);
	2123	+ if (dberror) {
	2124	+ regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
	2125	+ &err_addr);
	2126	+ edac_printk(KERN_ERR, EDAC_DEVICE,
	2127	+ "Previous Boot UE detected[0x%X] @ 0x%X\n",
	2128	+ dberror, err_addr);
	2129	+ /* Reset the sticky registers */
	2130	+ regmap_write(edac->ecc_mgr_map,
	2131	+ S10_SYSMGR_UE_VAL_OFST, 0);
	2132	+ regmap_write(edac->ecc_mgr_map,
	2133	+ S10_SYSMGR_UE_ADDR_OFST, 0);
	2134	+ }
	2135	+ }
	2136	+#else
2192	2137	edac->db_irq = platform_get_irq(pdev, 1);
2193	2138	if (edac->db_irq < 0) {
2194	2139	dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2195	2140	return edac->db_irq;
2196	2141	}
2197	2142	irq_set_chained_handler_and_data(edac->db_irq,
2198		- altr_edac_a10_irq_handler,
2199		- edac);
	2143	+ altr_edac_a10_irq_handler, edac);
	2144	+#endif
2200	2145
2201	2146	for_each_child_of_node(pdev->dev.of_node, child) {
2202	2147	if (!of_device_is_available(child))
2203	2148	continue;
2204	2149
2205		- if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") \|\|
2206		- of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") \|\|
2207		- of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") \|\|
2208		- of_device_is_compatible(child, "altr,socfpga-nand-ecc") \|\|
2209		- of_device_is_compatible(child, "altr,socfpga-dma-ecc") \|\|
2210		- of_device_is_compatible(child, "altr,socfpga-usb-ecc") \|\|
2211		- of_device_is_compatible(child, "altr,socfpga-qspi-ecc") \|\|
2212		- of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
2213		-
	2150	+ if (of_match_node(altr_edac_a10_device_of_match, child))
2214	2151	altr_edac_a10_device_add(edac, child);
2215	2152
	2153	+#ifdef CONFIG_EDAC_ALTERA_SDRAM
2216	2154	else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2217	2155	of_platform_populate(pdev->dev.of_node,
2218	2156	altr_sdram_ctrl_of_match,
2219	2157	NULL, &pdev->dev);
	2158	+#endif
2220	2159	}
2221	2160
2222	2161	return 0;
..	..	@@ -2224,6 +2163,7 @@
2224	2163
2225	2164	static const struct of_device_id altr_edac_a10_of_match[] = {
2226	2165	{ .compatible = "altr,socfpga-a10-ecc-manager" },
	2166	+ { .compatible = "altr,socfpga-s10-ecc-manager" },
2227	2167	{},
2228	2168	};
2229	2169	MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
..	..	@@ -2236,171 +2176,6 @@
2236	2176	},
2237	2177	};
2238	2178	module_platform_driver(altr_edac_a10_driver);
2239		-
2240		-/************ Stratix 10 EDAC Device Controller Functions> **********/
2241		-
2242		-#define to_s10edac(p, m) container_of(p, struct altr_stratix10_edac, m)
2243		-
2244		-/*
2245		- * The double bit error is handled through SError which is fatal. This is
2246		- * called as a panic notifier to printout ECC error info as part of the panic.
2247		- */
2248		-static int s10_edac_dberr_handler(struct notifier_block *this,
2249		- unsigned long event, void *ptr)
2250		-{
2251		- struct altr_stratix10_edac *edac = to_s10edac(this, panic_notifier);
2252		- int err_addr, dberror;
2253		-
2254		- s10_protected_reg_read(edac, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2255		- &dberror);
2256		- /* Remember the UE Errors for a reboot */
2257		- s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, dberror);
2258		- if (dberror & S10_DDR0_IRQ_MASK) {
2259		- s10_protected_reg_read(edac, S10_DERRADDR_OFST, &err_addr);
2260		- /* Remember the UE Error address */
2261		- s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST,
2262		- err_addr);
2263		- edac_printk(KERN_ERR, EDAC_MC,
2264		- "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
2265		- err_addr);
2266		- }
2267		-
2268		- return NOTIFY_DONE;
2269		-}
2270		-
2271		-static void altr_edac_s10_irq_handler(struct irq_desc *desc)
2272		-{
2273		- struct altr_stratix10_edac *edac = irq_desc_get_handler_data(desc);
2274		- struct irq_chip *chip = irq_desc_get_chip(desc);
2275		- int irq = irq_desc_get_irq(desc);
2276		- int bit, sm_offset, irq_status;
2277		-
2278		- sm_offset = S10_SYSMGR_ECC_INTSTAT_SERR_OFST;
2279		-
2280		- chained_irq_enter(chip, desc);
2281		-
2282		- s10_protected_reg_read(NULL, sm_offset, &irq_status);
2283		-
2284		- for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
2285		- irq = irq_linear_revmap(edac->domain, bit);
2286		- if (irq)
2287		- generic_handle_irq(irq);
2288		- }
2289		-
2290		- chained_irq_exit(chip, desc);
2291		-}
2292		-
2293		-static void s10_eccmgr_irq_mask(struct irq_data *d)
2294		-{
2295		- struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
2296		-
2297		- s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_SET_OFST,
2298		- BIT(d->hwirq));
2299		-}
2300		-
2301		-static void s10_eccmgr_irq_unmask(struct irq_data *d)
2302		-{
2303		- struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
2304		-
2305		- s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
2306		- BIT(d->hwirq));
2307		-}
2308		-
2309		-static int s10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2310		- irq_hw_number_t hwirq)
2311		-{
2312		- struct altr_stratix10_edac *edac = d->host_data;
2313		-
2314		- irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2315		- irq_set_chip_data(irq, edac);
2316		- irq_set_noprobe(irq);
2317		-
2318		- return 0;
2319		-}
2320		-
2321		-static const struct irq_domain_ops s10_eccmgr_ic_ops = {
2322		- .map = s10_eccmgr_irqdomain_map,
2323		- .xlate = irq_domain_xlate_twocell,
2324		-};
2325		-
2326		-static int altr_edac_s10_probe(struct platform_device *pdev)
2327		-{
2328		- struct altr_stratix10_edac *edac;
2329		- struct device_node *child;
2330		- int dberror, err_addr;
2331		-
2332		- edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2333		- if (!edac)
2334		- return -ENOMEM;
2335		-
2336		- edac->dev = &pdev->dev;
2337		- platform_set_drvdata(pdev, edac);
2338		- INIT_LIST_HEAD(&edac->s10_ecc_devices);
2339		-
2340		- edac->irq_chip.name = pdev->dev.of_node->name;
2341		- edac->irq_chip.irq_mask = s10_eccmgr_irq_mask;
2342		- edac->irq_chip.irq_unmask = s10_eccmgr_irq_unmask;
2343		- edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2344		- &s10_eccmgr_ic_ops, edac);
2345		- if (!edac->domain) {
2346		- dev_err(&pdev->dev, "Error adding IRQ domain\n");
2347		- return -ENOMEM;
2348		- }
2349		-
2350		- edac->sb_irq = platform_get_irq(pdev, 0);
2351		- if (edac->sb_irq < 0) {
2352		- dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2353		- return edac->sb_irq;
2354		- }
2355		-
2356		- irq_set_chained_handler_and_data(edac->sb_irq,
2357		- altr_edac_s10_irq_handler,
2358		- edac);
2359		-
2360		- edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2361		- atomic_notifier_chain_register(&panic_notifier_list,
2362		- &edac->panic_notifier);
2363		-
2364		- /* Printout a message if uncorrectable error previously. */
2365		- s10_protected_reg_read(edac, S10_SYSMGR_UE_VAL_OFST, &dberror);
2366		- if (dberror) {
2367		- s10_protected_reg_read(edac, S10_SYSMGR_UE_ADDR_OFST,
2368		- &err_addr);
2369		- edac_printk(KERN_ERR, EDAC_DEVICE,
2370		- "Previous Boot UE detected[0x%X] @ 0x%X\n",
2371		- dberror, err_addr);
2372		- /* Reset the sticky registers */
2373		- s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, 0);
2374		- s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST, 0);
2375		- }
2376		-
2377		- for_each_child_of_node(pdev->dev.of_node, child) {
2378		- if (!of_device_is_available(child))
2379		- continue;
2380		-
2381		- if (of_device_is_compatible(child, "altr,sdram-edac-s10"))
2382		- of_platform_populate(pdev->dev.of_node,
2383		- altr_sdram_ctrl_of_match,
2384		- NULL, &pdev->dev);
2385		- }
2386		-
2387		- return 0;
2388		-}
2389		-
2390		-static const struct of_device_id altr_edac_s10_of_match[] = {
2391		- { .compatible = "altr,socfpga-s10-ecc-manager" },
2392		- {},
2393		-};
2394		-MODULE_DEVICE_TABLE(of, altr_edac_s10_of_match);
2395		-
2396		-static struct platform_driver altr_edac_s10_driver = {
2397		- .probe = altr_edac_s10_probe,
2398		- .driver = {
2399		- .name = "socfpga_s10_ecc_manager",
2400		- .of_match_table = altr_edac_s10_of_match,
2401		- },
2402		-};
2403		-module_platform_driver(altr_edac_s10_driver);
2404	2179
2405	2180	MODULE_LICENSE("GPL v2");
2406	2181	MODULE_AUTHOR("Thor Thayer");