| .. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ |
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| 1 | 2 | /* |
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| 2 | 3 | * Driver for the Synopsys DesignWare AHB DMA Controller |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2005-2007 Atmel Corporation |
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| 5 | 6 | * Copyright (C) 2010-2011 ST Microelectronics |
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| 6 | 7 | * Copyright (C) 2016 Intel Corporation |
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| 7 | | - * |
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| 8 | | - * This program is free software; you can redistribute it and/or modify |
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| 9 | | - * it under the terms of the GNU General Public License version 2 as |
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| 10 | | - * published by the Free Software Foundation. |
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| 11 | 8 | */ |
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| 12 | 9 | |
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| 13 | 10 | #include <linux/bitops.h> |
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| .. | .. |
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| 128 | 125 | |
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| 129 | 126 | /* Bitfields in DWC_PARAMS */ |
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| 130 | 127 | #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */ |
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| 128 | +#define DWC_PARAMS_HC_LLP 13 /* set LLP register to zero */ |
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| 129 | +#define DWC_PARAMS_MSIZE 16 /* max group transaction size */ |
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| 131 | 130 | |
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| 132 | 131 | /* bursts size */ |
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| 133 | 132 | enum dw_dma_msize { |
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| .. | .. |
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| 222 | 221 | |
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| 223 | 222 | /* iDMA 32-bit support */ |
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| 224 | 223 | |
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| 224 | +/* bursts size */ |
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| 225 | +enum idma32_msize { |
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| 226 | + IDMA32_MSIZE_1, |
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| 227 | + IDMA32_MSIZE_2, |
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| 228 | + IDMA32_MSIZE_4, |
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| 229 | + IDMA32_MSIZE_8, |
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| 230 | + IDMA32_MSIZE_16, |
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| 231 | + IDMA32_MSIZE_32, |
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| 232 | +}; |
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| 233 | + |
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| 225 | 234 | /* Bitfields in CTL_HI */ |
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| 226 | 235 | #define IDMA32C_CTLH_BLOCK_TS_MASK GENMASK(16, 0) |
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| 227 | 236 | #define IDMA32C_CTLH_BLOCK_TS(x) ((x) & IDMA32C_CTLH_BLOCK_TS_MASK) |
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| .. | .. |
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| 276 | 285 | /* hardware configuration */ |
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| 277 | 286 | unsigned int block_size; |
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| 278 | 287 | bool nollp; |
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| 288 | + u32 max_burst; |
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| 279 | 289 | |
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| 280 | 290 | /* custom slave configuration */ |
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| 281 | 291 | struct dw_dma_slave dws; |
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| .. | .. |
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| 312 | 322 | u8 all_chan_mask; |
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| 313 | 323 | u8 in_use; |
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| 314 | 324 | |
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| 325 | + /* Channel operations */ |
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| 326 | + void (*initialize_chan)(struct dw_dma_chan *dwc); |
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| 327 | + void (*suspend_chan)(struct dw_dma_chan *dwc, bool drain); |
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| 328 | + void (*resume_chan)(struct dw_dma_chan *dwc, bool drain); |
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| 329 | + u32 (*prepare_ctllo)(struct dw_dma_chan *dwc); |
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| 330 | + void (*encode_maxburst)(struct dw_dma_chan *dwc, u32 *maxburst); |
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| 331 | + u32 (*bytes2block)(struct dw_dma_chan *dwc, size_t bytes, |
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| 332 | + unsigned int width, size_t *len); |
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| 333 | + size_t (*block2bytes)(struct dw_dma_chan *dwc, u32 block, u32 width); |
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| 334 | + |
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| 335 | + /* Device operations */ |
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| 336 | + void (*set_device_name)(struct dw_dma *dw, int id); |
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| 337 | + void (*disable)(struct dw_dma *dw); |
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| 338 | + void (*enable)(struct dw_dma *dw); |
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| 339 | + |
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| 315 | 340 | /* platform data */ |
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| 316 | 341 | struct dw_dma_platform_data *pdata; |
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| 317 | 342 | }; |
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