enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/clk/socfpga/clk-pll.c
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@@ -1,19 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *  Copyright 2011-2012 Calxeda, Inc.
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  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
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  *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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  * Based from clk-highbank.c
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- *
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  */
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 #include <linux/slab.h>
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 #include <linux/clk-provider.h>
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@@ -75,7 +65,7 @@
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 			CLK_MGR_PLL_CLK_SRC_MASK;
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 }
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-static struct clk_ops clk_pll_ops = {
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+static const struct clk_ops clk_pll_ops = {
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 	.recalc_rate = clk_pll_recalc_rate,
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 	.get_parent = clk_pll_get_parent,
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 };
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@@ -88,7 +78,7 @@
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 	struct socfpga_pll *pll_clk;
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 	const char *clk_name = node->name;
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 	const char *parent_name[SOCFPGA_MAX_PARENTS];
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	struct device_node *clkmgr_np;
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 	int rc;
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@@ -115,8 +105,6 @@
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 	pll_clk->hw.hw.init = &init;
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 	pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
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-	clk_pll_ops.enable = clk_gate_ops.enable;
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-	clk_pll_ops.disable = clk_gate_ops.disable;
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 	clk = clk_register(NULL, &pll_clk->hw.hw);
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 	if (WARN_ON(IS_ERR(clk))) {