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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/drivers/clk/rockchip/clk.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23  * Copyright (c) 2014 MundoReader S.L.
34  * Author: Heiko Stuebner <heiko@sntech.de>
....@@ -11,16 +12,6 @@
1112  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
1213  * Copyright (c) 2013 Linaro Ltd.
1314  * Author: Thomas Abraham <thomas.ab@samsung.com>
14
- *
15
- * This program is free software; you can redistribute it and/or modify
16
- * it under the terms of the GNU General Public License as published by
17
- * the Free Software Foundation; either version 2 of the License, or
18
- * (at your option) any later version.
19
- *
20
- * This program is distributed in the hope that it will be useful,
21
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
22
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23
- * GNU General Public License for more details.
2415  */
2516 
2617 #ifndef CLK_ROCKCHIP_CLK_H
....@@ -86,6 +77,64 @@
8677 #define PX30_PMU_CLKSEL_CON(x)		((x) * 0x4 + 0x40)
8778 #define PX30_PMU_CLKGATE_CON(x)		((x) * 0x4 + 0x80)
8879 #define PX30_PMU_MODE			0x0020
80
+
81
+#define RV1106_TOPCRU_BASE		0x10000
82
+#define RV1106_PERICRU_BASE		0x12000
83
+#define RV1106_VICRU_BASE		0x14000
84
+#define RV1106_NPUCRU_BASE		0x16000
85
+#define RV1106_CORECRU_BASE		0x18000
86
+#define RV1106_VEPUCRU_BASE		0x1A000
87
+#define RV1106_VOCRU_BASE		0x1C000
88
+#define RV1106_DDRCRU_BASE		0x1E000
89
+#define RV1106_SUBDDRCRU_BASE		0x1F000
90
+
91
+#define RV1106_VI_GRF_BASE		0x50000
92
+#define RV1106_VO_GRF_BASE		0x60000
93
+
94
+#define RV1106_PMUCLKSEL_CON(x)		((x) * 0x4 + 0x300)
95
+#define RV1106_PMUCLKGATE_CON(x)	((x) * 0x4 + 0x800)
96
+#define RV1106_PMUSOFTRST_CON(x)	((x) * 0x4 + 0xa00)
97
+#define RV1106_PLL_CON(x)		((x) * 0x4 + RV1106_TOPCRU_BASE)
98
+#define RV1106_MODE_CON			(0x280 + RV1106_TOPCRU_BASE)
99
+#define RV1106_CLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_TOPCRU_BASE)
100
+#define RV1106_CLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_TOPCRU_BASE)
101
+#define RV1106_SOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_TOPCRU_BASE)
102
+#define RV1106_GLB_SRST_FST		(0xc08 + RV1106_TOPCRU_BASE)
103
+#define RV1106_GLB_SRST_SND		(0xc0c + RV1106_TOPCRU_BASE)
104
+#define RV1106_SDIO_CON0		(0x1c + RV1106_VO_GRF_BASE)
105
+#define RV1106_SDIO_CON1		(0x20 + RV1106_VO_GRF_BASE)
106
+#define RV1106_SDMMC_CON0		(0x4 + RV1106_VI_GRF_BASE)
107
+#define RV1106_SDMMC_CON1		(0x8 + RV1106_VI_GRF_BASE)
108
+#define RV1106_EMMC_CON0		(0x20)
109
+#define RV1106_EMMC_CON1		(0x24)
110
+#define RV1106_PERICLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_PERICRU_BASE)
111
+#define RV1106_PERICLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_PERICRU_BASE)
112
+#define RV1106_PERISOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_PERICRU_BASE)
113
+#define RV1106_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
114
+#define RV1106_VICLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
115
+#define RV1106_VISOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
116
+#define RV1106_VICLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VICRU_BASE)
117
+#define RV1106_VICLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VICRU_BASE)
118
+#define RV1106_VISOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_VICRU_BASE)
119
+#define RV1106_NPUCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_NPUCRU_BASE)
120
+#define RV1106_NPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_NPUCRU_BASE)
121
+#define RV1106_NPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_NPUCRU_BASE)
122
+#define RV1106_CORECLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_CORECRU_BASE)
123
+#define RV1106_CORECLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_CORECRU_BASE)
124
+#define RV1106_CORESOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_CORECRU_BASE)
125
+#define RV1106_VEPUCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_VEPUCRU_BASE)
126
+#define RV1106_VEPUCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_VEPUCRU_BASE)
127
+#define RV1106_VEPUSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_VEPUCRU_BASE)
128
+#define RV1106_VOCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_VOCRU_BASE)
129
+#define RV1106_VOCLKGATE_CON(x)		((x) * 0x4 + 0x800 + RV1106_VOCRU_BASE)
130
+#define RV1106_VOSOFTRST_CON(x)		((x) * 0x4 + 0xa00 + RV1106_VOCRU_BASE)
131
+#define RV1106_DDRCLKSEL_CON(x)		((x) * 0x4 + 0x300 + RV1106_DDRCRU_BASE)
132
+#define RV1106_DDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_DDRCRU_BASE)
133
+#define RV1106_DDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_DDRCRU_BASE)
134
+#define RV1106_SUBDDRCLKSEL_CON(x)	((x) * 0x4 + 0x300 + RV1106_SUBDDRCRU_BASE)
135
+#define RV1106_SUBDDRCLKGATE_CON(x)	((x) * 0x4 + 0x800 + RV1106_SUBDDRCRU_BASE)
136
+#define RV1106_SUBDDRSOFTRST_CON(x)	((x) * 0x4 + 0xa00 + RV1106_SUBDDRCRU_BASE)
137
+#define RV1106_SUBDDRMODE_CON		(0x280 + RV1106_SUBDDRCRU_BASE)
89138 
90139 #define RV1108_PLL_CON(x)		((x) * 0x4)
91140 #define RV1108_CLKSEL_CON(x)		((x) * 0x4 + 0x60)
....@@ -283,6 +332,45 @@
283332 #define RK3528_GLB_SRST_FST		0xc08
284333 #define RK3528_GLB_SRST_SND		0xc0c
285334 
335
+#define RK3562_PMU0_CRU_BASE		0x10000
336
+#define RK3562_PMU1_CRU_BASE		0x18000
337
+#define RK3562_DDR_CRU_BASE		0x20000
338
+#define RK3562_SUBDDR_CRU_BASE		0x28000
339
+#define RK3562_PERI_CRU_BASE		0x30000
340
+
341
+#define RK3562_PLL_CON(x)		RK2928_PLL_CON(x)
342
+#define RK3562_PMU1_PLL_CON(x)		((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
343
+#define RK3562_SUBDDR_PLL_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
344
+#define RK3562_MODE_CON			0x600
345
+#define RK3562_PMU1_MODE_CON		(RK3562_PMU1_CRU_BASE + 0x380)
346
+#define RK3562_SUBDDR_MODE_CON		(RK3562_SUBDDR_CRU_BASE + 0x380)
347
+#define RK3562_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
348
+#define RK3562_CLKGATE_CON(x)		((x) * 0x4 + 0x300)
349
+#define RK3562_SOFTRST_CON(x)		((x) * 0x4 + 0x400)
350
+#define RK3562_DDR_CLKSEL_CON(x)	((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
351
+#define RK3562_DDR_CLKGATE_CON(x)	((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
352
+#define RK3562_DDR_SOFTRST_CON(x)	((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
353
+#define RK3562_SUBDDR_CLKSEL_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
354
+#define RK3562_SUBDDR_CLKGATE_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
355
+#define RK3562_SUBDDR_SOFTRST_CON(x)	((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
356
+#define RK3562_PERI_CLKSEL_CON(x)	((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
357
+#define RK3562_PERI_CLKGATE_CON(x)	((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
358
+#define RK3562_PERI_SOFTRST_CON(x)	((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
359
+#define RK3562_PMU0_CLKSEL_CON(x)	((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
360
+#define RK3562_PMU0_CLKGATE_CON(x)	((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
361
+#define RK3562_PMU0_SOFTRST_CON(x)	((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
362
+#define RK3562_PMU1_CLKSEL_CON(x)	((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
363
+#define RK3562_PMU1_CLKGATE_CON(x)	((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
364
+#define RK3562_PMU1_SOFTRST_CON(x)	((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
365
+#define RK3562_GLB_SRST_FST		0x614
366
+#define RK3562_GLB_SRST_SND		0x618
367
+#define RK3562_GLB_RST_CON		0x61c
368
+#define RK3562_GLB_RST_ST		0x620
369
+#define RK3562_SDMMC0_CON0		0x624
370
+#define RK3562_SDMMC0_CON1		0x628
371
+#define RK3562_SDMMC1_CON0		0x62c
372
+#define RK3562_SDMMC1_CON1		0x630
373
+
286374 #define RK3568_PLL_CON(x)		RK2928_PLL_CON(x)
287375 #define RK3568_MODE_CON0		0xc0
288376 #define RK3568_MISC_CON0		0xc4
....@@ -311,11 +399,58 @@
311399 #define RK3568_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x180)
312400 #define RK3568_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x200)
313401 
402
+#define RK3588_PHP_CRU_BASE		0x8000
403
+#define RK3588_PMU_CRU_BASE		0x30000
404
+#define RK3588_BIGCORE0_CRU_BASE	0x50000
405
+#define RK3588_BIGCORE1_CRU_BASE	0x52000
406
+#define RK3588_DSU_CRU_BASE		0x58000
407
+
408
+#define RK3588_PLL_CON(x)		RK2928_PLL_CON(x)
409
+#define RK3588_MODE_CON0		0x280
410
+#define RK3588_B0_PLL_MODE_CON0		(RK3588_BIGCORE0_CRU_BASE + 0x280)
411
+#define RK3588_B1_PLL_MODE_CON0		(RK3588_BIGCORE1_CRU_BASE + 0x280)
412
+#define RK3588_LPLL_MODE_CON0		(RK3588_DSU_CRU_BASE + 0x280)
413
+#define RK3588_CLKSEL_CON(x)		((x) * 0x4 + 0x300)
414
+#define RK3588_CLKGATE_CON(x)		((x) * 0x4 + 0x800)
415
+#define RK3588_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)
416
+#define RK3588_GLB_CNT_TH		0xc00
417
+#define RK3588_GLB_SRST_FST		0xc08
418
+#define RK3588_GLB_SRST_SND		0xc0c
419
+#define RK3588_GLB_RST_CON		0xc10
420
+#define RK3588_GLB_RST_ST		0xc04
421
+#define RK3588_SDIO_CON0		0xC24
422
+#define RK3588_SDIO_CON1		0xC28
423
+#define RK3588_SDMMC_CON0		0xC30
424
+#define RK3588_SDMMC_CON1		0xC34
425
+
426
+#define RK3588_PHP_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
427
+#define RK3588_PHP_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
428
+
429
+#define RK3588_PMU_PLL_CON(x)		((x) * 0x4 + RK3588_PHP_CRU_BASE)
430
+#define RK3588_PMU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
431
+#define RK3588_PMU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
432
+#define RK3588_PMU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
433
+
434
+#define RK3588_B0_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
435
+#define RK3588_BIGCORE0_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
436
+#define RK3588_BIGCORE0_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
437
+#define RK3588_BIGCORE0_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
438
+#define RK3588_B1_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
439
+#define RK3588_BIGCORE1_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
440
+#define RK3588_BIGCORE1_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
441
+#define RK3588_BIGCORE1_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
442
+#define RK3588_LPLL_CON(x)		((x) * 0x4 + RK3588_DSU_CRU_BASE)
443
+#define RK3588_DSU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
444
+#define RK3588_DSU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
445
+#define RK3588_DSU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
446
+
314447 enum rockchip_pll_type {
315448 	pll_rk3036,
316449 	pll_rk3066,
317450 	pll_rk3328,
318451 	pll_rk3399,
452
+	pll_rk3588,
453
+	pll_rk3588_core,
319454 };
320455 
321456 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,	\
....@@ -346,6 +481,15 @@
346481 	.nf = _nf,						\
347482 	.no = _no,						\
348483 	.nb = _nb,						\
484
+}
485
+
486
+#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k)			\
487
+{								\
488
+	.rate	= _rate##U,					\
489
+	.p = _p,						\
490
+	.m = _m,						\
491
+	.s = _s,						\
492
+	.k = _k,						\
349493 }
350494 
351495 /**
....@@ -383,6 +527,13 @@
383527 			unsigned int postdiv2;
384528 			unsigned int dsmpd;
385529 			unsigned int frac;
530
+		};
531
+		struct {
532
+			/* for RK3588 */
533
+			unsigned int m;
534
+			unsigned int p;
535
+			unsigned int s;
536
+			unsigned int k;
386537 		};
387538 	};
388539 };
....@@ -427,6 +578,7 @@
427578 #define ROCKCHIP_PLL_SYNC_RATE		BIT(0)
428579 /* normal mode only. now only for pll_rk3036, pll_rk3328 type */
429580 #define ROCKCHIP_PLL_FIXED_MODE		BIT(1)
581
+#define ROCKCHIP_PLL_ALLOW_POWER_DOWN	BIT(2)
430582 
431583 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift,	\
432584 		_lshift, _pflags, _rtable)				\
....@@ -466,7 +618,7 @@
466618 	u32 val;
467619 };
468620 
469
-#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	5
621
+#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	6
470622 #define ROCKCHIP_CPUCLK_MAX_CORES	4
471623 struct rockchip_cpuclk_rate_table {
472624 	unsigned long prate;
....@@ -481,6 +633,7 @@
481633  * @div_core_shift[]:	cores divider offset used to divide the pll value
482634  * @div_core_mask[]:	cores divider mask
483635  * @num_cores:	number of cpu cores
636
+ * @mux_core_reg:       register offset of the cores select parent
484637  * @mux_core_alt:       mux value to select alternate parent
485638  * @mux_core_main:	mux value to select main parent of core
486639  * @mux_core_shift:	offset of the core multiplexer
....@@ -491,6 +644,7 @@
491644 	u8	div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
492645 	u32	div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
493646 	int	num_cores;
647
+	int	mux_core_reg;
494648 	u8	mux_core_alt;
495649 	u8	mux_core_main;
496650 	u8	mux_core_shift;
....@@ -499,10 +653,22 @@
499653 };
500654 
501655 struct clk *rockchip_clk_register_cpuclk(const char *name,
502
-			const char *const *parent_names, u8 num_parents,
656
+			u8 num_parents,
657
+			struct clk *parent, struct clk *alt_parent,
503658 			const struct rockchip_cpuclk_reg_data *reg_data,
504659 			const struct rockchip_cpuclk_rate_table *rates,
505660 			int nrates, void __iomem *reg_base, spinlock_t *lock);
661
+
662
+struct clk *rockchip_clk_register_cpuclk_v2(const char *name,
663
+					    const char *const *parent_names,
664
+					    u8 num_parents, void __iomem *base,
665
+					    int muxdiv_offset, u8 mux_shift,
666
+					    u8 mux_width, u8 mux_flags,
667
+					    int div_offset, u8 div_shift,
668
+					    u8 div_width, u8 div_flags,
669
+					    unsigned long flags, spinlock_t *lock,
670
+					    const struct rockchip_cpuclk_rate_table *rates,
671
+					    int nrates);
506672 
507673 struct clk *rockchip_clk_register_mmc(const char *name,
508674 				const char *const *parent_names, u8 num_parents,
....@@ -511,11 +677,13 @@
511677 /*
512678  * DDRCLK flags, including method of setting the rate
513679  * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
514
- * ROCKCHIP_DDRCLK_SCPI: use SCPI APIs to let mcu change ddrclk rate.
515680  */
516681 #define ROCKCHIP_DDRCLK_SIP		BIT(0)
517
-#define ROCKCHIP_DDRCLK_SCPI		0x02
518682 #define ROCKCHIP_DDRCLK_SIP_V2		0x03
683
+
684
+#ifdef CONFIG_ROCKCHIP_DDRCLK
685
+void rockchip_set_ddrclk_params(void __iomem *params);
686
+void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void));
519687 
520688 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
521689 					 const char *const *parent_names,
....@@ -523,6 +691,20 @@
523691 					 int mux_shift, int mux_width,
524692 					 int div_shift, int div_width,
525693 					 int ddr_flags, void __iomem *reg_base);
694
+#else
695
+static inline void rockchip_set_ddrclk_params(void __iomem *params) {}
696
+static inline void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void)) {}
697
+static inline
698
+struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
699
+					 const char *const *parent_names,
700
+					 u8 num_parents, int mux_offset,
701
+					 int mux_shift, int mux_width,
702
+					 int div_shift, int div_width,
703
+					 int ddr_flags, void __iomem *reg_base)
704
+{
705
+	return NULL;
706
+}
707
+#endif
526708 
527709 #define ROCKCHIP_INVERTER_HIWORD_MASK	BIT(0)
528710 
....@@ -540,19 +722,18 @@
540722 
541723 enum rockchip_clk_branch_type {
542724 	branch_composite,
543
-	branch_composite_brother,
544725 	branch_mux,
545726 	branch_muxgrf,
546727 	branch_muxpmugrf,
547728 	branch_divider,
548729 	branch_fraction_divider,
549730 	branch_gate,
731
+	branch_gate_no_set_rate,
550732 	branch_mmc,
551733 	branch_inverter,
552734 	branch_factor,
553735 	branch_ddrclk,
554736 	branch_half_divider,
555
-	branch_dclk_divider,
556737 };
557738 
558739 struct rockchip_clk_branch {
....@@ -576,7 +757,6 @@
576757 	u8				gate_shift;
577758 	u8				gate_flags;
578759 	struct rockchip_clk_branch	*child;
579
-	unsigned long			max_prate;
580760 };
581761 
582762 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
....@@ -598,28 +778,6 @@
598778 		.gate_offset	= go,				\
599779 		.gate_shift	= gs,				\
600780 		.gate_flags	= gf,				\
601
-	}
602
-
603
-#define COMPOSITE_BROTHER(_id, cname, pnames, f, mo, ms, mw, mf,\
604
-			  ds, dw, df, go, gs, gf, bro)		\
605
-	{							\
606
-		.id		= _id,				\
607
-		.branch_type	= branch_composite_brother,	\
608
-		.name		= cname,			\
609
-		.parent_names	= pnames,			\
610
-		.num_parents	= ARRAY_SIZE(pnames),		\
611
-		.flags		= f,				\
612
-		.muxdiv_offset	= mo,				\
613
-		.mux_shift	= ms,				\
614
-		.mux_width	= mw,				\
615
-		.mux_flags	= mf,				\
616
-		.div_shift	= ds,				\
617
-		.div_width	= dw,				\
618
-		.div_flags	= df,				\
619
-		.gate_offset	= go,				\
620
-		.gate_shift	= gs,				\
621
-		.gate_flags	= gf,				\
622
-		.child		= bro,				\
623781 	}
624782 
625783 #define COMPOSITE_MUXTBL(_id, cname, pnames, f, mo, ms, mw, mf,	\
....@@ -740,26 +898,6 @@
740898 		.gate_offset	= -1,				\
741899 	}
742900 
743
-#define COMPOSITE_BROTHER_NOGATE(_id, cname, pnames, f, mo, ms, \
744
-				 mw, mf, ds, dw, df, bro)	\
745
-	{							\
746
-		.id		= _id,				\
747
-		.branch_type	= branch_composite_brother,	\
748
-		.name		= cname,			\
749
-		.parent_names	= pnames,			\
750
-		.num_parents	= ARRAY_SIZE(pnames),		\
751
-		.flags		= f,				\
752
-		.muxdiv_offset	= mo,				\
753
-		.mux_shift	= ms,				\
754
-		.mux_width	= mw,				\
755
-		.mux_flags	= mf,				\
756
-		.div_shift	= ds,				\
757
-		.div_width	= dw,				\
758
-		.div_flags	= df,				\
759
-		.gate_offset	= -1,				\
760
-		.child		= bro,				\
761
-	}
762
-
763901 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms,	\
764902 				mw, mf, ds, dw, df, dt)		\
765903 	{							\
....@@ -780,7 +918,7 @@
780918 		.gate_offset	= -1,				\
781919 	}
782920 
783
-#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf, prate)\
921
+#define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
784922 	{							\
785923 		.id		= _id,				\
786924 		.branch_type	= branch_fraction_divider,	\
....@@ -795,10 +933,9 @@
795933 		.gate_offset	= go,				\
796934 		.gate_shift	= gs,				\
797935 		.gate_flags	= gf,				\
798
-		.max_prate	= prate,			\
799936 	}
800937 
801
-#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch, prate) \
938
+#define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
802939 	{							\
803940 		.id		= _id,				\
804941 		.branch_type	= branch_fraction_divider,	\
....@@ -814,10 +951,9 @@
814951 		.gate_shift	= gs,				\
815952 		.gate_flags	= gf,				\
816953 		.child		= ch,				\
817
-		.max_prate	= prate,			\
818954 	}
819955 
820
-#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch, prate) \
956
+#define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
821957 	{							\
822958 		.id		= _id,				\
823959 		.branch_type	= branch_fraction_divider,	\
....@@ -831,7 +967,6 @@
831967 		.div_flags	= df,				\
832968 		.gate_offset	= -1,				\
833969 		.child		= ch,				\
834
-		.max_prate	= prate,			\
835970 	}
836971 
837972 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw,	\
....@@ -947,6 +1082,19 @@
9471082 	{							\
9481083 		.id		= _id,				\
9491084 		.branch_type	= branch_gate,			\
1085
+		.name		= cname,			\
1086
+		.parent_names	= (const char *[]){ pname },	\
1087
+		.num_parents	= 1,				\
1088
+		.flags		= f,				\
1089
+		.gate_offset	= o,				\
1090
+		.gate_shift	= b,				\
1091
+		.gate_flags	= gf,				\
1092
+	}
1093
+
1094
+#define GATE_NO_SET_RATE(_id, cname, pname, f, o, b, gf)	\
1095
+	{							\
1096
+		.id		= _id,				\
1097
+		.branch_type	= branch_gate_no_set_rate,	\
9501098 		.name		= cname,			\
9511099 		.parent_names	= (const char *[]){ pname },	\
9521100 		.num_parents	= 1,				\
....@@ -1101,28 +1249,6 @@
11011249 		.gate_offset	= -1,				\
11021250 	}
11031251 
1104
-#define COMPOSITE_DCLK(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
1105
-		  df, go, gs, gf, prate)				\
1106
-	{							\
1107
-		.id		= _id,				\
1108
-		.branch_type	= branch_dclk_divider,		\
1109
-		.name		= cname,			\
1110
-		.parent_names	= pnames,			\
1111
-		.num_parents	= ARRAY_SIZE(pnames),		\
1112
-		.flags		= f,				\
1113
-		.muxdiv_offset	= mo,				\
1114
-		.mux_shift	= ms,				\
1115
-		.mux_width	= mw,				\
1116
-		.mux_flags	= mf,				\
1117
-		.div_shift	= ds,				\
1118
-		.div_width	= dw,				\
1119
-		.div_flags	= df,				\
1120
-		.gate_offset	= go,				\
1121
-		.gate_shift	= gs,				\
1122
-		.gate_flags	= gf,				\
1123
-		.max_prate	= prate,				\
1124
-	}
1125
-
11261252 /* SGRF clocks are only accessible from secure mode, so not controllable */
11271253 #define SGRF_GATE(_id, cname, pname)				\
11281254 		FACTOR(_id, cname, pname, 0, 1, 1)
....@@ -1140,12 +1266,17 @@
11401266 				struct rockchip_pll_clock *pll_list,
11411267 				unsigned int nr_pll, int grf_lock_offset);
11421268 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
1143
-			unsigned int lookup_id, const char *name,
1144
-			const char *const *parent_names, u8 num_parents,
1145
-			const struct rockchip_cpuclk_reg_data *reg_data,
1146
-			const struct rockchip_cpuclk_rate_table *rates,
1147
-			int nrates);
1148
-void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
1269
+				  unsigned int lookup_id,
1270
+				  const char *name,
1271
+				  u8 num_parents,
1272
+				  struct clk *parent, struct clk *alt_parent,
1273
+				  const struct rockchip_cpuclk_reg_data *reg_data,
1274
+				  const struct rockchip_cpuclk_rate_table *rates,
1275
+				  int nrates);
1276
+void rockchip_clk_register_armclk_v2(struct rockchip_clk_provider *ctx,
1277
+				     struct rockchip_clk_branch *list,
1278
+				     const struct rockchip_cpuclk_rate_table *rates,
1279
+				     int nrates);
11491280 int rockchip_pll_clk_rate_to_scale(struct clk *clk, unsigned long rate);
11501281 int rockchip_pll_clk_scale_to_rate(struct clk *clk, unsigned int scale);
11511282 int rockchip_pll_clk_adaptive_scaling(struct clk *clk, int sel);
....@@ -1165,21 +1296,6 @@
11651296 					  u8 gate_flags, unsigned long flags,
11661297 					  spinlock_t *lock);
11671298 
1168
-struct clk *rockchip_clk_register_dclk_branch(const char *name,
1169
-					      const char *const *parent_names,
1170
-					      u8 num_parents,
1171
-					      void __iomem *base,
1172
-					      int muxdiv_offset, u8 mux_shift,
1173
-					      u8 mux_width, u8 mux_flags,
1174
-					      int div_offset, u8 div_shift,
1175
-					      u8 div_width, u8 div_flags,
1176
-					      struct clk_div_table *div_table,
1177
-					      int gate_offset,
1178
-					      u8 gate_shift, u8 gate_flags,
1179
-					      unsigned long flags,
1180
-					      unsigned long max_prate,
1181
-					      spinlock_t *lock);
1182
-
11831299 #ifdef CONFIG_RESET_CONTROLLER
11841300 void rockchip_register_softrst(struct device_node *np,
11851301 			       unsigned int num_regs,
....@@ -1193,4 +1309,20 @@
11931309 #endif
11941310 extern void (*rk_dump_cru)(void);
11951311 
1312
+#if IS_MODULE(CONFIG_COMMON_CLK_ROCKCHIP)
1313
+int rockchip_clk_protect(struct rockchip_clk_provider *ctx,
1314
+			 unsigned int *clocks, unsigned int nclocks);
1315
+void rockchip_clk_unprotect(void);
1316
+#else
1317
+static inline int rockchip_clk_protect(struct rockchip_clk_provider *ctx,
1318
+				       unsigned int *clocks,
1319
+				       unsigned int nclocks)
1320
+{
1321
+	return -EOPNOTSUPP;
1322
+}
1323
+
1324
+static inline void rockchip_clk_unprotect(void)
1325
+{
1326
+}
1327
+#endif
11961328 #endif