enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/clk/imx/clk.h
..
..
@@ -2,13 +2,26 @@
2
2
 #ifndef __MACH_IMX_CLK_H
3
3
 #define __MACH_IMX_CLK_H
4
4
 
5
+#include <linux/bits.h>
5
6
 #include <linux/spinlock.h>
6
7
 #include <linux/clk-provider.h>
8
+
9
+#define IMX_CLK_GATE2_SINGLE_BIT	1
7
10
 
8
11
 extern spinlock_t imx_ccm_lock;
9
12
 
10
13
 void imx_check_clocks(struct clk *clks[], unsigned int count);
11
-void imx_register_uart_clocks(struct clk ** const clks[]);
14
+void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
15
+#ifndef MODULE
16
+void imx_register_uart_clocks(unsigned int clk_count);
17
+#else
18
+static inline void imx_register_uart_clocks(unsigned int clk_count)
19
+{
20
+}
21
+#endif
22
+void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
23
+void imx_unregister_clocks(struct clk *clks[], unsigned int count);
24
+void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
12
25
 
13
26
 extern void imx_cscmr1_fixup(u32 *val);
14
27
 
..
..
@@ -21,11 +34,131 @@
21
34
 	IMX_PLLV1_IMX35,
22
35
 };
23
36
 
24
-struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
37
+enum imx_sscg_pll_type {
38
+	SCCG_PLL1,
39
+	SCCG_PLL2,
40
+};
41
+
42
+enum imx_pll14xx_type {
43
+	PLL_1416X,
44
+	PLL_1443X,
45
+};
46
+
47
+/* NOTE: Rate table should be kept sorted in descending order. */
48
+struct imx_pll14xx_rate_table {
49
+	unsigned int rate;
50
+	unsigned int pdiv;
51
+	unsigned int mdiv;
52
+	unsigned int sdiv;
53
+	unsigned int kdiv;
54
+};
55
+
56
+struct imx_pll14xx_clk {
57
+	enum imx_pll14xx_type type;
58
+	const struct imx_pll14xx_rate_table *rate_table;
59
+	int rate_count;
60
+	int flags;
61
+};
62
+
63
+extern struct imx_pll14xx_clk imx_1416x_pll;
64
+extern struct imx_pll14xx_clk imx_1443x_pll;
65
+extern struct imx_pll14xx_clk imx_1443x_dram_pll;
66
+
67
+#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
68
+	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
69
+
70
+#define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
71
+				cgr_val, clk_gate_flags, lock, share_count) \
72
+	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
73
+				cgr_val, clk_gate_flags, lock, share_count))
74
+
75
+#define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
76
+	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
77
+
78
+#define imx_clk_pfd(name, parent_name, reg, idx) \
79
+	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
80
+
81
+#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
82
+	to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
83
+
84
+#define imx_clk_fixed(name, rate) \
85
+	to_clk(imx_clk_hw_fixed(name, rate))
86
+
87
+#define imx_clk_fixed_factor(name, parent, mult, div) \
88
+	to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
89
+
90
+#define imx_clk_divider(name, parent, reg, shift, width) \
91
+	to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
92
+
93
+#define imx_clk_divider2(name, parent, reg, shift, width) \
94
+	to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
95
+
96
+#define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
97
+	to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
98
+
99
+#define imx_clk_gate(name, parent, reg, shift) \
100
+	to_clk(imx_clk_hw_gate(name, parent, reg, shift))
101
+
102
+#define imx_clk_gate_dis(name, parent, reg, shift) \
103
+	to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
104
+
105
+#define imx_clk_gate2(name, parent, reg, shift) \
106
+	to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
107
+
108
+#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
109
+	to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
110
+
111
+#define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
112
+	to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
113
+
114
+#define imx_clk_gate3(name, parent, reg, shift) \
115
+	to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
116
+
117
+#define imx_clk_gate4(name, parent, reg, shift) \
118
+	to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
119
+
120
+#define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
121
+	to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
122
+
123
+#define imx_clk_pllv1(type, name, parent, base) \
124
+	to_clk(imx_clk_hw_pllv1(type, name, parent, base))
125
+
126
+#define imx_clk_pllv2(name, parent, base) \
127
+	to_clk(imx_clk_hw_pllv2(name, parent, base))
128
+
129
+#define imx_clk_frac_pll(name, parent_name, base) \
130
+	to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
131
+
132
+#define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
133
+				bypass1, bypass2, base, flags) \
134
+	to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
135
+				bypass1, bypass2, base, flags))
136
+
137
+struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
138
+		 void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
139
+
140
+#define imx_clk_pll14xx(name, parent_name, base, pll_clk) \
141
+	to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
142
+
143
+struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
144
+				const char *parent_name, void __iomem *base,
145
+				const struct imx_pll14xx_clk *pll_clk);
146
+
147
+struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
25
148
 		const char *parent, void __iomem *base);
26
149
 
27
-struct clk *imx_clk_pllv2(const char *name, const char *parent,
150
+struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
28
151
 		void __iomem *base);
152
+
153
+struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
154
+			     void __iomem *base);
155
+
156
+struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
157
+				const char * const *parent_names,
158
+				u8 num_parents,
159
+				u8 parent, u8 bypass1, u8 bypass2,
160
+				void __iomem *base,
161
+				unsigned long flags);
29
162
 
30
163
 enum imx_pllv3_type {
31
164
 	IMX_PLLV3_GENERIC,
..
..
@@ -37,12 +170,33 @@
37
170
 	IMX_PLLV3_ENET_IMX7,
38
171
 	IMX_PLLV3_SYS_VF610,
39
172
 	IMX_PLLV3_DDR_IMX7,
173
+	IMX_PLLV3_AV_IMX7,
40
174
 };
41
175
 
42
-struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
176
+struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
43
177
 		const char *parent_name, void __iomem *base, u32 div_mask);
44
178
 
45
-struct clk *clk_register_gate2(struct device *dev, const char *name,
179
+#define PLL_1416X_RATE(_rate, _m, _p, _s)		\
180
+	{						\
181
+		.rate	=	(_rate),		\
182
+		.mdiv	=	(_m),			\
183
+		.pdiv	=	(_p),			\
184
+		.sdiv	=	(_s),			\
185
+	}
186
+
187
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)		\
188
+	{						\
189
+		.rate	=	(_rate),		\
190
+		.mdiv	=	(_m),			\
191
+		.pdiv	=	(_p),			\
192
+		.sdiv	=	(_s),			\
193
+		.kdiv	=	(_k),			\
194
+	}
195
+
196
+struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
197
+			     void __iomem *base);
198
+
199
+struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
46
200
 		const char *parent_name, unsigned long flags,
47
201
 		void __iomem *reg, u8 bit_idx, u8 cgr_val,
48
202
 		u8 clk_gate_flags, spinlock_t *lock,
..
..
@@ -51,122 +205,188 @@
51
205
 struct clk * imx_obtain_fixed_clock(
52
206
 			const char *name, unsigned long rate);
53
207
 
54
-struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
208
+struct clk_hw *imx_obtain_fixed_clock_hw(
209
+			const char *name, unsigned long rate);
210
+
211
+struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
212
+				       const char *name);
213
+
214
+struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
55
215
 	 void __iomem *reg, u8 shift, u32 exclusive_mask);
56
216
 
57
-struct clk *imx_clk_pfd(const char *name, const char *parent_name,
217
+struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
58
218
 		void __iomem *reg, u8 idx);
59
219
 
60
-struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
220
+struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
221
+			     void __iomem *reg, u8 idx);
222
+
223
+struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
61
224
 				 void __iomem *reg, u8 shift, u8 width,
62
225
 				 void __iomem *busy_reg, u8 busy_shift);
63
226
 
64
-struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
227
+struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
65
228
 			     u8 width, void __iomem *busy_reg, u8 busy_shift,
66
229
 			     const char * const *parent_names, int num_parents);
67
230
 
68
-struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
231
+struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
232
+				     const char * const *parent_names,
233
+				     int num_parents, bool mux_present,
234
+				     bool rate_present, bool gate_present,
235
+				     void __iomem *reg);
236
+
237
+struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
69
238
 				  void __iomem *reg, u8 shift, u8 width,
70
239
 				  void (*fixup)(u32 *val));
71
240
 
72
-struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
241
+struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
73
242
 			      u8 shift, u8 width, const char * const *parents,
74
243
 			      int num_parents, void (*fixup)(u32 *val));
75
244
 
76
-static inline struct clk *imx_clk_fixed(const char *name, int rate)
245
+static inline struct clk *to_clk(struct clk_hw *hw)
77
246
 {
78
-	return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
247
+	if (IS_ERR_OR_NULL(hw))
248
+		return ERR_CAST(hw);
249
+	return hw->clk;
79
250
 }
80
251
 
81
-static inline struct clk *imx_clk_mux_ldb(const char *name, void __iomem *reg,
252
+static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
253
+				  void __iomem *base,
254
+				  const struct imx_pll14xx_clk *pll_clk)
255
+{
256
+	return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk);
257
+}
258
+
259
+static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
260
+{
261
+	return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
262
+}
263
+
264
+static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg,
82
265
 			u8 shift, u8 width, const char * const *parents,
83
266
 			int num_parents)
84
267
 {
85
-	return clk_register_mux(NULL, name, parents, num_parents,
268
+	return clk_hw_register_mux(NULL, name, parents, num_parents,
86
269
 			CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
87
270
 			shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
88
271
 }
89
272
 
90
-static inline struct clk *imx_clk_fixed_factor(const char *name,
273
+static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
91
274
 		const char *parent, unsigned int mult, unsigned int div)
92
275
 {
93
-	return clk_register_fixed_factor(NULL, name, parent,
276
+	return clk_hw_register_fixed_factor(NULL, name, parent,
94
277
 			CLK_SET_RATE_PARENT, mult, div);
95
278
 }
96
279
 
97
-static inline struct clk *imx_clk_divider(const char *name, const char *parent,
98
-		void __iomem *reg, u8 shift, u8 width)
280
+static inline struct clk_hw *imx_clk_hw_divider(const char *name,
281
+						const char *parent,
282
+						void __iomem *reg, u8 shift,
283
+						u8 width)
99
284
 {
100
-	return clk_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
101
-			reg, shift, width, 0, &imx_ccm_lock);
285
+	return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
286
+				       reg, shift, width, 0, &imx_ccm_lock);
102
287
 }
103
288
 
104
-static inline struct clk *imx_clk_divider_flags(const char *name,
105
-		const char *parent, void __iomem *reg, u8 shift, u8 width,
106
-		unsigned long flags)
289
+static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
290
+						   const char *parent,
291
+						   void __iomem *reg, u8 shift,
292
+						   u8 width, unsigned long flags)
107
293
 {
108
-	return clk_register_divider(NULL, name, parent, flags,
109
-			reg, shift, width, 0, &imx_ccm_lock);
294
+	return clk_hw_register_divider(NULL, name, parent, flags,
295
+				       reg, shift, width, 0, &imx_ccm_lock);
110
296
 }
111
297
 
112
-static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
298
+static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent,
113
299
 		void __iomem *reg, u8 shift, u8 width)
114
300
 {
115
-	return clk_register_divider(NULL, name, parent,
301
+	return clk_hw_register_divider(NULL, name, parent,
116
302
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
117
303
 			reg, shift, width, 0, &imx_ccm_lock);
118
304
 }
119
305
 
120
-static inline struct clk *imx_clk_gate(const char *name, const char *parent,
121
-		void __iomem *reg, u8 shift)
306
+static inline struct clk *imx_clk_divider2_flags(const char *name,
307
+		const char *parent, void __iomem *reg, u8 shift, u8 width,
308
+		unsigned long flags)
122
309
 {
123
-	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
124
-			shift, 0, &imx_ccm_lock);
310
+	return clk_register_divider(NULL, name, parent,
311
+			flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
312
+			reg, shift, width, 0, &imx_ccm_lock);
125
313
 }
126
314
 
127
-static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
315
+static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent,
128
316
 		void __iomem *reg, u8 shift, unsigned long flags)
129
317
 {
130
-	return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
318
+	return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
131
319
 			shift, 0, &imx_ccm_lock);
132
320
 }
133
321
 
134
-static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent,
322
+static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
323
+					     void __iomem *reg, u8 shift)
324
+{
325
+	return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
326
+				    shift, 0, &imx_ccm_lock);
327
+}
328
+
329
+static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name,
330
+						const char *parent, void __iomem *reg, u8 shift)
331
+{
332
+	return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
333
+				    shift, 0, &imx_ccm_lock);
334
+}
335
+
336
+static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent,
135
337
 		void __iomem *reg, u8 shift)
136
338
 {
137
-	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
339
+	return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
138
340
 			shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
139
341
 }
140
342
 
141
-static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
142
-		void __iomem *reg, u8 shift)
143
-{
144
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
145
-			shift, 0x3, 0, &imx_ccm_lock, NULL);
146
-}
147
-
148
-static inline struct clk *imx_clk_gate2_flags(const char *name, const char *parent,
343
+static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent,
149
344
 		void __iomem *reg, u8 shift, unsigned long flags)
150
345
 {
151
-	return clk_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
346
+	return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
347
+			shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
348
+}
349
+
350
+static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent,
351
+		void __iomem *reg, u8 shift)
352
+{
353
+	return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
152
354
 			shift, 0x3, 0, &imx_ccm_lock, NULL);
153
355
 }
154
356
 
155
-static inline struct clk *imx_clk_gate2_shared(const char *name,
357
+static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent,
358
+		void __iomem *reg, u8 shift, unsigned long flags)
359
+{
360
+	return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
361
+			shift, 0x3, 0, &imx_ccm_lock, NULL);
362
+}
363
+
364
+static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name,
156
365
 		const char *parent, void __iomem *reg, u8 shift,
157
366
 		unsigned int *share_count)
158
367
 {
159
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
368
+	return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
160
369
 			shift, 0x3, 0, &imx_ccm_lock, share_count);
161
370
 }
162
371
 
163
-static inline struct clk *imx_clk_gate2_shared2(const char *name,
372
+static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
164
373
 		const char *parent, void __iomem *reg, u8 shift,
165
374
 		unsigned int *share_count)
166
375
 {
167
-	return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
376
+	return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
168
377
 				  CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
169
378
 				  &imx_ccm_lock, share_count);
379
+}
380
+
381
+static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev,
382
+				const char *name, const char *parent,
383
+				void __iomem *reg, u8 shift,
384
+				unsigned int *share_count)
385
+{
386
+	return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
387
+					CLK_OPS_PARENT_ENABLE, reg, shift, 0x3,
388
+					IMX_CLK_GATE2_SINGLE_BIT,
389
+					&imx_ccm_lock, share_count);
170
390
 }
171
391
 
172
392
 static inline struct clk *imx_clk_gate2_cgr(const char *name,
..
..
@@ -176,29 +396,62 @@
176
396
 			shift, cgr_val, 0, &imx_ccm_lock, NULL);
177
397
 }
178
398
 
179
-static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
399
+static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent,
180
400
 		void __iomem *reg, u8 shift)
181
401
 {
182
-	return clk_register_gate(NULL, name, parent,
402
+	return clk_hw_register_gate(NULL, name, parent,
183
403
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
184
404
 			reg, shift, 0, &imx_ccm_lock);
185
405
 }
186
406
 
187
-static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
407
+static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name,
408
+		const char *parent, void __iomem *reg, u8 shift,
409
+		unsigned long flags)
410
+{
411
+	return clk_hw_register_gate(NULL, name, parent,
412
+			flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
413
+			reg, shift, 0, &imx_ccm_lock);
414
+}
415
+
416
+#define imx_clk_gate3_flags(name, parent, reg, shift, flags) \
417
+	to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
418
+
419
+static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent,
188
420
 		void __iomem *reg, u8 shift)
189
421
 {
190
-	return clk_register_gate2(NULL, name, parent,
422
+	return clk_hw_register_gate2(NULL, name, parent,
191
423
 			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
192
424
 			reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
193
425
 }
194
426
 
195
-static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
427
+static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
428
+		const char *parent, void __iomem *reg, u8 shift,
429
+		unsigned long flags)
430
+{
431
+	return clk_hw_register_gate2(NULL, name, parent,
432
+			flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
433
+			reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
434
+}
435
+
436
+#define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
437
+	to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
438
+
439
+static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg,
196
440
 			u8 shift, u8 width, const char * const *parents,
197
441
 			int num_parents)
198
442
 {
199
-	return clk_register_mux(NULL, name, parents, num_parents,
443
+	return clk_hw_register_mux(NULL, name, parents, num_parents,
200
444
 			CLK_SET_RATE_NO_REPARENT, reg, shift,
201
445
 			width, 0, &imx_ccm_lock);
446
+}
447
+
448
+static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev,
449
+			const char *name, void __iomem *reg, u8 shift,
450
+			u8 width, const char * const *parents, int num_parents)
451
+{
452
+	return clk_hw_register_mux(dev, name, parents, num_parents,
453
+			CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
454
+			reg, shift, width, 0, &imx_ccm_lock);
202
455
 }
203
456
 
204
457
 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
..
..
@@ -208,6 +461,17 @@
208
461
 	return clk_register_mux(NULL, name, parents, num_parents,
209
462
 			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
210
463
 			reg, shift, width, 0, &imx_ccm_lock);
464
+}
465
+
466
+static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
467
+					     u8 shift, u8 width,
468
+					     const char * const *parents,
469
+					     int num_parents)
470
+{
471
+	return clk_hw_register_mux(NULL, name, parents, num_parents,
472
+				   CLK_SET_RATE_NO_REPARENT |
473
+				   CLK_OPS_PARENT_ENABLE,
474
+				   reg, shift, width, 0, &imx_ccm_lock);
211
475
 }
212
476
 
213
477
 static inline struct clk *imx_clk_mux_flags(const char *name,
..
..
@@ -220,8 +484,121 @@
220
484
 			&imx_ccm_lock);
221
485
 }
222
486
 
223
-struct clk *imx_clk_cpu(const char *name, const char *parent_name,
487
+static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name,
488
+		void __iomem *reg, u8 shift, u8 width,
489
+		const char * const *parents,
490
+		int num_parents, unsigned long flags)
491
+{
492
+	return clk_hw_register_mux(NULL, name, parents, num_parents,
493
+			flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
494
+			reg, shift, width, 0, &imx_ccm_lock);
495
+}
496
+
497
+static inline struct clk *imx_clk_mux2_flags(const char *name,
498
+		void __iomem *reg, u8 shift, u8 width,
499
+		const char * const *parents,
500
+		int num_parents, unsigned long flags)
501
+{
502
+	return clk_register_mux(NULL, name, parents, num_parents,
503
+			flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
504
+			reg, shift, width, 0, &imx_ccm_lock);
505
+}
506
+
507
+static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
508
+						  void __iomem *reg, u8 shift,
509
+						  u8 width,
510
+						  const char * const *parents,
511
+						  int num_parents,
512
+						  unsigned long flags)
513
+{
514
+	return clk_hw_register_mux(NULL, name, parents, num_parents,
515
+				   flags | CLK_SET_RATE_NO_REPARENT,
516
+				   reg, shift, width, 0, &imx_ccm_lock);
517
+}
518
+
519
+static inline struct clk_hw *imx_dev_clk_hw_mux_flags(struct device *dev,
520
+						  const char *name,
521
+						  void __iomem *reg, u8 shift,
522
+						  u8 width,
523
+						  const char * const *parents,
524
+						  int num_parents,
525
+						  unsigned long flags)
526
+{
527
+	return clk_hw_register_mux(dev, name, parents, num_parents,
528
+				   flags | CLK_SET_RATE_NO_REPARENT,
529
+				   reg, shift, width, 0, &imx_ccm_lock);
530
+}
531
+
532
+struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
224
533
 		struct clk *div, struct clk *mux, struct clk *pll,
225
534
 		struct clk *step);
226
535
 
536
+#define IMX_COMPOSITE_CORE		BIT(0)
537
+#define IMX_COMPOSITE_BUS		BIT(1)
538
+#define IMX_COMPOSITE_FW_MANAGED	BIT(2)
539
+
540
+struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
541
+					    const char * const *parent_names,
542
+					    int num_parents,
543
+					    void __iomem *reg,
544
+					    u32 composite_flags,
545
+					    unsigned long flags);
546
+
547
+#define imx8m_clk_hw_composite_bus(name, parent_names, reg)	\
548
+	imx8m_clk_hw_composite_flags(name, parent_names, \
549
+			ARRAY_SIZE(parent_names), reg, \
550
+			IMX_COMPOSITE_BUS, \
551
+			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
552
+
553
+#define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg)	\
554
+	imx8m_clk_hw_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \
555
+			IMX_COMPOSITE_BUS, \
556
+			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE | CLK_IS_CRITICAL)
557
+
558
+#define imx8m_clk_hw_composite_core(name, parent_names, reg)	\
559
+	imx8m_clk_hw_composite_flags(name, parent_names, \
560
+			ARRAY_SIZE(parent_names), reg, \
561
+			IMX_COMPOSITE_CORE, \
562
+			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
563
+
564
+#define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
565
+				  flags) \
566
+	to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
567
+				num_parents, reg, 0, flags))
568
+
569
+#define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
570
+	imx8m_clk_hw_composite_flags(name, parent_names, \
571
+		ARRAY_SIZE(parent_names), reg, 0, \
572
+		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
573
+
574
+#define __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, flags) \
575
+	imx8m_clk_hw_composite_flags(name, parent_names, \
576
+		ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_FW_MANAGED, \
577
+		flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
578
+
579
+#define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
580
+	__imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, 0)
581
+
582
+#define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
583
+	__imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, CLK_IS_CRITICAL)
584
+
585
+#define __imx8m_clk_composite(name, parent_names, reg, flags) \
586
+	to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
587
+
588
+#define imx8m_clk_hw_composite(name, parent_names, reg) \
589
+	__imx8m_clk_hw_composite(name, parent_names, reg, 0)
590
+
591
+#define imx8m_clk_composite(name, parent_names, reg) \
592
+	__imx8m_clk_composite(name, parent_names, reg, 0)
593
+
594
+#define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
595
+	__imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL)
596
+
597
+#define imx8m_clk_composite_critical(name, parent_names, reg) \
598
+	__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
599
+
600
+struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
601
+		unsigned long flags, void __iomem *reg, u8 shift, u8 width,
602
+		u8 clk_divider_flags, const struct clk_div_table *table,
603
+		spinlock_t *lock);
227
604
 #endif