| .. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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| 1 | 2 | /* |
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| 2 | 3 | * Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de> |
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| 3 | | - * |
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| 4 | | - * This program is free software; you can redistribute it and/or |
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| 5 | | - * modify it under the terms of the GNU General Public License |
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| 6 | | - * as published by the Free Software Foundation; either version 2 |
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| 7 | | - * of the License, or (at your option) any later version. |
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| 8 | | - * This program is distributed in the hope that it will be useful, |
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| 9 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 10 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 11 | | - * GNU General Public License for more details. |
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| 12 | | - * |
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| 13 | | - * You should have received a copy of the GNU General Public License |
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| 14 | | - * along with this program; if not, write to the Free Software |
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| 15 | | - * Foundation. |
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| 16 | 4 | */ |
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| 17 | 5 | |
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| 18 | 6 | #include <linux/module.h> |
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| .. | .. |
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| 142 | 130 | clk_prepare_enable(clk[iim_gate]); |
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| 143 | 131 | mx31_revision(); |
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| 144 | 132 | clk_disable_unprepare(clk[iim_gate]); |
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| 145 | | -} |
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| 146 | | - |
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| 147 | | -int __init mx31_clocks_init(unsigned long fref) |
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| 148 | | -{ |
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| 149 | | - void __iomem *base; |
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| 150 | | - |
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| 151 | | - base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); |
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| 152 | | - if (!base) |
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| 153 | | - panic("%s: failed to map registers\n", __func__); |
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| 154 | | - |
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| 155 | | - _mx31_clocks_init(base, fref); |
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| 156 | | - |
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| 157 | | - clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); |
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| 158 | | - clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); |
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| 159 | | - clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); |
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| 160 | | - clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1"); |
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| 161 | | - clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); |
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| 162 | | - clk_register_clkdev(clk[pwm_gate], "pwm", NULL); |
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| 163 | | - clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); |
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| 164 | | - clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); |
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| 165 | | - clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); |
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| 166 | | - clk_register_clkdev(clk[epit1_gate], "epit", NULL); |
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| 167 | | - clk_register_clkdev(clk[epit2_gate], "epit", NULL); |
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| 168 | | - clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0"); |
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| 169 | | - clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); |
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| 170 | | - clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); |
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| 171 | | - clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); |
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| 172 | | - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); |
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| 173 | | - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); |
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| 174 | | - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); |
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| 175 | | - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1"); |
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| 176 | | - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1"); |
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| 177 | | - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); |
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| 178 | | - clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); |
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| 179 | | - clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); |
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| 180 | | - clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); |
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| 181 | | - clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); |
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| 182 | | - clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); |
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| 183 | | - clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); |
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| 184 | | - clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); |
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| 185 | | - /* i.mx31 has the i.mx21 type uart */ |
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| 186 | | - clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); |
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| 187 | | - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); |
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| 188 | | - clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); |
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| 189 | | - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); |
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| 190 | | - clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); |
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| 191 | | - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); |
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| 192 | | - clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); |
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| 193 | | - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); |
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| 194 | | - clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); |
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| 195 | | - clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); |
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| 196 | | - clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); |
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| 197 | | - clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); |
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| 198 | | - clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); |
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| 199 | | - clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); |
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| 200 | | - clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0"); |
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| 201 | | - clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1"); |
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| 202 | | - clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); |
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| 203 | | - clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); |
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| 204 | | - clk_register_clkdev(clk[firi_gate], "firi", NULL); |
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| 205 | | - clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); |
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| 206 | | - clk_register_clkdev(clk[rtic_gate], "rtic", NULL); |
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| 207 | | - clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga"); |
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| 208 | | - clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); |
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| 209 | | - clk_register_clkdev(clk[iim_gate], "iim", NULL); |
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| 210 | | - |
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| 211 | | - |
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| 212 | | - imx_register_uart_clocks(uart_clks); |
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| 213 | | - mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31); |
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| 214 | | - |
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| 215 | | - return 0; |
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| 216 | 133 | } |
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| 217 | 134 | |
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| 218 | 135 | static void __init mx31_clocks_init_dt(struct device_node *np) |
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