enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/clk/clk-cdce925.c
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@@ -16,6 +16,7 @@
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 #include <linux/module.h>
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 #include <linux/i2c.h>
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 #include <linux/regmap.h>
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+#include <linux/regulator/consumer.h>
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 #include <linux/slab.h>
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 #include <linux/gcd.h>
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@@ -602,6 +603,30 @@
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 	return &data->clk[idx].hw;
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 }
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+static void cdce925_regulator_disable(void *regulator)
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+{
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+	regulator_disable(regulator);
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+}
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+
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+static int cdce925_regulator_enable(struct device *dev, const char *name)
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+{
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+	struct regulator *regulator;
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+	int err;
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+
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+	regulator = devm_regulator_get(dev, name);
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+	if (IS_ERR(regulator))
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+		return PTR_ERR(regulator);
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+
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+	err = regulator_enable(regulator);
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+	if (err) {
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+		dev_err(dev, "Failed to enable %s: %d\n", name, err);
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+		return err;
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+	}
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+
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+	return devm_add_action_or_reset(dev, cdce925_regulator_disable,
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+					regulator);
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+}
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+
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 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is
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  * just weird, so just use the single byte mode exclusively. */
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 static struct regmap_bus regmap_cdce925_bus = {
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@@ -616,7 +641,7 @@
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 	struct device_node *node = client->dev.of_node;
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 	const char *parent_name;
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 	const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	u32 value;
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 	int i;
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 	int err;
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@@ -630,6 +655,15 @@
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 	};
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 	dev_dbg(&client->dev, "%s\n", __func__);
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+
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+	err = cdce925_regulator_enable(&client->dev, "vdd");
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+	if (err)
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+		return err;
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+
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+	err = cdce925_regulator_enable(&client->dev, "vddout");
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+	if (err)
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+		return err;
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+
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 	data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
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 	if (!data)
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 		return -ENOMEM;
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@@ -669,8 +703,8 @@
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 	/* Register PLL clocks */
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 	for (i = 0; i < data->chip_info->num_plls; ++i) {
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-		pll_clk_name[i] = kasprintf(GFP_KERNEL, "%s.pll%d",
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-			client->dev.of_node->name, i);
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+		pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
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+			client->dev.of_node, i);
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 		init.name = pll_clk_name[i];
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 		data->pll[i].chip = data;
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 		data->pll[i].hw.init = &init;
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@@ -703,6 +737,7 @@
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 				0x12 + (i*CDCE925_OFFSET_PLL),
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 				0x07, value & 0x07);
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 		}
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+		of_node_put(np_output);
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 	}
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 	/* Register output clock Y1 */
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@@ -710,7 +745,7 @@
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 	init.flags = 0;
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 	init.num_parents = 1;
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 	init.parent_names = &parent_name; /* Mux Y1 to input */
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-	init.name = kasprintf(GFP_KERNEL, "%s.Y1", client->dev.of_node->name);
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+	init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
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 	data->clk[0].chip = data;
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 	data->clk[0].hw.init = &init;
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 	data->clk[0].index = 0;
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@@ -727,8 +762,8 @@
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 	init.flags = CLK_SET_RATE_PARENT;
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 	init.num_parents = 1;
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 	for (i = 1; i < data->chip_info->num_outputs; ++i) {
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-		init.name = kasprintf(GFP_KERNEL, "%s.Y%d",
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-			client->dev.of_node->name, i+1);
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+		init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
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+			client->dev.of_node, i+1);
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 		data->clk[i].chip = data;
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 		data->clk[i].hw.init = &init;
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 		data->clk[i].index = i;