enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/drivers/acpi/pci_mcfg.c
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@@ -1,20 +1,9 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2016 Broadcom
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  *	Author: Jayachandran C <jchandra@broadcom.com>
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  * Copyright (C) 2016 Semihalf
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  * 	Author: Tomasz Nowicki <tn@semihalf.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License, version 2, as
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- * published by the Free Software Foundation (the "GPL").
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- *
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- * This program is distributed in the hope that it will be useful, but
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- * WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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- * General Public License version 2 (GPLv2) for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * version 2 (GPLv2) along with this source code.
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  */
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8
 
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 #define pr_fmt(fmt) "ACPI: " fmt
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@@ -40,7 +29,7 @@
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 	u32 oem_revision;
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 	u16 segment;
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 	struct resource bus_range;
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-	struct pci_ecam_ops *ops;
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+	const struct pci_ecam_ops *ops;
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 	struct resource cfgres;
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 };
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@@ -51,6 +40,20 @@
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 static struct mcfg_fixup mcfg_quirks[] = {
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 /*	{ OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
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+
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+#ifdef CONFIG_ARM64
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+
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+#define AL_ECAM(table_id, rev, seg, ops) \
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+	{ "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
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+
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+	AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
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+	AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
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+	AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
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+	AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
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+	AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
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+	AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
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+	AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
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+	AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
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 #define QCOM_ECAM32(seg) \
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 	{ "QCOM  ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
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@@ -63,6 +66,11 @@
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 	QCOM_ECAM32(5),
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 	QCOM_ECAM32(6),
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 	QCOM_ECAM32(7),
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+
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+#define RKCP_ECAM(seg, table_id, ops) \
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+	{ "RKCP  ", table_id, 0x0000, seg, MCFG_BUS_ANY, ops }
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+
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+	RKCP_ECAM(0, "RK3588  ", &rk_pcie_ecam_ops), /* pcie3x4: Name (_SEG, Zero) */
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 #define HISI_QUAD_DOM(table_id, seg, ops) \
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 	{ "HISI  ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
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@@ -141,6 +149,27 @@
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 	XGENE_V2_ECAM_MCFG(4, 0),
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 	XGENE_V2_ECAM_MCFG(4, 1),
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 	XGENE_V2_ECAM_MCFG(4, 2),
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+
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+#define ALTRA_ECAM_QUIRK(rev, seg) \
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+	{ "Ampere", "Altra   ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
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+
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+	ALTRA_ECAM_QUIRK(1, 0),
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+	ALTRA_ECAM_QUIRK(1, 1),
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+	ALTRA_ECAM_QUIRK(1, 2),
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+	ALTRA_ECAM_QUIRK(1, 3),
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+	ALTRA_ECAM_QUIRK(1, 4),
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+	ALTRA_ECAM_QUIRK(1, 5),
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+	ALTRA_ECAM_QUIRK(1, 6),
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+	ALTRA_ECAM_QUIRK(1, 7),
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+	ALTRA_ECAM_QUIRK(1, 8),
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+	ALTRA_ECAM_QUIRK(1, 9),
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+	ALTRA_ECAM_QUIRK(1, 10),
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+	ALTRA_ECAM_QUIRK(1, 11),
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+	ALTRA_ECAM_QUIRK(1, 12),
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+	ALTRA_ECAM_QUIRK(1, 13),
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+	ALTRA_ECAM_QUIRK(1, 14),
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+	ALTRA_ECAM_QUIRK(1, 15),
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+#endif /* ARM64 */
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 };
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 static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
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@@ -152,7 +181,7 @@
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 {
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 	if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
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 	    !memcmp(f->oem_table_id, mcfg_oem_table_id,
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-	            ACPI_OEM_TABLE_ID_SIZE) &&
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+		    ACPI_OEM_TABLE_ID_SIZE) &&
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 	    f->oem_revision == mcfg_oem_revision &&
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 	    f->segment == segment &&
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 	    resource_contains(&f->bus_range, bus_range))
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@@ -164,7 +193,7 @@
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193
 
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 static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
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 				  struct resource *cfgres,
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-				  struct pci_ecam_ops **ecam_ops)
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+				  const struct pci_ecam_ops **ecam_ops)
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 {
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 #ifdef CONFIG_PCI_QUIRKS
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 	u16 segment = root->segment;
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@@ -190,9 +219,9 @@
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 static LIST_HEAD(pci_mcfg_list);
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 int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
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-		    struct pci_ecam_ops **ecam_ops)
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+		    const struct pci_ecam_ops **ecam_ops)
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 {
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-	struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
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+	const struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
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 	struct resource *bus_res = &root->secondary;
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 	u16 seg = root->segment;
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 	struct mcfg_entry *e;
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@@ -279,5 +308,5 @@
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 {
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 	int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
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 	if (err)
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-		pr_err("Failed to parse MCFG (%d)\n", err);
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+		pr_debug("Failed to parse MCFG (%d)\n", err);
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 }