enable docker ppp

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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/x86/kvm/x86.h
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@@ -5,6 +5,7 @@
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5
 #include <linux/kvm_host.h>
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6
 #include <asm/pvclock.h>
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 #include "kvm_cache_regs.h"
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+#include "kvm_emulate.h"
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9
 
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 #define KVM_DEFAULT_PLE_GAP		128
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 #define KVM_VMX_DEFAULT_PLE_WINDOW	4096
..
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@@ -96,7 +97,7 @@
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97
 
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 	if (!is_long_mode(vcpu))
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 		return false;
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-	kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
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+	kvm_x86_ops.get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
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 	return cs_l;
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 }
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..
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@@ -124,6 +125,12 @@
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 	return vcpu->arch.walk_mmu == &vcpu->arch.nested_mmu;
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 }
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+static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
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+{
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+	++vcpu->stat.tlb_flush;
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+	kvm_x86_ops.tlb_flush_current(vcpu);
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+}
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+
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 static inline int is_pae(struct kvm_vcpu *vcpu)
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 {
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 	return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
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@@ -144,19 +151,9 @@
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 	return !is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu);
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 }
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153
 
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-static inline u32 bit(int bitno)
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-{
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-	return 1 << (bitno & 31);
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-}
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-
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 static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
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 {
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 	return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
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-}
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-
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-static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
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-{
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-	return (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_LA57) ? 57 : 48;
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 }
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 static inline u64 get_canonical(u64 la, u8 vaddr_bits)
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@@ -166,21 +163,7 @@
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163
 
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 static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
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 {
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-#ifdef CONFIG_X86_64
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 	return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la;
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-#else
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-	return false;
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-#endif
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-}
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-
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-static inline bool emul_is_noncanonical_address(u64 la,
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-						struct x86_emulate_ctxt *ctxt)
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-{
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-#ifdef CONFIG_X86_64
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-	return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la;
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-#else
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-	return false;
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-#endif
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167
 }
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168
 
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 static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,
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@@ -188,7 +171,7 @@
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 {
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 	u64 gen = kvm_memslots(vcpu->kvm)->generation;
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173
 
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-	if (unlikely(gen & 1))
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+	if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
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 		return;
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 	/*
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@@ -196,7 +179,7 @@
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 	 * actually a nGPA.
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 	 */
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 	vcpu->arch.mmio_gva = mmu_is_nested(vcpu) ? 0 : gva & PAGE_MASK;
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-	vcpu->arch.access = access;
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+	vcpu->arch.mmio_access = access;
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 	vcpu->arch.mmio_gfn = gfn;
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 	vcpu->arch.mmio_gen = gen;
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 }
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@@ -238,8 +221,7 @@
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 	return false;
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 }
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223
 
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-static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu,
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-					       enum kvm_reg reg)
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+static inline unsigned long kvm_register_readl(struct kvm_vcpu *vcpu, int reg)
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 {
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 	unsigned long val = kvm_register_read(vcpu, reg);
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227
 
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@@ -247,8 +229,7 @@
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 }
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230
 
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 static inline void kvm_register_writel(struct kvm_vcpu *vcpu,
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-				       enum kvm_reg reg,
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-				       unsigned long val)
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+				       int reg, unsigned long val)
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 {
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 	if (!is_64_bit_mode(vcpu))
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 		val = (u32)val;
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@@ -260,8 +241,12 @@
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 	return !(kvm->arch.disabled_quirks & quirk);
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 }
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243
 
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-void kvm_set_pending_timer(struct kvm_vcpu *vcpu);
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-int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
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+static inline bool kvm_vcpu_latch_init(struct kvm_vcpu *vcpu)
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+{
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+	return is_smm(vcpu) || kvm_x86_ops.apic_init_signal_blocked(vcpu);
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+}
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+
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+void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip);
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250
 
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 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr);
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 u64 get_kvmclock_ns(struct kvm *kvm);
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@@ -276,6 +261,8 @@
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261
 
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 int handle_ud(struct kvm_vcpu *vcpu);
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263
 
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+void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu);
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+
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 void kvm_vcpu_mtrr_init(struct kvm_vcpu *vcpu);
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 u8 kvm_mtrr_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn);
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 bool kvm_mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data);
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@@ -284,22 +271,28 @@
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 bool kvm_mtrr_check_gfn_range_consistency(struct kvm_vcpu *vcpu, gfn_t gfn,
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272
 					  int page_num);
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 bool kvm_vector_hashing_enabled(void);
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+void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code);
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+int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
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+				    void *insn, int insn_len);
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 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
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 			    int emulation_type, void *insn, int insn_len);
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+fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu);
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280
 
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-#define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
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-				| XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
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-				| XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
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-				| XFEATURE_MASK_PKRU)
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 extern u64 host_xcr0;
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+extern u64 supported_xcr0;
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+extern u64 supported_xss;
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284
 
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-extern u64 kvm_supported_xcr0(void);
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+static inline bool kvm_mpx_supported(void)
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+{
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+	return (supported_xcr0 & (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR))
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+		== (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
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+}
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290
 
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 extern unsigned int min_timer_period_us;
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292
 
300
-extern unsigned int lapic_timer_advance_ns;
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-
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293
 extern bool enable_vmware_backdoor;
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+
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+extern int pi_inject_timer;
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296
 
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 extern struct static_key kvm_no_apic_vcpu;
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..
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@@ -338,6 +331,11 @@
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 	return kvm->arch.pause_in_guest;
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 }
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333
 
334
+static inline bool kvm_cstate_in_guest(struct kvm *kvm)
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+{
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+	return kvm->arch.cstate_in_guest;
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+}
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+
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 DECLARE_PER_CPU(struct kvm_vcpu *, current_vcpu);
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340
 
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 static inline void kvm_before_interrupt(struct kvm_vcpu *vcpu)
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@@ -359,7 +357,58 @@
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 	return (data | ((data & 0x0202020202020202ull) << 1)) == data;
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358
 }
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359
 
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-void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu);
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-void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu);
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+static inline bool kvm_dr7_valid(u64 data)
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+{
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+	/* Bits [63:32] are reserved */
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+	return !(data >> 32);
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+}
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+static inline bool kvm_dr6_valid(u64 data)
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+{
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+	/* Bits [63:32] are reserved */
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+	return !(data >> 32);
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+}
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+
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+void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu);
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+void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu);
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+int kvm_spec_ctrl_test_value(u64 value);
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+int kvm_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
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+bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu);
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+int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
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+			      struct x86_exception *e);
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+int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva);
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+bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type);
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+
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+/*
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+ * Internal error codes that are used to indicate that MSR emulation encountered
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+ * an error that should result in #GP in the guest, unless userspace
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+ * handles it.
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+ */
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+#define  KVM_MSR_RET_INVALID	2	/* in-kernel MSR emulation #GP condition */
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+#define  KVM_MSR_RET_FILTERED	3	/* #GP due to userspace MSR filter */
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+
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+#define __cr4_reserved_bits(__cpu_has, __c)             \
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+({                                                      \
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+	u64 __reserved_bits = CR4_RESERVED_BITS;        \
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+                                                        \
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+	if (!__cpu_has(__c, X86_FEATURE_XSAVE))         \
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+		__reserved_bits |= X86_CR4_OSXSAVE;     \
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+	if (!__cpu_has(__c, X86_FEATURE_SMEP))          \
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+		__reserved_bits |= X86_CR4_SMEP;        \
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+	if (!__cpu_has(__c, X86_FEATURE_SMAP))          \
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+		__reserved_bits |= X86_CR4_SMAP;        \
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+	if (!__cpu_has(__c, X86_FEATURE_FSGSBASE))      \
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+		__reserved_bits |= X86_CR4_FSGSBASE;    \
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+	if (!__cpu_has(__c, X86_FEATURE_PKU))           \
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+		__reserved_bits |= X86_CR4_PKE;         \
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+	if (!__cpu_has(__c, X86_FEATURE_LA57))          \
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+		__reserved_bits |= X86_CR4_LA57;        \
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+	if (!__cpu_has(__c, X86_FEATURE_UMIP))          \
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+		__reserved_bits |= X86_CR4_UMIP;        \
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+	if (!__cpu_has(__c, X86_FEATURE_VMX))           \
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+		__reserved_bits |= X86_CR4_VMXE;        \
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+	if (!__cpu_has(__c, X86_FEATURE_PCID))          \
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+		__reserved_bits |= X86_CR4_PCIDE;       \
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+	__reserved_bits;                                \
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+})
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 #endif