| .. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 1 | 2 | /* |
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| 2 | 3 | * vDSO provided cache flush routines |
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| 3 | 4 | * |
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| 4 | 5 | * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), |
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| 5 | 6 | * IBM Corp. |
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| 6 | | - * |
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| 7 | | - * This program is free software; you can redistribute it and/or |
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| 8 | | - * modify it under the terms of the GNU General Public License |
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| 9 | | - * as published by the Free Software Foundation; either version |
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| 10 | | - * 2 of the License, or (at your option) any later version. |
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| 11 | 7 | */ |
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| 12 | 8 | #include <asm/processor.h> |
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| 13 | 9 | #include <asm/ppc_asm.h> |
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| 14 | 10 | #include <asm/vdso.h> |
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| 11 | +#include <asm/vdso_datapage.h> |
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| 15 | 12 | #include <asm/asm-offsets.h> |
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| 13 | +#include <asm/cache.h> |
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| 16 | 14 | |
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| 17 | 15 | .text |
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| 18 | 16 | |
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| .. | .. |
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| 26 | 24 | */ |
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| 27 | 25 | V_FUNCTION_BEGIN(__kernel_sync_dicache) |
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| 28 | 26 | .cfi_startproc |
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| 27 | +#ifdef CONFIG_PPC64 |
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| 29 | 28 | mflr r12 |
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| 30 | 29 | .cfi_register lr,r12 |
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| 31 | | - mr r11,r3 |
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| 32 | | - bl __get_datapage@local |
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| 30 | + get_datapage r10, r0 |
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| 33 | 31 | mtlr r12 |
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| 34 | | - mr r10,r3 |
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| 32 | +#endif |
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| 35 | 33 | |
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| 34 | +#ifdef CONFIG_PPC64 |
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| 36 | 35 | lwz r7,CFG_DCACHE_BLOCKSZ(r10) |
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| 37 | 36 | addi r5,r7,-1 |
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| 38 | | - andc r6,r11,r5 /* round low to line bdy */ |
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| 37 | +#else |
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| 38 | + li r5, L1_CACHE_BYTES - 1 |
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| 39 | +#endif |
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| 40 | + andc r6,r3,r5 /* round low to line bdy */ |
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| 39 | 41 | subf r8,r6,r4 /* compute length */ |
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| 40 | 42 | add r8,r8,r5 /* ensure we get enough */ |
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| 43 | +#ifdef CONFIG_PPC64 |
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| 41 | 44 | lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10) |
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| 42 | 45 | srw. r8,r8,r9 /* compute line count */ |
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| 46 | +#else |
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| 47 | + srwi. r8, r8, L1_CACHE_SHIFT |
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| 48 | + mr r7, r6 |
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| 49 | +#endif |
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| 43 | 50 | crclr cr0*4+so |
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| 44 | 51 | beqlr /* nothing to do? */ |
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| 45 | 52 | mtctr r8 |
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| 46 | 53 | 1: dcbst 0,r6 |
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| 54 | +#ifdef CONFIG_PPC64 |
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| 47 | 55 | add r6,r6,r7 |
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| 56 | +#else |
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| 57 | + addi r6, r6, L1_CACHE_BYTES |
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| 58 | +#endif |
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| 48 | 59 | bdnz 1b |
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| 49 | 60 | sync |
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| 50 | 61 | |
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| 51 | 62 | /* Now invalidate the instruction cache */ |
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| 52 | 63 | |
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| 64 | +#ifdef CONFIG_PPC64 |
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| 53 | 65 | lwz r7,CFG_ICACHE_BLOCKSZ(r10) |
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| 54 | 66 | addi r5,r7,-1 |
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| 55 | | - andc r6,r11,r5 /* round low to line bdy */ |
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| 67 | + andc r6,r3,r5 /* round low to line bdy */ |
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| 56 | 68 | subf r8,r6,r4 /* compute length */ |
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| 57 | 69 | add r8,r8,r5 |
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| 58 | 70 | lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10) |
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| 59 | 71 | srw. r8,r8,r9 /* compute line count */ |
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| 60 | 72 | crclr cr0*4+so |
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| 61 | 73 | beqlr /* nothing to do? */ |
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| 74 | +#endif |
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| 62 | 75 | mtctr r8 |
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| 76 | +#ifdef CONFIG_PPC64 |
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| 63 | 77 | 2: icbi 0,r6 |
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| 64 | 78 | add r6,r6,r7 |
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| 79 | +#else |
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| 80 | +2: icbi 0, r7 |
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| 81 | + addi r7, r7, L1_CACHE_BYTES |
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| 82 | +#endif |
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| 65 | 83 | bdnz 2b |
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| 66 | 84 | isync |
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| 67 | 85 | li r3,0 |
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