enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/powerpc/kernel/pci_of_scan.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Helper routines to scan the device tree for PCI devices and busses
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  *
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@@ -8,10 +9,6 @@
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  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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  *   Rework, based on alpha PCI code.
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  * Copyright (c) 2009 Secret Lab Technologies Ltd.
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * version 2 as published by the Free Software Foundation.
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  */
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 #include <linux/pci.h>
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@@ -37,31 +34,75 @@
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  * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
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  * @addr0: value of 1st cell of a device tree PCI address.
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  * @bridge: Set this flag if the address is from a bridge 'ranges' property
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+ *
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+ * PCI Bus Binding to IEEE Std 1275-1994
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+ *
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+ * Bit#            33222222 22221111 11111100 00000000
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+ *                 10987654 32109876 54321098 76543210
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+ * phys.hi cell:   npt000ss bbbbbbbb dddddfff rrrrrrrr
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+ * phys.mid cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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+ * phys.lo cell:   llllllll llllllll llllllll llllllll
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+ *
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+ * where:
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+ * n        is 0 if the address is relocatable, 1 otherwise
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+ * p        is 1 if the addressable region is "prefetchable", 0 otherwise
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+ * t        is 1 if the address is aliased (for non-relocatable I/O),
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+ *          below 1 MB (for Memory),or below 64 KB (for relocatable I/O).
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+ * ss       is the space code, denoting the address space:
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+ *              00 denotes Configuration Space
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+ *              01 denotes I/O Space
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+ *              10 denotes 32-bit-address Memory Space
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+ *              11 denotes 64-bit-address Memory Space
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+ * bbbbbbbb is the 8-bit Bus Number
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+ * ddddd    is the 5-bit Device Number
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+ * fff      is the 3-bit Function Number
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+ * rrrrrrrr is the 8-bit Register Number
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  */
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+#define OF_PCI_ADDR0_SPACE(ss)		(((ss)&3)<<24)
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+#define OF_PCI_ADDR0_SPACE_CFG		OF_PCI_ADDR0_SPACE(0)
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+#define OF_PCI_ADDR0_SPACE_IO		OF_PCI_ADDR0_SPACE(1)
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+#define OF_PCI_ADDR0_SPACE_MMIO32	OF_PCI_ADDR0_SPACE(2)
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+#define OF_PCI_ADDR0_SPACE_MMIO64	OF_PCI_ADDR0_SPACE(3)
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+#define OF_PCI_ADDR0_SPACE_MASK		OF_PCI_ADDR0_SPACE(3)
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+#define OF_PCI_ADDR0_RELOC		(1UL<<31)
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+#define OF_PCI_ADDR0_PREFETCH		(1UL<<30)
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+#define OF_PCI_ADDR0_ALIAS		(1UL<<29)
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+#define OF_PCI_ADDR0_BUS		0x00FF0000UL
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+#define OF_PCI_ADDR0_DEV		0x0000F800UL
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+#define OF_PCI_ADDR0_FN			0x00000700UL
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+#define OF_PCI_ADDR0_BARREG		0x000000FFUL
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+
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 unsigned int pci_parse_of_flags(u32 addr0, int bridge)
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 {
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-	unsigned int flags = 0;
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+	unsigned int flags = 0, as = addr0 & OF_PCI_ADDR0_SPACE_MASK;
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-	if (addr0 & 0x02000000) {
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+	if (as == OF_PCI_ADDR0_SPACE_MMIO32 || as == OF_PCI_ADDR0_SPACE_MMIO64) {
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 		flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
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-		flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
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-		if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
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-			flags |= IORESOURCE_MEM_64;
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-		flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
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-		if (addr0 & 0x40000000)
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-			flags |= IORESOURCE_PREFETCH
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-				 | PCI_BASE_ADDRESS_MEM_PREFETCH;
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+
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+		if (as == OF_PCI_ADDR0_SPACE_MMIO64)
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+			flags |= PCI_BASE_ADDRESS_MEM_TYPE_64 | IORESOURCE_MEM_64;
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+
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+		if (addr0 & OF_PCI_ADDR0_ALIAS)
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+			flags |= PCI_BASE_ADDRESS_MEM_TYPE_1M;
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+
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+		if (addr0 & OF_PCI_ADDR0_PREFETCH)
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+			flags |= IORESOURCE_PREFETCH |
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+				 PCI_BASE_ADDRESS_MEM_PREFETCH;
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+
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 		/* Note: We don't know whether the ROM has been left enabled
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 		 * by the firmware or not. We mark it as disabled (ie, we do
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 		 * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
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 		 * do a config space read, it will be force-enabled if needed
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 		 */
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-		if (!bridge && (addr0 & 0xff) == 0x30)
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+		if (!bridge && (addr0 & OF_PCI_ADDR0_BARREG) == PCI_ROM_ADDRESS)
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 			flags |= IORESOURCE_READONLY;
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-	} else if (addr0 & 0x01000000)
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+
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+	} else if (as == OF_PCI_ADDR0_SPACE_IO)
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 		flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
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+
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 	if (flags)
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 		flags |= IORESOURCE_SIZEALIGN;
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+
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 	return flags;
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 }
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@@ -135,16 +176,13 @@
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 				 struct pci_bus *bus, int devfn)
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 {
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 	struct pci_dev *dev;
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-	const char *type;
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 	dev = pci_alloc_dev(bus);
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 	if (!dev)
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 		return NULL;
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-	type = of_get_property(node, "device_type", NULL);
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-	if (type == NULL)
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-		type = "";
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-	pr_debug("    create device, devfn: %x, type: %s\n", devfn, type);
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+	pr_debug("    create device, devfn: %x, type: %s\n", devfn,
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+		 of_node_get_device_type(node));
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 	dev->dev.of_node = of_node_get(node);
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 	dev->dev.parent = bus->bridge;
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@@ -177,12 +215,12 @@
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 	/* Early fixups, before probing the BARs */
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 	pci_fixup_device(pci_fixup_early, dev);
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-	if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
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+	if (of_node_is_type(node, "pci") || of_node_is_type(node, "pciex")) {
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 		/* a PCI-PCI bridge */
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 		dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
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 		dev->rom_base_reg = PCI_ROM_ADDRESS1;
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 		set_pcie_hotplug_bridge(dev);
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-	} else if (!strcmp(type, "cardbus")) {
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+	} else if (of_node_is_type(node, "cardbus")) {
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 		dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
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 	} else {
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 		dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
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@@ -376,7 +414,6 @@
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 	 */
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 	if (!rescan_existing)
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 		pcibios_setup_bus_self(bus);
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-	pcibios_setup_bus_devices(bus);
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 	/* Now scan child busses */
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 	for_each_pci_bridge(dev, bus)