enable docker ppp

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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/parisc/kernel/cache.c
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@@ -24,31 +24,38 @@
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 #include <asm/cacheflush.h>
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 #include <asm/tlbflush.h>
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 #include <asm/page.h>
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-#include <asm/pgalloc.h>
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 #include <asm/processor.h>
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 #include <asm/sections.h>
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 #include <asm/shmparam.h>
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30
 
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-int split_tlb __read_mostly;
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-int dcache_stride __read_mostly;
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-int icache_stride __read_mostly;
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+int split_tlb __ro_after_init;
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+int dcache_stride __ro_after_init;
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+int icache_stride __ro_after_init;
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 EXPORT_SYMBOL(dcache_stride);
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35
 
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 void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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 EXPORT_SYMBOL(flush_dcache_page_asm);
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+void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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 void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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40
 
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41
 
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-/* On some machines (e.g. ones with the Merced bus), there can be
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+/* On some machines (i.e., ones with the Merced bus), there can be
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  * only a single PxTLB broadcast at a time; this must be guaranteed
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- * by software.  We put a spinlock around all TLB flushes  to
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- * ensure this.
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+ * by software. We need a spinlock around all TLB flushes to ensure
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+ * this.
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  */
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-DEFINE_SPINLOCK(pa_tlb_lock);
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+DEFINE_SPINLOCK(pa_tlb_flush_lock);
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-struct pdc_cache_info cache_info __read_mostly;
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+/* Swapper page setup lock. */
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+DEFINE_SPINLOCK(pa_swapper_pg_lock);
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+
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+#if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
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+int pa_serialize_tlb_flushes __ro_after_init;
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+#endif
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+
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+struct pdc_cache_info cache_info __ro_after_init;
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 #ifndef CONFIG_PA20
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-static struct pdc_btlb_info btlb_info __read_mostly;
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+static struct pdc_btlb_info btlb_info __ro_after_init;
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 #endif
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60
 
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 #ifdef CONFIG_SMP
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@@ -76,9 +83,9 @@
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 #define pfn_va(pfn)	__va(PFN_PHYS(pfn))
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84
 
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 void
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-update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
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+__update_cache(pte_t pte)
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 {
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-	unsigned long pfn = pte_pfn(*ptep);
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+	unsigned long pfn = pte_pfn(pte);
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 	struct page *page;
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90
 
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 	/* We don't have pte special.  As a result, we can be called with
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@@ -303,6 +310,17 @@
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 	preempt_enable();
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 }
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312
 
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+static inline void
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+__purge_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
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+		   unsigned long physaddr)
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+{
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+	preempt_disable();
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+	purge_dcache_page_asm(physaddr, vmaddr);
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+	if (vma->vm_flags & VM_EXEC)
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+		flush_icache_page_asm(physaddr, vmaddr);
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+	preempt_enable();
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+}
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+
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 void flush_dcache_page(struct page *page)
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 {
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 	struct address_space *mapping = page_mapping_file(page);
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@@ -346,7 +364,7 @@
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 		if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))
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 				      != (addr & (SHM_COLOUR - 1))) {
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 			__flush_cache_page(mpnt, addr, page_to_phys(page));
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-			if (old_addr)
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+			if (parisc_requires_coherency() && old_addr)
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 				printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %pD\n", old_addr, addr, mpnt->vm_file);
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 			old_addr = addr;
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 		}
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@@ -362,15 +380,15 @@
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 EXPORT_SYMBOL(flush_kernel_icache_range_asm);
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381
 
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 #define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
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-static unsigned long parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
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+static unsigned long parisc_cache_flush_threshold __ro_after_init = FLUSH_THRESHOLD;
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384
 
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-#define FLUSH_TLB_THRESHOLD (2*1024*1024) /* 2MB initial TLB threshold */
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-static unsigned long parisc_tlb_flush_threshold __read_mostly = FLUSH_TLB_THRESHOLD;
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+#define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
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+static unsigned long parisc_tlb_flush_threshold __ro_after_init = ~0UL;
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387
 
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 void __init parisc_setup_cache_timing(void)
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 {
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 	unsigned long rangetime, alltime;
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-	unsigned long size, start;
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+	unsigned long size;
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 	unsigned long threshold;
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393
 
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 	alltime = mfctl(16);
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@@ -404,28 +422,28 @@
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 		goto set_tlb_threshold;
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 	}
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424
 
425
+	size = (unsigned long)_end - (unsigned long)_text;
426
+	rangetime = mfctl(16);
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+	flush_tlb_kernel_range((unsigned long)_text, (unsigned long)_end);
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+	rangetime = mfctl(16) - rangetime;
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+
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 	alltime = mfctl(16);
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 	flush_tlb_all();
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 	alltime = mfctl(16) - alltime;
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433
 
411
-	size = 0;
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-	start = (unsigned long) _text;
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-	rangetime = mfctl(16);
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-	while (start < (unsigned long) _end) {
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-		flush_tlb_kernel_range(start, start + PAGE_SIZE);
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-		start += PAGE_SIZE;
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-		size += PAGE_SIZE;
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-	}
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-	rangetime = mfctl(16) - rangetime;
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-
421
-	printk(KERN_DEBUG "Whole TLB flush %lu cycles, flushing %lu bytes %lu cycles\n",
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+	printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",
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 		alltime, size, rangetime);
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436
 
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-	threshold = PAGE_ALIGN(num_online_cpus() * size * alltime / rangetime);
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+	threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);
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+	printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",
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+		threshold/1024);
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440
 
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 set_tlb_threshold:
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-	if (threshold)
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+	if (threshold > FLUSH_TLB_THRESHOLD)
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 		parisc_tlb_flush_threshold = threshold;
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+	else
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+		parisc_tlb_flush_threshold = FLUSH_TLB_THRESHOLD;
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+
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 	printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",
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 		parisc_tlb_flush_threshold/1024);
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 }
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@@ -477,18 +495,6 @@
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 	/* Purge TLB entries for small ranges using the pdtlb and
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 	   pitlb instructions.  These instructions execute locally
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 	   but cause a purge request to be broadcast to other TLBs.  */
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-	if (likely(!split_tlb)) {
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-		while (start < end) {
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-			purge_tlb_start(flags);
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-			mtsp(sid, 1);
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-			pdtlb(start);
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-			purge_tlb_end(flags);
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-			start += PAGE_SIZE;
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-		}
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-		return 0;
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-	}
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-
491
-	/* split TLB case */
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 	while (start < end) {
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 		purge_tlb_start(flags);
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 		mtsp(sid, 1);
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@@ -525,11 +531,14 @@
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 	pte_t *ptep = NULL;
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532
 
527
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 	if (!pgd_none(*pgd)) {
528
-		pud_t *pud = pud_offset(pgd, addr);
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-		if (!pud_none(*pud)) {
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-			pmd_t *pmd = pmd_offset(pud, addr);
531
-			if (!pmd_none(*pmd))
532
-				ptep = pte_offset_map(pmd, addr);
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+		p4d_t *p4d = p4d_offset(pgd, addr);
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+		if (!p4d_none(*p4d)) {
536
+			pud_t *pud = pud_offset(p4d, addr);
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+			if (!pud_none(*pud)) {
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+				pmd_t *pmd = pmd_offset(pud, addr);
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+				if (!pmd_none(*pmd))
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+					ptep = pte_offset_map(pmd, addr);
541
+			}
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542
 		}
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 	}
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 	return ptep;
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@@ -573,9 +582,12 @@
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 			pfn = pte_pfn(*ptep);
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583
 			if (!pfn_valid(pfn))
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584
 				continue;
576
-			if (unlikely(mm->context))
585
+			if (unlikely(mm->context)) {
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 				flush_tlb_page(vma, addr);
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-			__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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+				__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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+			} else {
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+				__purge_cache_page(vma, addr, PFN_PHYS(pfn));
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+			}
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 		}
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 	}
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 }
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@@ -610,9 +622,12 @@
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 			continue;
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 		pfn = pte_pfn(*ptep);
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 		if (pfn_valid(pfn)) {
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-			if (unlikely(vma->vm_mm->context))
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+			if (unlikely(vma->vm_mm->context)) {
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 				flush_tlb_page(vma, addr);
615
-			__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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+				__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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+			} else {
629
+				__purge_cache_page(vma, addr, PFN_PHYS(pfn));
630
+			}
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 		}
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 	}
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 }
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@@ -621,9 +636,12 @@
621
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 flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
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 {
623
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 	if (pfn_valid(pfn)) {
624
-		if (likely(vma->vm_mm->context))
639
+		if (likely(vma->vm_mm->context)) {
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 			flush_tlb_page(vma, vmaddr);
626
-		__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
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+			__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
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+		} else {
643
+			__purge_cache_page(vma, vmaddr, PFN_PHYS(pfn));
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+		}
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 	}
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 }
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