enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/parisc/include/asm/pdcpat.h
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@@ -67,6 +67,10 @@
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 #define PDC_PAT_CHASSIS_READ_LOG     	1L /* Read  Log Entry */
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+/* PDC PAT COMPLEX */
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+
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+#define PDC_PAT_COMPLEX			66L
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+
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 /* PDC PAT CPU  -- CPU configuration within the protection domain */
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 #define PDC_PAT_CPU                	67L
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@@ -173,6 +177,16 @@
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 /* PDC PAT PD */
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 #define PDC_PAT_PD		74L         /* Protection Domain Info   */
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 #define PDC_PAT_PD_GET_ADDR_MAP		0L  /* Get Address Map          */
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+#define PDC_PAT_PD_GET_PDC_INTERF_REV	1L  /* Get PDC Interface Revisions */
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+
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+#define PDC_PAT_CAPABILITY_BIT_PDC_SERIALIZE	(1UL << 0)
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+#define PDC_PAT_CAPABILITY_BIT_PDC_POLLING	(1UL << 1)
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+#define PDC_PAT_CAPABILITY_BIT_PDC_NBC		(1UL << 2) /* non-blocking calls */
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+#define PDC_PAT_CAPABILITY_BIT_PDC_UFO		(1UL << 3)
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+#define PDC_PAT_CAPABILITY_BIT_PDC_IODC_32	(1UL << 4)
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+#define PDC_PAT_CAPABILITY_BIT_PDC_IODC_64	(1UL << 5)
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+#define PDC_PAT_CAPABILITY_BIT_PDC_HPMC_RENDEZ	(1UL << 6)
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+#define PDC_PAT_CAPABILITY_BIT_SIMULTANEOUS_PTLB (1UL << 7)
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 /* PDC_PAT_PD_GET_ADDR_MAP entry types */
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 #define PAT_MEMORY_DESCRIPTOR		1   
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@@ -186,6 +200,14 @@
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 #define PAT_MEMUSE_GI			128
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 #define PAT_MEMUSE_GNI			129
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+/* PDC PAT REGISTER TOC */
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+#define PDC_PAT_REGISTER_TOC	75L
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+#define PDC_PAT_TOC_REGISTER_VECTOR	0L /* Register TOC Vector */
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+#define PDC_PAT_TOC_READ_VECTOR		1L /* Read TOC Vector     */
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+
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+/* PDC PAT SYSTEM_INFO */
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+#define PDC_PAT_SYSTEM_INFO	76L
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+/* PDC_PAT_SYSTEM_INFO uses the same options as PDC_SYSTEM_INFO function. */
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 #ifndef __ASSEMBLY__
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 #include <linux/types.h>
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@@ -297,18 +319,29 @@
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 ** PDC_PAT_CELL_GET_INFO return block
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 */
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 typedef struct pdc_pat_cell_info_rtn_block {
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-	unsigned long cpu_info;
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-	unsigned long cell_info;
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-	unsigned long cell_location;
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-	unsigned long reo_location;
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-	unsigned long mem_size;
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-	unsigned long dimm_status;
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 	unsigned long pdc_rev;
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-	unsigned long fabric_info0;
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-	unsigned long fabric_info1;
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-	unsigned long fabric_info2;
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-	unsigned long fabric_info3;
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-	unsigned long reserved[21];
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+	unsigned long capabilities; /* see PDC_PAT_CAPABILITY_BIT_* */
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+	unsigned long reserved0[2];
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+	unsigned long cell_info;	/* 0x20 */
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+	unsigned long cell_phys_location;
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+	unsigned long cpu_info;
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+	unsigned long cpu_speed;
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+	unsigned long io_chassis_phys_location;
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+	unsigned long cell_io_information;
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+	unsigned long reserved1[2];
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+	unsigned long io_slot_info_size; /* 0x60 */
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+	struct {
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+		unsigned long header, info0, info1;
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+		unsigned long phys_loc, hw_path;
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+	} io_slot[16];
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+	unsigned long cell_mem_size;	/* 0x2e8 */
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+	unsigned long cell_dimm_info_size;
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+	unsigned long dimm_info[16];
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+	unsigned long fabric_info_size;	/* 0x3f8 */
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+	struct {			/* 0x380 */
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+		unsigned long fabric_info_xbc_port;
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+		unsigned long rc_attached_to_xbc;
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+	} xbc[8*4];
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 } pdc_pat_cell_info_rtn_block_t;
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@@ -326,12 +359,19 @@
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 extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
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 extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
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-extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc, unsigned long mod, unsigned long view_type, void *mem_addr);
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+extern int pdc_pat_cell_info(struct pdc_pat_cell_info_rtn_block *info,
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+		unsigned long *actcnt, unsigned long offset,
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+		unsigned long cell_number);
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+extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc,
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+		unsigned long mod, unsigned long view_type, void *mem_addr);
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 extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
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 extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, unsigned long hpa);
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-extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr, unsigned long count, unsigned long offset);
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+extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr,
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+		unsigned long count, unsigned long offset);
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+extern int pdc_pat_pd_get_pdc_revisions(unsigned long *legacy_rev,
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+		unsigned long *pat_rev, unsigned long *pdc_cap);
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 extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val); 
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 extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val);