enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/nds32/kernel/head.S
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@@ -3,11 +3,11 @@
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 #include <linux/linkage.h>
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 #include <linux/init.h>
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+#include <linux/pgtable.h>
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 #include <asm/ptrace.h>
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 #include <asm/asm-offsets.h>
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 #include <asm/page.h>
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-#include <asm/pgtable.h>
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-#include <asm/sizes.h>
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+#include <linux/sizes.h>
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 #include <asm/thread_info.h>
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 #ifdef CONFIG_CPU_BIG_ENDIAN
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@@ -123,21 +123,12 @@
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         andi    $r0, $r0, MMU_CFG_mskTBS
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         srli    $r6, $r6, MMU_CFG_offTBW
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         srli    $r0, $r0, MMU_CFG_offTBS
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-        /*
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-         * we just map the kernel to the maximum way - 1 of tlb
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-         * reserver one way for UART VA mapping
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-         * it will cause page fault if UART mapping cover the kernel mapping
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-         *
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-         * direct mapping is not supported now.
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-         */
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-        li      $r2, 't'
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-        beqz    $r6, __error                 ! MMU_CFG.TBW = 0 is direct mappin
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+	addi    $r6, $r6, #0x1               ! MMU_CFG.TBW value -> meaning
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         addi    $r0, $r0, #0x2               ! MMU_CFG.TBS value -> meaning
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         sll     $r0, $r6, $r0                ! entries = k-way * n-set
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         mul     $r6, $r0, $r5                ! max size = entries * page size
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         /* check kernel image size */
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         la      $r3, (_end - PAGE_OFFSET)
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-        li      $r2, 's'
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         bgt     $r3, $r6, __error
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 	li      $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr)
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@@ -160,7 +151,7 @@
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 #endif
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 	mtsr    $r3, $TLB_MISC
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-	mfsr    $r0, $MISC_CTL      ! Enable BTB and RTP and shadow sp
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+	mfsr    $r0, $MISC_CTL      ! Enable BTB, RTP, shadow sp, and HW_PRE
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 	ori     $r0, $r0, #MISC_init
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 	mtsr    $r0, $MISC_CTL
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