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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/arch/arm64/include/asm/kvm_host.h
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2012,2013 - ARM Ltd
34  * Author: Marc Zyngier <marc.zyngier@arm.com>
....@@ -5,31 +6,26 @@
56  * Derived from arch/arm/include/asm/kvm_host.h:
67  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
78  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
8
- *
9
- * This program is free software; you can redistribute it and/or modify
10
- * it under the terms of the GNU General Public License version 2 as
11
- * published by the Free Software Foundation.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- * GNU General Public License for more details.
17
- *
18
- * You should have received a copy of the GNU General Public License
19
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
209  */
2110 
2211 #ifndef __ARM64_KVM_HOST_H__
2312 #define __ARM64_KVM_HOST_H__
2413 
14
+#include <linux/arm-smccc.h>
15
+#include <linux/bitmap.h>
2516 #include <linux/types.h>
17
+#include <linux/jump_label.h>
2618 #include <linux/kvm_types.h>
19
+#include <linux/percpu.h>
20
+#include <linux/psci.h>
21
+#include <asm/arch_gicv3.h>
22
+#include <asm/barrier.h>
2723 #include <asm/cpufeature.h>
24
+#include <asm/cputype.h>
2825 #include <asm/daifflags.h>
2926 #include <asm/fpsimd.h>
3027 #include <asm/kvm.h>
3128 #include <asm/kvm_asm.h>
32
-#include <asm/kvm_mmio.h>
3329 #include <asm/thread_info.h>
3430 
3531 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
....@@ -43,33 +39,73 @@
4339 
4440 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
4541 
46
-#define KVM_VCPU_MAX_FEATURES 4
42
+#define KVM_VCPU_MAX_FEATURES 7
4743 
4844 #define KVM_REQ_SLEEP \
4945 	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
5046 #define KVM_REQ_IRQ_PENDING	KVM_ARCH_REQ(1)
5147 #define KVM_REQ_VCPU_RESET	KVM_ARCH_REQ(2)
48
+#define KVM_REQ_RECORD_STEAL	KVM_ARCH_REQ(3)
49
+#define KVM_REQ_RELOAD_GICv4	KVM_ARCH_REQ(4)
50
+
51
+#define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
52
+				     KVM_DIRTY_LOG_INITIALLY_SET)
53
+
54
+/*
55
+ * Mode of operation configurable with kvm-arm.mode early param.
56
+ * See Documentation/admin-guide/kernel-parameters.txt for more information.
57
+ */
58
+enum kvm_mode {
59
+	KVM_MODE_DEFAULT,
60
+	KVM_MODE_PROTECTED,
61
+};
62
+enum kvm_mode kvm_get_mode(void);
5263 
5364 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
5465 
66
+extern unsigned int kvm_sve_max_vl;
67
+int kvm_arm_init_sve(void);
68
+
5569 int __attribute_const__ kvm_target_cpu(void);
5670 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
57
-int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
58
-void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
71
+void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
5972 
60
-struct kvm_arch {
73
+struct kvm_vmid {
6174 	/* The VMID generation used for the virt. memory system */
6275 	u64    vmid_gen;
6376 	u32    vmid;
77
+};
6478 
65
-	/* 1-level 2nd stage table, protected by kvm->mmu_lock */
66
-	pgd_t *pgd;
79
+struct kvm_s2_mmu {
80
+	struct kvm_vmid vmid;
6781 
68
-	/* VTTBR value associated with above pgd and vmid */
69
-	u64    vttbr;
82
+	/*
83
+	 * stage2 entry level table
84
+	 *
85
+	 * Two kvm_s2_mmu structures in the same VM can point to the same
86
+	 * pgd here.  This happens when running a guest using a
87
+	 * translation regime that isn't affected by its own stage-2
88
+	 * translation, such as a non-VHE hypervisor running at vEL2, or
89
+	 * for vEL1/EL0 with vHCR_EL2.VM == 0.  In that case, we use the
90
+	 * canonical stage-2 page tables.
91
+	 */
92
+	phys_addr_t	pgd_phys;
93
+	struct kvm_pgtable *pgt;
7094 
7195 	/* The last vcpu id that ran on each physical CPU */
7296 	int __percpu *last_vcpu_ran;
97
+
98
+	struct kvm_arch *arch;
99
+};
100
+
101
+struct kvm_arch_memory_slot {
102
+};
103
+
104
+struct kvm_arch {
105
+	struct kvm_s2_mmu mmu;
106
+
107
+	/* VTCR_EL2 value for this VM */
108
+	u64    vtcr;
73109 
74110 	/* The maximum number of vCPUs depends on the used GIC model */
75111 	int max_vcpus;
....@@ -79,17 +115,24 @@
79115 
80116 	/* Mandated version of PSCI */
81117 	u32 psci_version;
82
-};
83118 
84
-#define KVM_NR_MEM_OBJS     40
119
+	/*
120
+	 * If we encounter a data abort without valid instruction syndrome
121
+	 * information, report this to user space.  User space can (and
122
+	 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
123
+	 * supported.
124
+	 */
125
+	bool return_nisv_io_abort_to_user;
85126 
86
-/*
87
- * We don't want allocation failures within the mmu code, so we preallocate
88
- * enough memory for a single page fault in a cache.
89
- */
90
-struct kvm_mmu_memory_cache {
91
-	int nobjs;
92
-	void *objects[KVM_NR_MEM_OBJS];
127
+	/*
128
+	 * VM-wide PMU filter, implemented as a bitmap and big enough for
129
+	 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
130
+	 */
131
+	unsigned long *pmu_filter;
132
+	unsigned int pmuver;
133
+
134
+	u8 pfr0_csv2;
135
+	u8 pfr0_csv3;
93136 };
94137 
95138 struct kvm_vcpu_fault_info {
....@@ -99,17 +142,14 @@
99142 	u64 disr_el1;		/* Deferred [SError] Status Register */
100143 };
101144 
102
-/*
103
- * 0 is reserved as an invalid value.
104
- * Order should be kept in sync with the save/restore code.
105
- */
106145 enum vcpu_sysreg {
107
-	__INVALID_SYSREG__,
146
+	__INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
108147 	MPIDR_EL1,	/* MultiProcessor Affinity Register */
109148 	CSSELR_EL1,	/* Cache Size Selection Register */
110149 	SCTLR_EL1,	/* System Control Register */
111150 	ACTLR_EL1,	/* Auxiliary Control Register */
112151 	CPACR_EL1,	/* Coprocessor Access Control */
152
+	ZCR_EL1,	/* SVE Control */
113153 	TTBR0_EL1,	/* Translation Table Base Register 0 */
114154 	TTBR1_EL1,	/* Translation Table Base Register 1 */
115155 	TCR_EL1,	/* Translation Control Register */
....@@ -145,6 +185,28 @@
145185 	PMSWINC_EL0,	/* Software Increment Register */
146186 	PMUSERENR_EL0,	/* User Enable Register */
147187 
188
+	/* Pointer Authentication Registers in a strict increasing order. */
189
+	APIAKEYLO_EL1,
190
+	APIAKEYHI_EL1,
191
+	APIBKEYLO_EL1,
192
+	APIBKEYHI_EL1,
193
+	APDAKEYLO_EL1,
194
+	APDAKEYHI_EL1,
195
+	APDBKEYLO_EL1,
196
+	APDBKEYHI_EL1,
197
+	APGAKEYLO_EL1,
198
+	APGAKEYHI_EL1,
199
+
200
+	ELR_EL1,
201
+	SP_EL1,
202
+	SPSR_EL1,
203
+
204
+	CNTVOFF_EL2,
205
+	CNTV_CVAL_EL0,
206
+	CNTV_CTL_EL0,
207
+	CNTP_CVAL_EL0,
208
+	CNTP_CTL_EL0,
209
+
148210 	/* 32bit specific registers. Keep them at the end of the range */
149211 	DACR32_EL2,	/* Domain Access Control Register */
150212 	IFSR32_EL2,	/* Instruction Fault Status Register */
....@@ -154,60 +216,52 @@
154216 	NR_SYS_REGS	/* Nothing after this line! */
155217 };
156218 
157
-/* 32bit mapping */
158
-#define c0_MPIDR	(MPIDR_EL1 * 2)	/* MultiProcessor ID Register */
159
-#define c0_CSSELR	(CSSELR_EL1 * 2)/* Cache Size Selection Register */
160
-#define c1_SCTLR	(SCTLR_EL1 * 2)	/* System Control Register */
161
-#define c1_ACTLR	(ACTLR_EL1 * 2)	/* Auxiliary Control Register */
162
-#define c1_CPACR	(CPACR_EL1 * 2)	/* Coprocessor Access Control */
163
-#define c2_TTBR0	(TTBR0_EL1 * 2)	/* Translation Table Base Register 0 */
164
-#define c2_TTBR0_high	(c2_TTBR0 + 1)	/* TTBR0 top 32 bits */
165
-#define c2_TTBR1	(TTBR1_EL1 * 2)	/* Translation Table Base Register 1 */
166
-#define c2_TTBR1_high	(c2_TTBR1 + 1)	/* TTBR1 top 32 bits */
167
-#define c2_TTBCR	(TCR_EL1 * 2)	/* Translation Table Base Control R. */
168
-#define c2_TTBCR2	(c2_TTBCR + 1)	/* Translation Table Base Control R. 2 */
169
-#define c3_DACR		(DACR32_EL2 * 2)/* Domain Access Control Register */
170
-#define c5_DFSR		(ESR_EL1 * 2)	/* Data Fault Status Register */
171
-#define c5_IFSR		(IFSR32_EL2 * 2)/* Instruction Fault Status Register */
172
-#define c5_ADFSR	(AFSR0_EL1 * 2)	/* Auxiliary Data Fault Status R */
173
-#define c5_AIFSR	(AFSR1_EL1 * 2)	/* Auxiliary Instr Fault Status R */
174
-#define c6_DFAR		(FAR_EL1 * 2)	/* Data Fault Address Register */
175
-#define c6_IFAR		(c6_DFAR + 1)	/* Instruction Fault Address Register */
176
-#define c7_PAR		(PAR_EL1 * 2)	/* Physical Address Register */
177
-#define c7_PAR_high	(c7_PAR + 1)	/* PAR top 32 bits */
178
-#define c10_PRRR	(MAIR_EL1 * 2)	/* Primary Region Remap Register */
179
-#define c10_NMRR	(c10_PRRR + 1)	/* Normal Memory Remap Register */
180
-#define c12_VBAR	(VBAR_EL1 * 2)	/* Vector Base Address Register */
181
-#define c13_CID		(CONTEXTIDR_EL1 * 2)	/* Context ID Register */
182
-#define c13_TID_URW	(TPIDR_EL0 * 2)	/* Thread ID, User R/W */
183
-#define c13_TID_URO	(TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
184
-#define c13_TID_PRIV	(TPIDR_EL1 * 2)	/* Thread ID, Privileged */
185
-#define c10_AMAIR0	(AMAIR_EL1 * 2)	/* Aux Memory Attr Indirection Reg */
186
-#define c10_AMAIR1	(c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
187
-#define c14_CNTKCTL	(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
188
-
189
-#define cp14_DBGDSCRext	(MDSCR_EL1 * 2)
190
-#define cp14_DBGBCR0	(DBGBCR0_EL1 * 2)
191
-#define cp14_DBGBVR0	(DBGBVR0_EL1 * 2)
192
-#define cp14_DBGBXVR0	(cp14_DBGBVR0 + 1)
193
-#define cp14_DBGWCR0	(DBGWCR0_EL1 * 2)
194
-#define cp14_DBGWVR0	(DBGWVR0_EL1 * 2)
195
-#define cp14_DBGDCCINT	(MDCCINT_EL1 * 2)
196
-#define cp14_DBGVCR	(DBGVCR32_EL2 * 2)
197
-
198
-#define NR_COPRO_REGS	(NR_SYS_REGS * 2)
199
-
200219 struct kvm_cpu_context {
201
-	struct kvm_regs	gp_regs;
202
-	union {
203
-		u64 sys_regs[NR_SYS_REGS];
204
-		u32 copro[NR_COPRO_REGS];
205
-	};
220
+	struct user_pt_regs regs;	/* sp = sp_el0 */
221
+
222
+	u64	spsr_abt;
223
+	u64	spsr_und;
224
+	u64	spsr_irq;
225
+	u64	spsr_fiq;
226
+
227
+	struct user_fpsimd_state fp_regs;
228
+
229
+	u64 sys_regs[NR_SYS_REGS];
206230 
207231 	struct kvm_vcpu *__hyp_running_vcpu;
208232 };
209233 
210
-typedef struct kvm_cpu_context kvm_cpu_context_t;
234
+struct kvm_pmu_events {
235
+	u32 events_host;
236
+	u32 events_guest;
237
+};
238
+
239
+struct kvm_host_data {
240
+	struct kvm_cpu_context host_ctxt;
241
+	struct kvm_pmu_events pmu_events;
242
+};
243
+
244
+struct kvm_host_psci_config {
245
+	/* PSCI version used by host. */
246
+	u32 version;
247
+
248
+	/* Function IDs used by host if version is v0.1. */
249
+	struct psci_0_1_function_ids function_ids_0_1;
250
+
251
+	bool psci_0_1_cpu_suspend_implemented;
252
+	bool psci_0_1_cpu_on_implemented;
253
+	bool psci_0_1_cpu_off_implemented;
254
+	bool psci_0_1_migrate_implemented;
255
+};
256
+
257
+extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
258
+#define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
259
+
260
+extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
261
+#define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
262
+
263
+extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
264
+#define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
211265 
212266 struct vcpu_reset_state {
213267 	unsigned long	pc;
....@@ -218,6 +272,11 @@
218272 
219273 struct kvm_vcpu_arch {
220274 	struct kvm_cpu_context ctxt;
275
+	void *sve_state;
276
+	unsigned int sve_max_vl;
277
+
278
+	/* Stage 2 paging state used by the hardware on next switch */
279
+	struct kvm_s2_mmu *hw_mmu;
221280 
222281 	/* HYP configuration */
223282 	u64 hcr_el2;
....@@ -249,9 +308,6 @@
249308 	struct kvm_guest_debug_arch vcpu_debug_state;
250309 	struct kvm_guest_debug_arch external_debug_state;
251310 
252
-	/* Pointer to host CPU context */
253
-	kvm_cpu_context_t *host_cpu_context;
254
-
255311 	struct thread_info *host_thread_info;	/* hyp VA */
256312 	struct user_fpsimd_state *host_fpsimd_state;	/* hyp VA */
257313 
....@@ -260,6 +316,8 @@
260316 		struct kvm_guest_debug_arch regs;
261317 		/* Statistical profiling extension */
262318 		u64 pmscr_el1;
319
+		/* Self-hosted trace */
320
+		u64 trfcr_el1;
263321 	} host_debug_state;
264322 
265323 	/* VGIC state */
....@@ -289,9 +347,6 @@
289347 	/* Don't run the guest (internal implementation need) */
290348 	bool pause;
291349 
292
-	/* IO related fields */
293
-	struct kvm_decode mmio_decode;
294
-
295350 	/* Cache some mmu pages needed inside spinlock regions */
296351 	struct kvm_mmu_memory_cache mmu_page_cache;
297352 
....@@ -309,9 +364,35 @@
309364 	struct vcpu_reset_state	reset_state;
310365 
311366 	/* True when deferrable sysregs are loaded on the physical CPU,
312
-	 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
367
+	 * see kvm_vcpu_load_sysregs_vhe and kvm_vcpu_put_sysregs_vhe. */
313368 	bool sysregs_loaded_on_cpu;
369
+
370
+	/* Guest PV state */
371
+	struct {
372
+		u64 last_steal;
373
+		gpa_t base;
374
+	} steal;
314375 };
376
+
377
+/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
378
+#define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) +	\
379
+			     sve_ffr_offset((vcpu)->arch.sve_max_vl))
380
+
381
+#define vcpu_sve_max_vq(vcpu)	sve_vq_from_vl((vcpu)->arch.sve_max_vl)
382
+
383
+#define vcpu_sve_state_size(vcpu) ({					\
384
+	size_t __size_ret;						\
385
+	unsigned int __vcpu_vq;						\
386
+									\
387
+	if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) {		\
388
+		__size_ret = 0;						\
389
+	} else {							\
390
+		__vcpu_vq = vcpu_sve_max_vq(vcpu);			\
391
+		__size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq);		\
392
+	}								\
393
+									\
394
+	__size_ret;							\
395
+})
315396 
316397 /* vcpu_arch flags field values: */
317398 #define KVM_ARM64_DEBUG_DIRTY		(1 << 0)
....@@ -319,28 +400,157 @@
319400 #define KVM_ARM64_FP_HOST		(1 << 2) /* host FP regs loaded */
320401 #define KVM_ARM64_HOST_SVE_IN_USE	(1 << 3) /* backup for host TIF_SVE */
321402 #define KVM_ARM64_HOST_SVE_ENABLED	(1 << 4) /* SVE enabled for EL0 */
322
-
323
-#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.gp_regs)
403
+#define KVM_ARM64_GUEST_HAS_SVE		(1 << 5) /* SVE exposed to guest */
404
+#define KVM_ARM64_VCPU_SVE_FINALIZED	(1 << 6) /* SVE config completed */
405
+#define KVM_ARM64_GUEST_HAS_PTRAUTH	(1 << 7) /* PTRAUTH exposed to guest */
406
+#define KVM_ARM64_PENDING_EXCEPTION	(1 << 8) /* Exception pending */
407
+#define KVM_ARM64_EXCEPT_MASK		(7 << 9) /* Target EL/MODE */
408
+#define KVM_ARM64_DEBUG_STATE_SAVE_SPE	(1 << 12) /* Save SPE context if active  */
409
+#define KVM_ARM64_DEBUG_STATE_SAVE_TRBE	(1 << 13) /* Save TRBE context if active  */
324410 
325411 /*
326
- * Only use __vcpu_sys_reg if you know you want the memory backed version of a
327
- * register, and not the one most recently accessed by a running VCPU.  For
328
- * example, for userspace access or for system registers that are never context
329
- * switched, but only emulated.
412
+ * When KVM_ARM64_PENDING_EXCEPTION is set, KVM_ARM64_EXCEPT_MASK can
413
+ * take the following values:
414
+ *
415
+ * For AArch32 EL1:
330416  */
331
-#define __vcpu_sys_reg(v,r)	((v)->arch.ctxt.sys_regs[(r)])
417
+#define KVM_ARM64_EXCEPT_AA32_UND	(0 << 9)
418
+#define KVM_ARM64_EXCEPT_AA32_IABT	(1 << 9)
419
+#define KVM_ARM64_EXCEPT_AA32_DABT	(2 << 9)
420
+/* For AArch64: */
421
+#define KVM_ARM64_EXCEPT_AA64_ELx_SYNC	(0 << 9)
422
+#define KVM_ARM64_EXCEPT_AA64_ELx_IRQ	(1 << 9)
423
+#define KVM_ARM64_EXCEPT_AA64_ELx_FIQ	(2 << 9)
424
+#define KVM_ARM64_EXCEPT_AA64_ELx_SERR	(3 << 9)
425
+#define KVM_ARM64_EXCEPT_AA64_EL1	(0 << 11)
426
+#define KVM_ARM64_EXCEPT_AA64_EL2	(1 << 11)
332427 
333
-u64 vcpu_read_sys_reg(struct kvm_vcpu *vcpu, int reg);
428
+/*
429
+ * Overlaps with KVM_ARM64_EXCEPT_MASK on purpose so that it can't be
430
+ * set together with an exception...
431
+ */
432
+#define KVM_ARM64_INCREMENT_PC		(1 << 9) /* Increment PC */
433
+
434
+#define vcpu_has_sve(vcpu) (system_supports_sve() &&			\
435
+			    ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE))
436
+
437
+#ifdef CONFIG_ARM64_PTR_AUTH
438
+#define vcpu_has_ptrauth(vcpu)						\
439
+	((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||		\
440
+	  cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&		\
441
+	 (vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH)
442
+#else
443
+#define vcpu_has_ptrauth(vcpu)		false
444
+#endif
445
+
446
+#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.regs)
447
+
448
+/*
449
+ * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
450
+ * memory backed version of a register, and not the one most recently
451
+ * accessed by a running VCPU.  For example, for userspace access or
452
+ * for system registers that are never context switched, but only
453
+ * emulated.
454
+ */
455
+#define __ctxt_sys_reg(c,r)	(&(c)->sys_regs[(r)])
456
+
457
+#define ctxt_sys_reg(c,r)	(*__ctxt_sys_reg(c,r))
458
+
459
+#define __vcpu_sys_reg(v,r)	(ctxt_sys_reg(&(v)->arch.ctxt, (r)))
460
+
461
+u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
334462 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
335463 
336
-/*
337
- * CP14 and CP15 live in the same array, as they are backed by the
338
- * same system registers.
339
- */
340
-#define CPx_BIAS		IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)
464
+static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
465
+{
466
+	/*
467
+	 * *** VHE ONLY ***
468
+	 *
469
+	 * System registers listed in the switch are not saved on every
470
+	 * exit from the guest but are only saved on vcpu_put.
471
+	 *
472
+	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
473
+	 * should never be listed below, because the guest cannot modify its
474
+	 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
475
+	 * thread when emulating cross-VCPU communication.
476
+	 */
477
+	if (!has_vhe())
478
+		return false;
341479 
342
-#define vcpu_cp14(v,r)		((v)->arch.ctxt.copro[(r) ^ CPx_BIAS])
343
-#define vcpu_cp15(v,r)		((v)->arch.ctxt.copro[(r) ^ CPx_BIAS])
480
+	switch (reg) {
481
+	case CSSELR_EL1:	*val = read_sysreg_s(SYS_CSSELR_EL1);	break;
482
+	case SCTLR_EL1:		*val = read_sysreg_s(SYS_SCTLR_EL12);	break;
483
+	case CPACR_EL1:		*val = read_sysreg_s(SYS_CPACR_EL12);	break;
484
+	case TTBR0_EL1:		*val = read_sysreg_s(SYS_TTBR0_EL12);	break;
485
+	case TTBR1_EL1:		*val = read_sysreg_s(SYS_TTBR1_EL12);	break;
486
+	case TCR_EL1:		*val = read_sysreg_s(SYS_TCR_EL12);	break;
487
+	case ESR_EL1:		*val = read_sysreg_s(SYS_ESR_EL12);	break;
488
+	case AFSR0_EL1:		*val = read_sysreg_s(SYS_AFSR0_EL12);	break;
489
+	case AFSR1_EL1:		*val = read_sysreg_s(SYS_AFSR1_EL12);	break;
490
+	case FAR_EL1:		*val = read_sysreg_s(SYS_FAR_EL12);	break;
491
+	case MAIR_EL1:		*val = read_sysreg_s(SYS_MAIR_EL12);	break;
492
+	case VBAR_EL1:		*val = read_sysreg_s(SYS_VBAR_EL12);	break;
493
+	case CONTEXTIDR_EL1:	*val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
494
+	case TPIDR_EL0:		*val = read_sysreg_s(SYS_TPIDR_EL0);	break;
495
+	case TPIDRRO_EL0:	*val = read_sysreg_s(SYS_TPIDRRO_EL0);	break;
496
+	case TPIDR_EL1:		*val = read_sysreg_s(SYS_TPIDR_EL1);	break;
497
+	case AMAIR_EL1:		*val = read_sysreg_s(SYS_AMAIR_EL12);	break;
498
+	case CNTKCTL_EL1:	*val = read_sysreg_s(SYS_CNTKCTL_EL12);	break;
499
+	case ELR_EL1:		*val = read_sysreg_s(SYS_ELR_EL12);	break;
500
+	case PAR_EL1:		*val = read_sysreg_par();		break;
501
+	case DACR32_EL2:	*val = read_sysreg_s(SYS_DACR32_EL2);	break;
502
+	case IFSR32_EL2:	*val = read_sysreg_s(SYS_IFSR32_EL2);	break;
503
+	case DBGVCR32_EL2:	*val = read_sysreg_s(SYS_DBGVCR32_EL2);	break;
504
+	default:		return false;
505
+	}
506
+
507
+	return true;
508
+}
509
+
510
+static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
511
+{
512
+	/*
513
+	 * *** VHE ONLY ***
514
+	 *
515
+	 * System registers listed in the switch are not restored on every
516
+	 * entry to the guest but are only restored on vcpu_load.
517
+	 *
518
+	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
519
+	 * should never be listed below, because the MPIDR should only be set
520
+	 * once, before running the VCPU, and never changed later.
521
+	 */
522
+	if (!has_vhe())
523
+		return false;
524
+
525
+	switch (reg) {
526
+	case CSSELR_EL1:	write_sysreg_s(val, SYS_CSSELR_EL1);	break;
527
+	case SCTLR_EL1:		write_sysreg_s(val, SYS_SCTLR_EL12);	break;
528
+	case CPACR_EL1:		write_sysreg_s(val, SYS_CPACR_EL12);	break;
529
+	case TTBR0_EL1:		write_sysreg_s(val, SYS_TTBR0_EL12);	break;
530
+	case TTBR1_EL1:		write_sysreg_s(val, SYS_TTBR1_EL12);	break;
531
+	case TCR_EL1:		write_sysreg_s(val, SYS_TCR_EL12);	break;
532
+	case ESR_EL1:		write_sysreg_s(val, SYS_ESR_EL12);	break;
533
+	case AFSR0_EL1:		write_sysreg_s(val, SYS_AFSR0_EL12);	break;
534
+	case AFSR1_EL1:		write_sysreg_s(val, SYS_AFSR1_EL12);	break;
535
+	case FAR_EL1:		write_sysreg_s(val, SYS_FAR_EL12);	break;
536
+	case MAIR_EL1:		write_sysreg_s(val, SYS_MAIR_EL12);	break;
537
+	case VBAR_EL1:		write_sysreg_s(val, SYS_VBAR_EL12);	break;
538
+	case CONTEXTIDR_EL1:	write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
539
+	case TPIDR_EL0:		write_sysreg_s(val, SYS_TPIDR_EL0);	break;
540
+	case TPIDRRO_EL0:	write_sysreg_s(val, SYS_TPIDRRO_EL0);	break;
541
+	case TPIDR_EL1:		write_sysreg_s(val, SYS_TPIDR_EL1);	break;
542
+	case AMAIR_EL1:		write_sysreg_s(val, SYS_AMAIR_EL12);	break;
543
+	case CNTKCTL_EL1:	write_sysreg_s(val, SYS_CNTKCTL_EL12);	break;
544
+	case ELR_EL1:		write_sysreg_s(val, SYS_ELR_EL12);	break;
545
+	case PAR_EL1:		write_sysreg_s(val, SYS_PAR_EL1);	break;
546
+	case DACR32_EL2:	write_sysreg_s(val, SYS_DACR32_EL2);	break;
547
+	case IFSR32_EL2:	write_sysreg_s(val, SYS_IFSR32_EL2);	break;
548
+	case DBGVCR32_EL2:	write_sysreg_s(val, SYS_DBGVCR32_EL2);	break;
549
+	default:		return false;
550
+	}
551
+
552
+	return true;
553
+}
344554 
345555 struct kvm_vm_stat {
346556 	ulong remote_tlb_flush;
....@@ -349,6 +559,8 @@
349559 struct kvm_vcpu_stat {
350560 	u64 halt_successful_poll;
351561 	u64 halt_attempted_poll;
562
+	u64 halt_poll_success_ns;
563
+	u64 halt_poll_fail_ns;
352564 	u64 halt_poll_invalid;
353565 	u64 halt_wakeup;
354566 	u64 hvc_exit_stat;
....@@ -364,6 +576,12 @@
364576 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
365577 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
366578 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
579
+
580
+unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
581
+int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
582
+int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
583
+int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
584
+
367585 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
368586 			      struct kvm_vcpu_events *events);
369587 
....@@ -372,85 +590,130 @@
372590 
373591 #define KVM_ARCH_WANT_MMU_NOTIFIER
374592 int kvm_unmap_hva_range(struct kvm *kvm,
375
-			unsigned long start, unsigned long end, bool blockable);
376
-void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
593
+			unsigned long start, unsigned long end, unsigned flags);
594
+int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
377595 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
378596 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
379597 
380
-struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
381
-struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
382598 void kvm_arm_halt_guest(struct kvm *kvm);
383599 void kvm_arm_resume_guest(struct kvm *kvm);
384600 
385
-u64 __kvm_call_hyp(void *hypfn, ...);
386
-#define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
601
+#ifndef __KVM_NVHE_HYPERVISOR__
602
+#define kvm_call_hyp_nvhe(f, ...)						\
603
+	({								\
604
+		struct arm_smccc_res res;				\
605
+									\
606
+		arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f),		\
607
+				  ##__VA_ARGS__, &res);			\
608
+		WARN_ON(res.a0 != SMCCC_RET_SUCCESS);			\
609
+									\
610
+		res.a1;							\
611
+	})
612
+
613
+/*
614
+ * The couple of isb() below are there to guarantee the same behaviour
615
+ * on VHE as on !VHE, where the eret to EL1 acts as a context
616
+ * synchronization event.
617
+ */
618
+#define kvm_call_hyp(f, ...)						\
619
+	do {								\
620
+		if (has_vhe()) {					\
621
+			f(__VA_ARGS__);					\
622
+			isb();						\
623
+		} else {						\
624
+			kvm_call_hyp_nvhe(f, ##__VA_ARGS__);		\
625
+		}							\
626
+	} while(0)
627
+
628
+#define kvm_call_hyp_ret(f, ...)					\
629
+	({								\
630
+		typeof(f(__VA_ARGS__)) ret;				\
631
+									\
632
+		if (has_vhe()) {					\
633
+			ret = f(__VA_ARGS__);				\
634
+			isb();						\
635
+		} else {						\
636
+			ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__);	\
637
+		}							\
638
+									\
639
+		ret;							\
640
+	})
641
+#else /* __KVM_NVHE_HYPERVISOR__ */
642
+#define kvm_call_hyp(f, ...) f(__VA_ARGS__)
643
+#define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
644
+#define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
645
+#endif /* __KVM_NVHE_HYPERVISOR__ */
387646 
388647 void force_vm_exit(const cpumask_t *mask);
389648 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
390649 
391
-int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
392
-		int exception_index);
393
-void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
394
-		       int exception_index);
650
+int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
651
+void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
652
+
653
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
654
+int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
655
+int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
656
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
657
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
658
+int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
659
+
660
+void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
661
+
662
+void kvm_sys_reg_table_init(void);
663
+
664
+/* MMIO helpers */
665
+void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
666
+unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
667
+
668
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
669
+int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
395670 
396671 int kvm_perf_init(void);
397672 int kvm_perf_teardown(void);
673
+
674
+long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
675
+gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
676
+void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
677
+
678
+bool kvm_arm_pvtime_supported(void);
679
+int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
680
+			    struct kvm_device_attr *attr);
681
+int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
682
+			    struct kvm_device_attr *attr);
683
+int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
684
+			    struct kvm_device_attr *attr);
685
+
686
+static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
687
+{
688
+	vcpu_arch->steal.base = GPA_INVALID;
689
+}
690
+
691
+static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
692
+{
693
+	return (vcpu_arch->steal.base != GPA_INVALID);
694
+}
398695 
399696 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
400697 
401698 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
402699 
403
-DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);
700
+DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
404701 
405
-void __kvm_enable_ssbs(void);
406
-
407
-static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
408
-				       unsigned long hyp_stack_ptr,
409
-				       unsigned long vector_ptr)
702
+static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
410703 {
411
-	/*
412
-	 * Calculate the raw per-cpu offset without a translation from the
413
-	 * kernel's mapping to the linear mapping, and store it in tpidr_el2
414
-	 * so that we can use adr_l to access per-cpu variables in EL2.
415
-	 */
416
-	u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) -
417
-			 (u64)kvm_ksym_ref(kvm_host_cpu_state));
418
-
419
-	/*
420
-	 * Call initialization code, and switch to the full blown HYP code.
421
-	 * If the cpucaps haven't been finalized yet, something has gone very
422
-	 * wrong, and hyp will crash and burn when it uses any
423
-	 * cpus_have_const_cap() wrapper.
424
-	 */
425
-	BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
426
-	__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
427
-
428
-	/*
429
-	 * Disabling SSBD on a non-VHE system requires us to enable SSBS
430
-	 * at EL2.
431
-	 */
432
-	if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
433
-	    arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
434
-		kvm_call_hyp(__kvm_enable_ssbs);
435
-	}
704
+	/* The host's MPIDR is immutable, so let's set it up at boot time */
705
+	ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
436706 }
437707 
438
-static inline bool kvm_arch_check_sve_has_vhe(void)
708
+static inline bool kvm_system_needs_idmapped_vectors(void)
439709 {
440
-	/*
441
-	 * The Arm architecture specifies that implementation of SVE
442
-	 * requires VHE also to be implemented.  The KVM code for arm64
443
-	 * relies on this when SVE is present:
444
-	 */
445
-	if (system_supports_sve())
446
-		return has_vhe();
447
-	else
448
-		return true;
710
+	return cpus_have_const_cap(ARM64_SPECTRE_V3A);
449711 }
712
+
713
+void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu);
450714 
451715 static inline void kvm_arch_hardware_unsetup(void) {}
452716 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
453
-static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
454717 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
455718 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
456719 
....@@ -459,7 +722,6 @@
459722 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
460723 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
461724 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
462
-bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run);
463725 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
464726 			       struct kvm_device_attr *attr);
465727 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
....@@ -467,79 +729,68 @@
467729 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
468730 			       struct kvm_device_attr *attr);
469731 
470
-static inline void __cpu_init_stage2(void)
471
-{
472
-	u32 parange = kvm_call_hyp(__init_stage2_translation);
473
-
474
-	WARN_ONCE(parange < 40,
475
-		  "PARange is %d bits, unsupported configuration!", parange);
476
-}
477
-
478732 /* Guest/host FPSIMD coordination helpers */
479733 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
480734 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
481735 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
482736 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
483737 
738
+static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
739
+{
740
+	return (!has_vhe() && attr->exclude_host);
741
+}
742
+
743
+/* Flags for host debug state */
744
+void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu);
745
+void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu);
746
+
484747 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
485748 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
486749 {
487750 	return kvm_arch_vcpu_run_map_fp(vcpu);
488751 }
752
+
753
+void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr);
754
+void kvm_clr_pmu_events(u32 clr);
755
+
756
+void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu);
757
+void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu);
758
+#else
759
+static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {}
760
+static inline void kvm_clr_pmu_events(u32 clr) {}
489761 #endif
490762 
491
-static inline void kvm_arm_vhe_guest_enter(void)
492
-{
493
-	local_daif_mask();
494
-}
763
+void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu);
764
+void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu);
495765 
496
-static inline void kvm_arm_vhe_guest_exit(void)
497
-{
498
-	local_daif_restore(DAIF_PROCCTX_NOIRQ);
499
-
500
-	/*
501
-	 * When we exit from the guest we change a number of CPU configuration
502
-	 * parameters, such as traps.  Make sure these changes take effect
503
-	 * before running the host or additional guests.
504
-	 */
505
-	isb();
506
-}
507
-
508
-static inline bool kvm_arm_harden_branch_predictor(void)
509
-{
510
-	return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
511
-}
512
-
513
-#define KVM_SSBD_UNKNOWN		-1
514
-#define KVM_SSBD_FORCE_DISABLE		0
515
-#define KVM_SSBD_KERNEL		1
516
-#define KVM_SSBD_FORCE_ENABLE		2
517
-#define KVM_SSBD_MITIGATED		3
518
-
519
-static inline int kvm_arm_have_ssbd(void)
520
-{
521
-	switch (arm64_get_ssbd_state()) {
522
-	case ARM64_SSBD_FORCE_DISABLE:
523
-		return KVM_SSBD_FORCE_DISABLE;
524
-	case ARM64_SSBD_KERNEL:
525
-		return KVM_SSBD_KERNEL;
526
-	case ARM64_SSBD_FORCE_ENABLE:
527
-		return KVM_SSBD_FORCE_ENABLE;
528
-	case ARM64_SSBD_MITIGATED:
529
-		return KVM_SSBD_MITIGATED;
530
-	case ARM64_SSBD_UNKNOWN:
531
-	default:
532
-		return KVM_SSBD_UNKNOWN;
533
-	}
534
-}
535
-
536
-void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
537
-void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
766
+int kvm_set_ipa_limit(void);
538767 
539768 #define __KVM_HAVE_ARCH_VM_ALLOC
540769 struct kvm *kvm_arch_alloc_vm(void);
541770 void kvm_arch_free_vm(struct kvm *kvm);
542771 
543
-#define kvm_arm_vcpu_loaded(vcpu)	((vcpu)->arch.sysregs_loaded_on_cpu)
772
+int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
773
+
774
+int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
775
+bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
776
+
777
+#define kvm_arm_vcpu_sve_finalized(vcpu) \
778
+	((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED)
779
+
780
+#define kvm_vcpu_has_pmu(vcpu)					\
781
+	(test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
782
+
783
+#define kvm_supports_32bit_el0()				\
784
+	(system_supports_32bit_el0() &&				\
785
+	 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
786
+
787
+int kvm_trng_call(struct kvm_vcpu *vcpu);
788
+#ifdef CONFIG_KVM
789
+extern phys_addr_t hyp_mem_base;
790
+extern phys_addr_t hyp_mem_size;
791
+void __init kvm_hyp_reserve(void);
792
+#else
793
+static inline void kvm_hyp_reserve(void) { }
794
+#endif
544795 
545796 #endif /* __ARM64_KVM_HOST_H__ */