enable docker ppp

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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arm64/include/asm/io.h
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@@ -1,37 +1,23 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Based on arch/arm/include/asm/io.h
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  *
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  * Copyright (C) 1996-2000 Russell King
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  * Copyright (C) 2012 ARM Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef __ASM_IO_H
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 #define __ASM_IO_H
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-#ifdef __KERNEL__
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-
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 #include <linux/types.h>
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+#include <linux/log_mmiorw.h>
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+#include <linux/pgtable.h>
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 #include <asm/byteorder.h>
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 #include <asm/barrier.h>
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 #include <asm/memory.h>
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-#include <asm/pgtable.h>
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 #include <asm/early_ioremap.h>
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 #include <asm/alternative.h>
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 #include <asm/cpufeature.h>
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-
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-#include <xen/xen.h>
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 /*
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  * Generic IO read/write.  These perform native-endian accesses.
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@@ -39,24 +25,28 @@
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 #define __raw_writeb __raw_writeb
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 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
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 {
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+	log_write_mmio(val, 8,  addr);
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 	asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
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 }
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 #define __raw_writew __raw_writew
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 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
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 {
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+	log_write_mmio(val, 16, addr);
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 	asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
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 }
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 #define __raw_writel __raw_writel
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-static inline void __raw_writel(u32 val, volatile void __iomem *addr)
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+static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr)
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 {
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+	log_write_mmio(val, 32, addr);
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 	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
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 }
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 #define __raw_writeq __raw_writeq
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 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
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 {
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+	log_write_mmio(val, 64, addr);
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 	asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
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 }
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@@ -64,10 +54,13 @@
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 static inline u8 __raw_readb(const volatile void __iomem *addr)
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 {
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 	u8 val;
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+
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+	log_read_mmio(8, addr);
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 	asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
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 				 "ldarb %w0, [%1]",
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 				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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 		     : "=r" (val) : "r" (addr));
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+	log_post_read_mmio(val, 8, addr);
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 	return val;
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 }
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@@ -76,21 +69,26 @@
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 {
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 	u16 val;
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+	log_read_mmio(16, addr);
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 	asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
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 				 "ldarh %w0, [%1]",
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 				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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 		     : "=r" (val) : "r" (addr));
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+	log_post_read_mmio(val, 16,  addr);
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 	return val;
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 }
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 #define __raw_readl __raw_readl
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-static inline u32 __raw_readl(const volatile void __iomem *addr)
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+static __always_inline u32 __raw_readl(const volatile void __iomem *addr)
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 {
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 	u32 val;
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+
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+	log_read_mmio(32, addr);
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 	asm volatile(ALTERNATIVE("ldr %w0, [%1]",
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 				 "ldar %w0, [%1]",
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 				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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 		     : "=r" (val) : "r" (addr));
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+	log_post_read_mmio(val, 32, addr);
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 	return val;
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 }
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@@ -98,10 +96,13 @@
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 static inline u64 __raw_readq(const volatile void __iomem *addr)
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 {
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 	u64 val;
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+
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+	log_read_mmio(64, addr);
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 	asm volatile(ALTERNATIVE("ldr %0, [%1]",
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 				 "ldar %0, [%1]",
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 				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
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 		     : "=r" (val) : "r" (addr));
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+	log_post_read_mmio(val, 64, addr);
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 	return val;
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 }
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@@ -110,7 +111,7 @@
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 ({									\
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 	unsigned long tmp;						\
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 									\
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-	rmb();								\
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+	dma_rmb();								\
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 									\
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 	/*								\
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 	 * Create a dummy control dependency from the IO read to any	\
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@@ -123,9 +124,9 @@
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 		     : "memory");					\
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 })
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-#define __iowmb()		wmb()
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-
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-#define mmiowb()		do { } while (0)
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+#define __io_par(v)		__iormb(v)
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+#define __iowmb()		dma_wmb()
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+#define __iomb()		dma_mb()
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 /*
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  * Relaxed I/O memory access primitives. These follow the Device memory
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@@ -179,14 +180,11 @@
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  * I/O memory mapping functions.
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  */
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 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
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-extern void __iounmap(volatile void __iomem *addr);
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+extern void iounmap(volatile void __iomem *addr);
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 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
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 #define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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-#define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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 #define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
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-#define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
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-#define iounmap				__iounmap
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 /*
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  * PCI configuration space mapping function.
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@@ -221,12 +219,8 @@
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 extern int devmem_is_allowed(unsigned long pfn);
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-struct bio_vec;
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-extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
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-				      const struct bio_vec *vec2);
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-#define BIOVEC_PHYS_MERGEABLE(vec1, vec2)				\
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-	(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&				\
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-	 (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
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+extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
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+					unsigned long flags);
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+#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
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-#endif	/* __KERNEL__ */
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 #endif	/* __ASM_IO_H */