enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arm64/include/asm/cpu.h
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@@ -1,17 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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   * Copyright (C) 2014 ARM Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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 #ifndef __ASM_CPU_H
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 #define __ASM_CPU_H
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@@ -23,6 +12,31 @@
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 /*
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  * Records attributes of an individual CPU.
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  */
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+struct cpuinfo_32bit {
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+	u32		reg_id_dfr0;
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+	u32		reg_id_dfr1;
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+	u32		reg_id_isar0;
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+	u32		reg_id_isar1;
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+	u32		reg_id_isar2;
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+	u32		reg_id_isar3;
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+	u32		reg_id_isar4;
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+	u32		reg_id_isar5;
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+	u32		reg_id_isar6;
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+	u32		reg_id_mmfr0;
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+	u32		reg_id_mmfr1;
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+	u32		reg_id_mmfr2;
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+	u32		reg_id_mmfr3;
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+	u32		reg_id_mmfr4;
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+	u32		reg_id_mmfr5;
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+	u32		reg_id_pfr0;
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+	u32		reg_id_pfr1;
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+	u32		reg_id_pfr2;
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+
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+	u32		reg_mvfr0;
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+	u32		reg_mvfr1;
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+	u32		reg_mvfr2;
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+};
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+
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 struct cpuinfo_arm64 {
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 	struct cpu	cpu;
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 	struct kobject	kobj;
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@@ -36,6 +50,7 @@
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 	u64		reg_id_aa64dfr1;
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 	u64		reg_id_aa64isar0;
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 	u64		reg_id_aa64isar1;
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+	u64		reg_id_aa64isar2;
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 	u64		reg_id_aa64mmfr0;
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 	u64		reg_id_aa64mmfr1;
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 	u64		reg_id_aa64mmfr2;
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@@ -43,23 +58,7 @@
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 	u64		reg_id_aa64pfr1;
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 	u64		reg_id_aa64zfr0;
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-	u32		reg_id_dfr0;
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-	u32		reg_id_isar0;
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-	u32		reg_id_isar1;
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-	u32		reg_id_isar2;
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-	u32		reg_id_isar3;
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-	u32		reg_id_isar4;
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-	u32		reg_id_isar5;
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-	u32		reg_id_mmfr0;
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-	u32		reg_id_mmfr1;
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-	u32		reg_id_mmfr2;
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-	u32		reg_id_mmfr3;
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-	u32		reg_id_pfr0;
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-	u32		reg_id_pfr1;
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-
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-	u32		reg_mvfr0;
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-	u32		reg_mvfr1;
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-	u32		reg_mvfr2;
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+	struct cpuinfo_32bit	aarch32;
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 	/* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */
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 	u64		reg_zcr;