forked from ~ljy/RK356X_SDK_RELEASE
blame | history | patch | commit | commitdiff
hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/arch/arm64/boot/dts/rockchip/rk3328.dtsi
....@@ -8,12 +8,9 @@
88 #include <dt-bindings/interrupt-controller/arm-gic.h>
99 #include <dt-bindings/interrupt-controller/irq.h>
1010 #include <dt-bindings/pinctrl/rockchip.h>
11
-#include <dt-bindings/soc/rockchip-system-status.h>
12
-#include <dt-bindings/suspend/rockchip-rk3328.h>
1311 #include <dt-bindings/power/rk3328-power.h>
1412 #include <dt-bindings/soc/rockchip,boot-mode.h>
1513 #include <dt-bindings/thermal/thermal.h>
16
-#include "rk3328-dram-default-timing.dtsi"
1714 
1815 / {
1916 	compatible = "rockchip,rk3328";
....@@ -23,15 +20,19 @@
2320 	#size-cells = <2>;
2421 
2522 	aliases {
26
-		ethernet0 = &gmac2io;
27
-		ethernet1 = &gmac2phy;
23
+		gpio0 = &gpio0;
24
+		gpio1 = &gpio1;
25
+		gpio2 = &gpio2;
26
+		gpio3 = &gpio3;
27
+		serial0 = &uart0;
28
+		serial1 = &uart1;
29
+		serial2 = &uart2;
2830 		i2c0 = &i2c0;
2931 		i2c1 = &i2c1;
3032 		i2c2 = &i2c2;
3133 		i2c3 = &i2c3;
32
-		serial0 = &uart0;
33
-		serial1 = &uart1;
34
-		serial2 = &uart2;
34
+		ethernet0 = &gmac2io;
35
+		ethernet1 = &gmac2phy;
3536 	};
3637 
3738 	cpus {
....@@ -40,10 +41,11 @@
4041 
4142 		cpu0: cpu@0 {
4243 			device_type = "cpu";
43
-			compatible = "arm,cortex-a53", "arm,armv8";
44
+			compatible = "arm,cortex-a53";
4445 			reg = <0x0 0x0>;
4546 			clocks = <&cru ARMCLK>;
4647 			#cooling-cells = <2>;
48
+			cpu-idle-states = <&CPU_SLEEP>;
4749 			dynamic-power-coefficient = <120>;
4850 			enable-method = "psci";
4951 			next-level-cache = <&l2>;
....@@ -52,10 +54,11 @@
5254 
5355 		cpu1: cpu@1 {
5456 			device_type = "cpu";
55
-			compatible = "arm,cortex-a53", "arm,armv8";
57
+			compatible = "arm,cortex-a53";
5658 			reg = <0x0 0x1>;
5759 			clocks = <&cru ARMCLK>;
5860 			#cooling-cells = <2>;
61
+			cpu-idle-states = <&CPU_SLEEP>;
5962 			dynamic-power-coefficient = <120>;
6063 			enable-method = "psci";
6164 			next-level-cache = <&l2>;
....@@ -64,10 +67,11 @@
6467 
6568 		cpu2: cpu@2 {
6669 			device_type = "cpu";
67
-			compatible = "arm,cortex-a53", "arm,armv8";
70
+			compatible = "arm,cortex-a53";
6871 			reg = <0x0 0x2>;
6972 			clocks = <&cru ARMCLK>;
7073 			#cooling-cells = <2>;
74
+			cpu-idle-states = <&CPU_SLEEP>;
7175 			dynamic-power-coefficient = <120>;
7276 			enable-method = "psci";
7377 			next-level-cache = <&l2>;
....@@ -76,14 +80,28 @@
7680 
7781 		cpu3: cpu@3 {
7882 			device_type = "cpu";
79
-			compatible = "arm,cortex-a53", "arm,armv8";
83
+			compatible = "arm,cortex-a53";
8084 			reg = <0x0 0x3>;
8185 			clocks = <&cru ARMCLK>;
8286 			#cooling-cells = <2>;
87
+			cpu-idle-states = <&CPU_SLEEP>;
8388 			dynamic-power-coefficient = <120>;
8489 			enable-method = "psci";
8590 			next-level-cache = <&l2>;
8691 			operating-points-v2 = <&cpu0_opp_table>;
92
+		};
93
+
94
+		idle-states {
95
+			entry-method = "psci";
96
+
97
+			CPU_SLEEP: cpu-sleep {
98
+				compatible = "arm,idle-state";
99
+				local-timer-stop;
100
+				arm,psci-suspend-param = <0x0010000>;
101
+				entry-latency-us = <120>;
102
+				exit-latency-us = <250>;
103
+				min-residency-us = <900>;
104
+			};
87105 		};
88106 
89107 		l2: l2-cache0 {
....@@ -91,65 +109,44 @@
91109 		};
92110 	};
93111 
94
-	cpu0_opp_table: cpu0-opp-table {
112
+	cpu0_opp_table: opp_table0 {
95113 		compatible = "operating-points-v2";
96114 		opp-shared;
97115 
98
-		rockchip,video-4k-freq = <1008000>;
99
-
100
-		rockchip,leakage-voltage-sel = <
101
-			1   10    0
102
-			11  254   1
103
-		>;
104
-		nvmem-cells = <&cpu_leakage>;
105
-		nvmem-cell-names = "cpu_leakage";
106
-
107116 		opp-408000000 {
108117 			opp-hz = /bits/ 64 <408000000>;
109
-			opp-microvolt = <950000 950000 1350000>;
110
-			opp-microvolt-L0 = <950000 950000 1350000>;
111
-			opp-microvolt-L1 = <950000 950000 1350000>;
118
+			opp-microvolt = <950000>;
112119 			clock-latency-ns = <40000>;
113120 			opp-suspend;
114121 		};
115122 		opp-600000000 {
116123 			opp-hz = /bits/ 64 <600000000>;
117
-			opp-microvolt = <950000 950000 1350000>;
118
-			opp-microvolt-L0 = <950000 950000 1350000>;
119
-			opp-microvolt-L1 = <950000 950000 1350000>;
124
+			opp-microvolt = <950000>;
120125 			clock-latency-ns = <40000>;
121126 		};
122127 		opp-816000000 {
123128 			opp-hz = /bits/ 64 <816000000>;
124
-			opp-microvolt = <1050000 1050000 1350000>;
125
-			opp-microvolt-L0 = <1050000 1050000 1350000>;
126
-			opp-microvolt-L1 = <1000000 1000000 1350000>;
129
+			opp-microvolt = <1000000>;
127130 			clock-latency-ns = <40000>;
128131 		};
129132 		opp-1008000000 {
130133 			opp-hz = /bits/ 64 <1008000000>;
131
-			opp-microvolt = <1150000 1150000 1350000>;
132
-			opp-microvolt-L0 = <1150000 1150000 1350000>;
133
-			opp-microvolt-L1 = <1100000 1100000 1350000>;
134
+			opp-microvolt = <1100000>;
134135 			clock-latency-ns = <40000>;
135136 		};
136137 		opp-1200000000 {
137138 			opp-hz = /bits/ 64 <1200000000>;
138
-			opp-microvolt = <1275000 1275000 1350000>;
139
-			opp-microvolt-L0 = <1275000 1275000 1350000>;
140
-			opp-microvolt-L1 = <1225000 1225000 1350000>;
139
+			opp-microvolt = <1225000>;
141140 			clock-latency-ns = <40000>;
142141 		};
143142 		opp-1296000000 {
144143 			opp-hz = /bits/ 64 <1296000000>;
145
-			opp-microvolt = <1350000 1350000 1350000>;
146
-			opp-microvolt-L0 = <1350000 1350000 1350000>;
147
-			opp-microvolt-L1 = <1300000 1300000 1350000>;
144
+			opp-microvolt = <1300000>;
148145 			clock-latency-ns = <40000>;
149146 		};
150147 	};
151148 
152
-	amba {
149
+	amba: bus {
153150 		compatible = "simple-bus";
154151 		#address-cells = <2>;
155152 		#size-cells = <2>;
....@@ -160,10 +157,26 @@
160157 			reg = <0x0 0xff1f0000 0x0 0x4000>;
161158 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
162159 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160
+			arm,pl330-periph-burst;
163161 			clocks = <&cru ACLK_DMAC>;
164162 			clock-names = "apb_pclk";
165163 			#dma-cells = <1>;
166
-			arm,pl330-periph-burst;
164
+		};
165
+	};
166
+
167
+	analog_sound: analog-sound {
168
+		compatible = "simple-audio-card";
169
+		simple-audio-card,format = "i2s";
170
+		simple-audio-card,mclk-fs = <256>;
171
+		simple-audio-card,name = "Analog";
172
+		status = "disabled";
173
+
174
+		simple-audio-card,cpu {
175
+			sound-dai = <&i2s1>;
176
+		};
177
+
178
+		simple-audio-card,codec {
179
+			sound-dai = <&codec>;
167180 		};
168181 	};
169182 
....@@ -176,38 +189,30 @@
176189 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
177190 	};
178191 
179
-	cpuinfo {
180
-		compatible = "rockchip,cpuinfo";
181
-		nvmem-cells = <&efuse_id>, <&efuse_cpu_version>;
182
-		nvmem-cell-names = "id", "cpu-version";
192
+	display_subsystem: display-subsystem {
193
+		compatible = "rockchip,display-subsystem";
194
+		ports = <&vop_out>;
183195 	};
184196 
185
-	firmware {
186
-		optee: optee {
187
-			compatible = "linaro,optee-tz";
188
-			method = "smc";
197
+	hdmi_sound: hdmi-sound {
198
+		compatible = "simple-audio-card";
199
+		simple-audio-card,format = "i2s";
200
+		simple-audio-card,mclk-fs = <128>;
201
+		simple-audio-card,name = "HDMI";
202
+		status = "disabled";
203
+
204
+		simple-audio-card,cpu {
205
+			sound-dai = <&i2s0>;
206
+		};
207
+
208
+		simple-audio-card,codec {
209
+			sound-dai = <&hdmi>;
189210 		};
190211 	};
191212 
192213 	psci {
193214 		compatible = "arm,psci-1.0", "arm,psci-0.2";
194215 		method = "smc";
195
-	};
196
-
197
-	rockchip_suspend: rockchip-suspend {
198
-		compatible = "rockchip,pm-rk3328";
199
-		status = "disabled";
200
-		rockchip,sleep-mode-config = <0>;
201
-		rockchip,virtual-poweroff = <0>;
202
-	};
203
-
204
-	rockchip_system_monitor: rockchip-system-monitor {
205
-		compatible = "rockchip,system-monitor";
206
-
207
-		rockchip,thermal-zone = "soc-thermal";
208
-		rockchip,polling-delay = <200>; /* milliseconds */
209
-
210
-		rockchip,video-4k-offline-cpus = "3";
211216 	};
212217 
213218 	timer {
....@@ -233,8 +238,7 @@
233238 		clock-names = "i2s_clk", "i2s_hclk";
234239 		dmas = <&dmac 11>, <&dmac 12>;
235240 		dma-names = "tx", "rx";
236
-		resets = <&cru SRST_I2S0>, <&cru SRST_I2S0_H>;
237
-		reset-names = "reset-m", "reset-h";
241
+		#sound-dai-cells = <0>;
238242 		status = "disabled";
239243 	};
240244 
....@@ -246,8 +250,7 @@
246250 		clock-names = "i2s_clk", "i2s_hclk";
247251 		dmas = <&dmac 14>, <&dmac 15>;
248252 		dma-names = "tx", "rx";
249
-		resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>;
250
-		reset-names = "reset-m", "reset-h";
253
+		#sound-dai-cells = <0>;
251254 		status = "disabled";
252255 	};
253256 
....@@ -259,16 +262,7 @@
259262 		clock-names = "i2s_clk", "i2s_hclk";
260263 		dmas = <&dmac 0>, <&dmac 1>;
261264 		dma-names = "tx", "rx";
262
-		resets = <&cru SRST_I2S2>, <&cru SRST_I2S2_H>;
263
-		reset-names = "reset-m", "reset-h";
264
-		pinctrl-names = "default", "sleep";
265
-		pinctrl-0 = <&i2s2m0_mclk
266
-			     &i2s2m0_sclk
267
-			     &i2s2m0_lrcktx
268
-			     &i2s2m0_lrckrx
269
-			     &i2s2m0_sdo
270
-			     &i2s2m0_sdi>;
271
-		pinctrl-1 = <&i2s2m0_sleep>;
265
+		#sound-dai-cells = <0>;
272266 		status = "disabled";
273267 	};
274268 
....@@ -282,11 +276,12 @@
282276 		dma-names = "tx";
283277 		pinctrl-names = "default";
284278 		pinctrl-0 = <&spdifm2_tx>;
279
+		#sound-dai-cells = <0>;
285280 		status = "disabled";
286281 	};
287282 
288283 	pdm: pdm@ff040000 {
289
-		compatible = "rockchip,rk3328-pdm";
284
+		compatible = "rockchip,pdm";
290285 		reg = <0x0 0xff040000 0x0 0x1000>;
291286 		clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
292287 		clock-names = "pdm_clk", "pdm_hclk";
....@@ -306,50 +301,19 @@
306301 		status = "disabled";
307302 	};
308303 
309
-	tsp: tsp@ff050000 {
310
-		compatible = "rockchip,rk3328-tsp";
311
-		reg = <0x0 0xff050000 0x0 0x10000>;
312
-		rockchip,grf = <&grf>;
313
-		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
314
-		interrupt-names = "irq_tsp";
315
-		clocks = <&cru SCLK_TSP>, <&cru ACLK_TSP>, <&cru HCLK_TSP>;
316
-		clock-names = "clk_tsp", "aclk_tsp", "hclk_tsp";
317
-		pinctrl-names = "default";
318
-		pinctrl-0 = <&tsp_d0
319
-			     &tsp_d1
320
-			     &tsp_d2
321
-			     &tsp_d3
322
-			     &tsp_d4
323
-			     &tsp_d5
324
-			     &tsp_d6
325
-			     &tsp_d7
326
-			     &tsp_sync
327
-			     &tsp_clk
328
-			     &tsp_fail
329
-			     &tsp_valid>;
330
-		status = "disabled";
331
-	};
332
-
333
-	rng: rng@ff060000 {
334
-		compatible = "rockchip,cryptov1-rng";
335
-		reg = <0x0 0xff060000 0x0 0x4000>;
336
-
337
-		clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
338
-		clock-names = "clk_crypto", "hclk_crypto";
339
-		assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
340
-		assigned-clock-rates = <150000000>, <100000000>;
341
-		status = "disabled";
342
-	};
343
-
344304 	grf: syscon@ff100000 {
345305 		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
346306 		reg = <0x0 0xff100000 0x0 0x1000>;
347
-		#address-cells = <1>;
348
-		#size-cells = <1>;
349307 
350308 		io_domains: io-domains {
351309 			compatible = "rockchip,rk3328-io-voltage-domain";
352310 			status = "disabled";
311
+		};
312
+
313
+		grf_gpio: grf-gpio {
314
+			compatible = "rockchip,rk3328-grf-gpio";
315
+			gpio-controller;
316
+			#gpio-cells = <2>;
353317 		};
354318 
355319 		power: power-controller {
....@@ -357,28 +321,20 @@
357321 			#power-domain-cells = <1>;
358322 			#address-cells = <1>;
359323 			#size-cells = <0>;
360
-			status = "okay";
361324 
362
-			pd_hevc@RK3328_PD_HEVC {
325
+			power-domain@RK3328_PD_HEVC {
363326 				reg = <RK3328_PD_HEVC>;
364327 			};
365
-			pd_video@RK3328_PD_VIDEO {
328
+			power-domain@RK3328_PD_VIDEO {
366329 				reg = <RK3328_PD_VIDEO>;
367
-				clocks = <&cru ACLK_RKVDEC>,
368
-					 <&cru HCLK_RKVDEC>,
369
-					 <&cru SCLK_VDEC_CABAC>,
370
-					 <&cru SCLK_VDEC_CORE>;
371
-				pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>;
372330 			};
373
-			pd_vpu@RK3328_PD_VPU {
331
+			power-domain@RK3328_PD_VPU {
374332 				reg = <RK3328_PD_VPU>;
375
-				clocks = <&cru ACLK_VPU>,
376
-					 <&cru HCLK_VPU>;
377
-				pm_qos = <&qos_vpu>;
333
+				clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
378334 			};
379335 		};
380336 
381
-		reboot_mode: reboot-mode {
337
+		reboot-mode {
382338 			compatible = "syscon-reboot-mode";
383339 			offset = <0x5c8>;
384340 			mode-normal = <BOOT_NORMAL>;
....@@ -386,7 +342,6 @@
386342 			mode-bootloader = <BOOT_FASTBOOT>;
387343 			mode-loader = <BOOT_BL_DOWNLOAD>;
388344 		};
389
-
390345 	};
391346 
392347 	uart0: serial@ff110000 {
....@@ -573,7 +528,7 @@
573528 					type = "passive";
574529 				};
575530 				soc_crit: soc-crit {
576
-					temperature = <115000>;
531
+					temperature = <95000>;
577532 					hysteresis = <2000>;
578533 					type = "critical";
579534 				};
....@@ -582,23 +537,11 @@
582537 			cooling-maps {
583538 				map0 {
584539 					trip = <&target>;
585
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
540
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
541
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
542
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
543
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
586544 					contribution = <4096>;
587
-				};
588
-				map1 {
589
-					trip = <&target>;
590
-					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
591
-					contribution = <4096>;
592
-				};
593
-				map2 {
594
-					trip = <&target>;
595
-					cooling-device = <&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
596
-					contribution = <1024>;
597
-				};
598
-				map3 {
599
-					trip = <&target>;
600
-					cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
601
-					contribution = <1024>;
602545 				};
603546 			};
604547 		};
....@@ -614,12 +557,12 @@
614557 		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
615558 		clock-names = "tsadc", "apb_pclk";
616559 		pinctrl-names = "gpio", "otpout";
617
-		pinctrl-0 = <&otp_gpio>;
560
+		pinctrl-0 = <&otp_pin>;
618561 		pinctrl-1 = <&otp_out>;
619562 		resets = <&cru SRST_TSADC>;
620563 		reset-names = "tsadc-apb";
621564 		rockchip,grf = <&grf>;
622
-		rockchip,hw-tshut-temp = <120000>;
565
+		rockchip,hw-tshut-temp = <100000>;
623566 		#thermal-sensor-cells = <1>;
624567 		status = "disabled";
625568 	};
....@@ -662,9 +605,8 @@
662605 	};
663606 
664607 	gpu: gpu@ff300000 {
665
-		compatible = "arm,mali-450";
608
+		compatible = "rockchip,rk3328-mali", "arm,mali-450";
666609 		reg = <0x0 0xff300000 0x0 0x30000>;
667
-
668610 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
669611 			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
670612 			     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
....@@ -672,120 +614,26 @@
672614 			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
673615 			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
674616 			     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
675
-		interrupt-names = "Mali_GP_IRQ",
676
-				  "Mali_GP_MMU_IRQ",
677
-				  "IRQPP",
678
-				  "Mali_PP0_IRQ",
679
-				  "Mali_PP0_MMU_IRQ",
680
-				  "Mali_PP1_IRQ",
681
-				  "Mali_PP1_MMU_IRQ";
682
-		clocks = <&cru ACLK_GPU>;
683
-		clock-names = "clk_mali";
684
-		#cooling-cells = <2>; /* min followed by max */
685
-		operating-points-v2 = <&gpu_opp_table>;
686
-		status = "disabled";
687
-
688
-		gpu_power_model: power_model {
689
-			compatible = "arm,mali-simple-power-model";
690
-			voltage = <900>;
691
-			frequency = <500>;
692
-			static-power = <300>;
693
-			dynamic-power = <396>;
694
-			ts = <32000 4700 (-80) 2>;
695
-			thermal-zone = "soc-thermal";
696
-		};
617
+		interrupt-names = "gp",
618
+				  "gpmmu",
619
+				  "pp",
620
+				  "pp0",
621
+				  "ppmmu0",
622
+				  "pp1",
623
+				  "ppmmu1";
624
+		clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
625
+		clock-names = "bus", "core";
626
+		resets = <&cru SRST_GPU_A>;
697627 	};
698628 
699
-	gpu_opp_table: gpu-opp-table {
700
-		compatible = "operating-points-v2";
701
-
702
-		rockchip,leakage-voltage-sel = <
703
-			1   10    0
704
-			11  254   1
705
-		>;
706
-		nvmem-cells = <&logic_leakage>;
707
-		nvmem-cell-names = "gpu_leakage";
708
-
709
-		opp-200000000 {
710
-			opp-hz = /bits/ 64 <200000000>;
711
-			opp-microvolt = <950000>;
712
-			opp-microvolt-L0 = <950000>;
713
-			opp-microvolt-L1 = <950000>;
714
-		};
715
-		opp-300000000 {
716
-			opp-hz = /bits/ 64 <300000000>;
717
-			opp-microvolt = <975000>;
718
-			opp-microvolt-L0 = <975000>;
719
-			opp-microvolt-L1 = <950000>;
720
-		};
721
-		opp-400000000 {
722
-			opp-hz = /bits/ 64 <400000000>;
723
-			opp-microvolt = <1050000>;
724
-			opp-microvolt-L0 = <1050000>;
725
-			opp-microvolt-L1 = <1025000>;
726
-		};
727
-		opp-500000000 {
728
-			opp-hz = /bits/ 64 <500000000>;
729
-			opp-microvolt = <1150000>;
730
-			opp-microvolt-L0 = <1150000>;
731
-			opp-microvolt-L1 = <1100000>;
732
-		};
733
-	};
734
-
735
-	mpp_srv: mpp-srv {
736
-		compatible = "rockchip,mpp-service";
737
-		rockchip,taskqueue-count = <3>;
738
-		rockchip,resetgroup-count = <4>;
739
-		rockchip,grf = <&grf>;
740
-		rockchip,grf-offset = <0x040c>;
741
-		rockchip,grf-values = <0x8000000>, <0x8000800>;
742
-		rockchip,grf-names = "grf_vepu2", "grf_vepu22";
743
-		status = "disabled";
744
-	};
745
-
746
-	vepu22: vepu22@ff330000 {
747
-		compatible = "rockchip,hevc-encoder-v22";
748
-		reg = <0x0 0xff330000 0 0x200>;
749
-		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
750
-		clocks = <&cru ACLK_H265>, <&cru PCLK_H265>,
751
-			<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
752
-			<&cru ACLK_RKVENC>, <&cru ACLK_AXISRAM>;
753
-		clock-names = "aclk_h265", "pclk_h265", "clk_core",
754
-			"clk_dsp", "aclk_venc", "aclk_axi2sram";
755
-		iommus = <&vepu22_mmu>;
756
-		rockchip,srv = <&mpp_srv>;
757
-		rockchip,taskqueue-node = <2>;
758
-		rockchip,resetgroup-node = <2>;
759
-		power-domains = <&power RK3328_PD_HEVC>;
760
-		status = "disabled";
761
-	};
762
-
763
-	vepu22_mmu: iommu@ff330200 {
629
+	h265e_mmu: iommu@ff330200 {
764630 		compatible = "rockchip,iommu";
765631 		reg = <0x0 0xff330200 0 0x100>;
766632 		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
767
-		interrupt-names = "vepu22_mmu";
633
+		interrupt-names = "h265e_mmu";
768634 		clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
769635 		clock-names = "aclk", "iface";
770
-		power-domains = <&power RK3328_PD_HEVC>;
771636 		#iommu-cells = <0>;
772
-		status = "disabled";
773
-	};
774
-
775
-	vepu: vepu@ff340000 {
776
-		compatible = "rockchip,vpu-encoder-v2";
777
-		reg = <0x0 0xff340000 0x0 0x400>;
778
-		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
779
-		clocks = <&cru ACLK_H264>, <&cru HCLK_H264>;
780
-		clock-names = "aclk_vcodec", "hclk_vcodec";
781
-		resets = <&cru SRST_RKVENC_H264_A>,
782
-			<&cru SRST_RKVENC_H264_H>;
783
-		reset-names = "video_a", "video_h";
784
-		iommus = <&vepu_mmu>;
785
-		rockchip,srv = <&mpp_srv>;
786
-		rockchip,taskqueue-node = <0>;
787
-		rockchip,resetgroup-node = <3>;
788
-		power-domains = <&power RK3328_PD_HEVC>;
789637 		status = "disabled";
790638 	};
791639 
....@@ -794,28 +642,21 @@
794642 		reg = <0x0 0xff340800 0x0 0x40>;
795643 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
796644 		interrupt-names = "vepu_mmu";
797
-		clocks = <&cru ACLK_H264>, <&cru HCLK_H264>;
645
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
798646 		clock-names = "aclk", "iface";
799
-		power-domains = <&power RK3328_PD_HEVC>;
800647 		#iommu-cells = <0>;
801648 		status = "disabled";
802649 	};
803650 
804
-	vdpu: vdpu@ff350000 {
805
-		compatible = "rockchip,vpu-decoder-v2";
806
-		reg = <0x0 0xff350400 0x0 0x400>;
651
+	vpu: video-codec@ff350000 {
652
+		compatible = "rockchip,rk3328-vpu";
653
+		reg = <0x0 0xff350000 0x0 0x800>;
807654 		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
808
-		interrupt-names = "irq_dec";
655
+		interrupt-names = "vdpu";
809656 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
810
-		clock-names = "aclk_vcodec", "hclk_vcodec";
811
-		resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
812
-		reset-names = "shared_video_a", "shared_video_h";
657
+		clock-names = "aclk", "hclk";
813658 		iommus = <&vpu_mmu>;
814659 		power-domains = <&power RK3328_PD_VPU>;
815
-		rockchip,srv = <&mpp_srv>;
816
-		rockchip,taskqueue-node = <0>;
817
-		rockchip,resetgroup-node = <0>;
818
-		status = "disabled";
819660 	};
820661 
821662 	vpu_mmu: iommu@ff350800 {
....@@ -823,94 +664,10 @@
823664 		reg = <0x0 0xff350800 0x0 0x40>;
824665 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
825666 		interrupt-names = "vpu_mmu";
667
+		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
826668 		clock-names = "aclk", "iface";
827
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
828
-		power-domains = <&power RK3328_PD_VPU>;
829669 		#iommu-cells = <0>;
830
-		status = "disabled";
831
-	};
832
-
833
-	avsd: avsd_plus@ff351000 {
834
-		compatible = "rockchip,avs-plus-decoder";
835
-		reg = <0x0 0xff351000 0x0 0x200>;
836
-		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
837
-		interrupt-names = "irq_dec";
838
-		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
839
-		clock-names = "aclk_vcodec", "hclk_vcodec";
840
-		resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
841
-		reset-names = "shared_video_a", "shared_video_h";
842
-		iommus = <&vpu_mmu>;
843670 		power-domains = <&power RK3328_PD_VPU>;
844
-		rockchip,srv = <&mpp_srv>;
845
-		rockchip,taskqueue-node = <0>;
846
-		rockchip,resetgroup-node = <0>;
847
-		status = "disabled";
848
-	};
849
-
850
-	rkvdec: rkvdec@ff36000 {
851
-		compatible = "rockchip,rkv-decoder-rk3328";
852
-		reg = <0x0 0xff360000 0x0 0x400>;
853
-		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
854
-		interrupt-names = "irq_dec";
855
-		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
856
-			<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
857
-		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac",
858
-			"clk_core";
859
-		rockchip,normal-rates = <300000000>, <0>, <300000000>, <300000000>;
860
-		rockchip,advanced-rates = <400000000>, <0>, <400000000>, <300000000>;
861
-		rockchip,default-max-load = <2088960>;
862
-		resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>,
863
-			<&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>,
864
-			<&cru SRST_VDEC_CABAC>, <&cru SRST_VDEC_CORE>;
865
-		reset-names = "video_a", "video_h", "niu_a", "niu_h",
866
-			"video_cabac", "video_core";
867
-		iommus = <&rkvdec_mmu>;
868
-		rockchip,srv = <&mpp_srv>;
869
-		rockchip,taskqueue-node = <1>;
870
-		rockchip,resetgroup-node = <1>;
871
-		power-domains = <&power RK3328_PD_VIDEO>;
872
-		operating-points-v2 = <&rkvdec_opp_table>;
873
-		#cooling-cells = <2>;
874
-		devfreq = <&dmc>;
875
-		status = "disabled";
876
-
877
-		vcodec_power_model: vcodec_power_model {
878
-			compatible = "vcodec_power_model";
879
-			dynamic-power-coefficient = <120>;
880
-			static-power-coefficient = <200>;
881
-			ts = <32000 4700 (-80) 2>;
882
-			thermal-zone = "soc-thermal";
883
-		};
884
-	};
885
-
886
-	rkvdec_opp_table: rkvdec-opp-table {
887
-		compatible = "operating-points-v2";
888
-
889
-		rockchip,leakage-voltage-sel = <
890
-			1   10    0
891
-			11  254   1
892
-		>;
893
-		nvmem-cells = <&logic_leakage>;
894
-		nvmem-cell-names = "rkvdec_leakage";
895
-
896
-		opp-100000000 {
897
-			opp-hz = /bits/ 64 <100000000>;
898
-			opp-microvolt = <975000>;
899
-			opp-microvolt-L0 = <975000>;
900
-			opp-microvolt-L1 = <950000>;
901
-		};
902
-		opp-200000000 {
903
-			opp-hz = /bits/ 64 <200000000>;
904
-			opp-microvolt = <975000>;
905
-			opp-microvolt-L0 = <975000>;
906
-			opp-microvolt-L1 = <950000>;
907
-		};
908
-		opp-500000000 {
909
-			opp-hz = /bits/ 64 <500000000>;
910
-			opp-microvolt = <1075000>;
911
-			opp-microvolt-L0 = <1075000>;
912
-			opp-microvolt-L1 = <1050000>;
913
-		};
914671 	};
915672 
916673 	rkvdec_mmu: iommu@ff360480 {
....@@ -920,7 +677,6 @@
920677 		interrupt-names = "rkvdec_mmu";
921678 		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
922679 		clock-names = "aclk", "iface";
923
-		power-domains = <&power RK3328_PD_VIDEO>;
924680 		#iommu-cells = <0>;
925681 		status = "disabled";
926682 	};
....@@ -931,8 +687,6 @@
931687 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
932688 		clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
933689 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
934
-		assigned-clocks = <&cru DCLK_LCDC>;
935
-		assigned-clock-parents = <&cru HDMIPHY>;
936690 		resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
937691 		reset-names = "axi", "ahb", "dclk";
938692 		iommus = <&vop_mmu>;
....@@ -945,10 +699,6 @@
945699 			vop_out_hdmi: endpoint@0 {
946700 				reg = <0>;
947701 				remote-endpoint = <&hdmi_in_vop>;
948
-			};
949
-			vop_out_tve: endpoint@1 {
950
-				reg = <1>;
951
-				remote-endpoint = <&tve_in_vop>;
952702 			};
953703 		};
954704 	};
....@@ -964,42 +714,6 @@
964714 		status = "disabled";
965715 	};
966716 
967
-	rga: rga@ff3900000 {
968
-		compatible = "rockchip,rga2";
969
-		dev_mode = <1>;
970
-		reg = <0x0 0xff390000 0x0 0x1000>;
971
-		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
972
-		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
973
-		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
974
-		status = "disabled";
975
-	};
976
-
977
-	iep: iep@ff3a0000 {
978
-		compatible = "rockchip,iep";
979
-		iommu_enabled = <1>;
980
-		iommus = <&iep_mmu>;
981
-		reg = <0x0 0xff3a0000 0x0 0x800>;
982
-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
983
-		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
984
-		clock-names = "aclk_iep", "hclk_iep";
985
-		power-domains = <&power RK3328_PD_VIDEO>;
986
-		allocator = <1>;
987
-		version = <2>;
988
-		status = "disabled";
989
-	};
990
-
991
-	iep_mmu: iommu@ff3a0800 {
992
-		compatible = "rockchip,iommu";
993
-		reg = <0x0 0xff3a0800 0x0 0x40>;
994
-		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
995
-		interrupt-names = "iep_mmu";
996
-		clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
997
-		clock-names = "aclk", "iface";
998
-		power-domains = <&power RK3328_PD_VIDEO>;
999
-		#iommu-cells = <0>;
1000
-		status = "disabled";
1001
-	};
1002
-
1003717 	hdmi: hdmi@ff3c0000 {
1004718 		compatible = "rockchip,rk3328-dw-hdmi";
1005719 		reg = <0x0 0xff3c0000 0x0 0x20000>;
....@@ -1008,87 +722,48 @@
1008722 			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1009723 		clocks = <&cru PCLK_HDMI>,
1010724 			 <&cru SCLK_HDMI_SFC>,
1011
-			 <&cru SCLK_RTC32K>,
1012
-			 <&cru HCLK_VIO>;
725
+			 <&cru SCLK_RTC32K>;
1013726 		clock-names = "iahb",
1014727 			      "isfr",
1015
-			      "cec",
1016
-			      "hclk_vio";
728
+			      "cec";
1017729 		phys = <&hdmiphy>;
1018730 		phy-names = "hdmi";
1019
-		pinctrl-names = "default", "gpio";
731
+		pinctrl-names = "default";
1020732 		pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
1021
-		pinctrl-1 = <&i2c3_gpio>;
1022
-		resets = <&cru SRST_HDMI_P>,
1023
-			 <&cru SRST_HDMIPHY>;
1024
-		reset-names = "hdmi",
1025
-			      "hdmiphy";
1026733 		rockchip,grf = <&grf>;
1027
-		max-tmdsclk = <371250>;
734
+		#sound-dai-cells = <0>;
1028735 		status = "disabled";
1029736 
1030737 		ports {
1031738 			hdmi_in: port {
1032
-				#address-cells = <1>;
1033
-				#size-cells = <0>;
1034
-				hdmi_in_vop: endpoint@0 {
1035
-					reg = <0>;
739
+				hdmi_in_vop: endpoint {
1036740 					remote-endpoint = <&vop_out_hdmi>;
1037741 				};
1038742 			};
1039743 		};
1040744 	};
1041745 
1042
-	tve: tve@ff373e00 {
1043
-		compatible = "rockchip,rk3328-tve";
1044
-		reg = <0x0 0xff373e00 0x0 0x100>,
1045
-		      <0x0 0xff420000 0x0 0x10000>;
1046
-		rockchip,saturation = <0x00376749>;
1047
-		rockchip,brightcontrast = <0x0000a305>;
1048
-		rockchip,adjtiming = <0xb6c00880>;
1049
-		rockchip,lumafilter0 = <0x01ff0000>;
1050
-		rockchip,lumafilter1 = <0xf40200fe>;
1051
-		rockchip,lumafilter2 = <0xf332d70c>;
1052
-		rockchip,daclevel = <0x22>;
1053
-		rockchip,dac1level = <0x7>;
1054
-		status = "disabled";
1055
-
1056
-		ports {
1057
-			tve_in: port {
1058
-				#address-cells = <1>;
1059
-				#size-cells = <0>;
1060
-				tve_in_vop: endpoint@0 {
1061
-					reg = <0>;
1062
-					remote-endpoint = <&vop_out_tve>;
1063
-				};
1064
-			};
1065
-		};
1066
-	};
1067
-
1068
-	display_subsystem: display-subsystem {
1069
-		compatible = "rockchip,display-subsystem";
1070
-		ports = <&vop_out>;
1071
-		status = "disabled";
1072
-	};
1073
-
1074746 	codec: codec@ff410000 {
1075747 		compatible = "rockchip,rk3328-codec";
1076748 		reg = <0x0 0xff410000 0x0 0x1000>;
1077
-		rockchip,grf = <&grf>;
1078
-		clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S1>;
749
+		clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
1079750 		clock-names = "pclk", "mclk";
751
+		rockchip,grf = <&grf>;
752
+		#sound-dai-cells = <0>;
1080753 		status = "disabled";
1081754 	};
1082755 
1083
-	hdmiphy: hdmiphy@ff430000 {
756
+	hdmiphy: phy@ff430000 {
1084757 		compatible = "rockchip,rk3328-hdmi-phy";
1085758 		reg = <0x0 0xff430000 0x0 0x10000>;
1086759 		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1087
-		#phy-cells = <0>;
1088
-		clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
1089
-		clock-names = "sysclk", "refclk";
1090
-		#clock-cells = <0>;
760
+		clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
761
+		clock-names = "sysclk", "refoclk", "refpclk";
1091762 		clock-output-names = "hdmi_phy";
763
+		#clock-cells = <0>;
764
+		nvmem-cells = <&efuse_cpu_version>;
765
+		nvmem-cell-names = "cpu-version";
766
+		#phy-cells = <0>;
1092767 		status = "disabled";
1093768 	};
1094769 
....@@ -1109,7 +784,8 @@
1109784 			<&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
1110785 			<&cru SCLK_UART1>, <&cru SCLK_UART2>,
1111786 			<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
1112
-			<&cru ACLK_RGA_PRE>, <&cru ACLK_RKVDEC_PRE>,
787
+			<&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
788
+			<&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
1113789 			<&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
1114790 			<&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
1115791 			<&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
....@@ -1119,8 +795,7 @@
1119795 			<&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
1120796 			<&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
1121797 			<&cru HCLK_PERI>, <&cru PCLK_PERI>,
1122
-			<&cru SCLK_RTC32K>, <&cru ACLK_VOP>,
1123
-			<&cru ACLK_GMAC>;
798
+			<&cru SCLK_RTC32K>;
1124799 		assigned-clock-parents =
1125800 			<&cru HDMIPHY>, <&cru PLL_APLL>,
1126801 			<&cru PLL_GPLL>, <&xin24m>,
....@@ -1131,6 +806,7 @@
1131806 			<24000000>, <24000000>,
1132807 			<15000000>, <15000000>,
1133808 			<100000000>, <100000000>,
809
+			<100000000>, <100000000>,
1134810 			<50000000>, <100000000>,
1135811 			<100000000>, <100000000>,
1136812 			<50000000>, <50000000>,
....@@ -1140,8 +816,7 @@
1140816 			<150000000>, <75000000>,
1141817 			<75000000>, <150000000>,
1142818 			<75000000>, <75000000>,
1143
-			<32768>, <400000000>,
1144
-			<180000000>;
819
+			<32768>;
1145820 	};
1146821 
1147822 	usb2phy_grf: syscon@ff450000 {
....@@ -1181,48 +856,7 @@
1181856 		};
1182857 	};
1183858 
1184
-	usb3phy_grf: syscon@ff460000 {
1185
-		compatible = "rockchip,usb3phy-grf", "syscon";
1186
-		reg = <0x0 0xff460000 0x0 0x1000>;
1187
-	};
1188
-
1189
-	u3phy: usb3-phy@ff470000 {
1190
-		compatible = "rockchip,rk3328-u3phy";
1191
-		reg = <0x0 0xff470000 0x0 0x0>;
1192
-		rockchip,u3phygrf = <&usb3phy_grf>;
1193
-		rockchip,grf = <&grf>;
1194
-		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1195
-		interrupt-names = "linestate";
1196
-		clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
1197
-		clock-names = "u3phy-otg", "u3phy-pipe";
1198
-		resets = <&cru SRST_USB3PHY_U2>,
1199
-			 <&cru SRST_USB3PHY_U3>,
1200
-			 <&cru SRST_USB3PHY_PIPE>,
1201
-			 <&cru SRST_USB3OTG_UTMI>,
1202
-			 <&cru SRST_USB3PHY_OTG_P>,
1203
-			 <&cru SRST_USB3PHY_PIPE_P>;
1204
-		reset-names = "u3phy-u2-por", "u3phy-u3-por",
1205
-			      "u3phy-pipe-mac", "u3phy-utmi-mac",
1206
-			      "u3phy-utmi-apb", "u3phy-pipe-apb";
1207
-		#address-cells = <2>;
1208
-		#size-cells = <2>;
1209
-		ranges;
1210
-		status = "disabled";
1211
-
1212
-		u3phy_utmi: utmi@ff470000 {
1213
-			reg = <0x0 0xff470000 0x0 0x8000>;
1214
-			#phy-cells = <0>;
1215
-			status = "disabled";
1216
-		};
1217
-
1218
-		u3phy_pipe: pipe@ff478000 {
1219
-			reg = <0x0 0xff478000 0x0 0x8000>;
1220
-			#phy-cells = <0>;
1221
-			status = "disabled";
1222
-		};
1223
-	};
1224
-
1225
-	sdmmc: dwmmc@ff500000 {
859
+	sdmmc: mmc@ff500000 {
1226860 		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1227861 		reg = <0x0 0xff500000 0x0 0x4000>;
1228862 		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
....@@ -1234,7 +868,7 @@
1234868 		status = "disabled";
1235869 	};
1236870 
1237
-	sdio: dwmmc@ff510000 {
871
+	sdio: mmc@ff510000 {
1238872 		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1239873 		reg = <0x0 0xff510000 0x0 0x4000>;
1240874 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
....@@ -1246,7 +880,7 @@
1246880 		status = "disabled";
1247881 	};
1248882 
1249
-	emmc: dwmmc@ff520000 {
883
+	emmc: mmc@ff520000 {
1250884 		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1251885 		reg = <0x0 0xff520000 0x0 0x4000>;
1252886 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
....@@ -1274,6 +908,7 @@
1274908 		resets = <&cru SRST_GMAC2IO_A>;
1275909 		reset-names = "stmmaceth";
1276910 		rockchip,grf = <&grf>;
911
+		snps,txpbl = <0x4>;
1277912 		status = "disabled";
1278913 	};
1279914 
....@@ -1295,6 +930,8 @@
1295930 		reset-names = "stmmaceth", "mac-phy";
1296931 		phy-mode = "rmii";
1297932 		phy-handle = <&phy>;
933
+		snps,txpbl = <0x4>;
934
+		clock_in_out = "output";
1298935 		status = "disabled";
1299936 
1300937 		mdio {
....@@ -1302,7 +939,7 @@
1302939 			#address-cells = <1>;
1303940 			#size-cells = <0>;
1304941 
1305
-			phy: phy@0 {
942
+			phy: ethernet-phy@0 {
1306943 				compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
1307944 				reg = <0>;
1308945 				clocks = <&cru SCLK_MAC2PHY_OUT>;
....@@ -1325,7 +962,6 @@
1325962 		g-np-tx-fifo-size = <16>;
1326963 		g-rx-fifo-size = <280>;
1327964 		g-tx-fifo-size = <256 128 128 64 32 16>;
1328
-		g-use-dma;
1329965 		phys = <&u2phy_otg>;
1330966 		phy-names = "usb2-phy";
1331967 		status = "disabled";
....@@ -1336,7 +972,6 @@
1336972 		reg = <0x0 0xff5c0000 0x0 0x10000>;
1337973 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1338974 		clocks = <&cru HCLK_HOST0>, <&u2phy>;
1339
-		clock-names = "usbhost", "utmi";
1340975 		phys = <&u2phy_host>;
1341976 		phy-names = "usb";
1342977 		status = "disabled";
....@@ -1347,166 +982,30 @@
1347982 		reg = <0x0 0xff5d0000 0x0 0x10000>;
1348983 		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1349984 		clocks = <&cru HCLK_HOST0>, <&u2phy>;
1350
-		clock-names = "usbhost", "utmi";
1351985 		phys = <&u2phy_host>;
1352986 		phy-names = "usb";
1353987 		status = "disabled";
1354988 	};
1355989 
1356
-	sdmmc_ext: dwmmc@ff5f0000 {
1357
-		compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
1358
-		reg = <0x0 0xff5f0000 0x0 0x4000>;
1359
-		clock-freq-min-max = <400000 150000000>;
1360
-		clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>,
1361
-			 <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>;
1362
-		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1363
-		fifo-depth = <0x100>;
1364
-		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1365
-		status = "disabled";
1366
-	};
1367
-
1368990 	usbdrd3: usb@ff600000 {
1369
-		compatible = "rockchip,rk3328-dwc3";
991
+		compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
992
+		reg = <0x0 0xff600000 0x0 0x100000>;
993
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1370994 		clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
1371995 			 <&cru ACLK_USB3OTG>;
1372996 		clock-names = "ref_clk", "suspend_clk",
1373997 			      "bus_clk";
1374
-		#address-cells = <2>;
1375
-		#size-cells = <2>;
1376
-		ranges;
998
+		dr_mode = "otg";
999
+		phy_type = "utmi_wide";
1000
+		snps,dis-del-phy-power-chg-quirk;
1001
+		snps,dis_enblslpm_quirk;
1002
+		snps,dis-tx-ipgap-linecheck-quirk;
1003
+		snps,dis-u2-freeclk-exists-quirk;
1004
+		snps,dis_u2_susphy_quirk;
1005
+		snps,dis_u3_susphy_quirk;
1006
+		snps,parkmode-disable-hs-quirk;
1007
+		snps,parkmode-disable-ss-quirk;
13771008 		status = "disabled";
1378
-
1379
-		usbdrd_dwc3: dwc3@ff600000 {
1380
-			compatible = "snps,dwc3";
1381
-			reg = <0x0 0xff600000 0x0 0x100000>;
1382
-			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1383
-			dr_mode = "host";
1384
-			phys = <&u3phy_utmi>, <&u3phy_pipe>;
1385
-			phy-names = "usb2-phy", "usb3-phy";
1386
-			phy_type = "utmi_wide";
1387
-			snps,dis_enblslpm_quirk;
1388
-			snps,dis-u2-freeclk-exists-quirk;
1389
-			snps,dis_u2_susphy_quirk;
1390
-			snps,dis-u3-autosuspend-quirk;
1391
-			snps,dis_u3_susphy_quirk;
1392
-			snps,dis-del-phy-power-chg-quirk;
1393
-			snps,tx-ipgap-linecheck-dis-quirk;
1394
-			status = "disabled";
1395
-		};
1396
-	};
1397
-
1398
-	qos_rkvdec_r: qos@ff750000 {
1399
-		compatible = "syscon";
1400
-		reg = <0x0 0xff750000 0x0 0x20>;
1401
-	};
1402
-
1403
-	qos_rkvdec_w: qos@ff750080 {
1404
-		compatible = "syscon";
1405
-		reg = <0x0 0xff750080 0x0 0x20>;
1406
-	};
1407
-
1408
-	qos_vpu: qos@ff778000 {
1409
-		compatible = "syscon";
1410
-		reg = <0x0 0xff778000 0x0 0x20>;
1411
-	};
1412
-
1413
-	dfi: dfi@ff790000 {
1414
-		reg = <0x00 0xff790000 0x00 0x400>;
1415
-		compatible = "rockchip,rk3328-dfi";
1416
-		rockchip,grf = <&grf>;
1417
-		status = "disabled";
1418
-	};
1419
-
1420
-	dmc: dmc {
1421
-		compatible = "rockchip,rk3328-dmc";
1422
-		devfreq-events = <&dfi>;
1423
-		clocks = <&cru SCLK_DDRCLK>;
1424
-		clock-names = "dmc_clk";
1425
-		operating-points-v2 = <&dmc_opp_table>;
1426
-		ddr_timing = <&ddr_timing>;
1427
-		upthreshold = <40>;
1428
-		downdifferential = <20>;
1429
-		system-status-freq = <
1430
-			/*system status         freq(KHz)*/
1431
-			SYS_STATUS_NORMAL       786000
1432
-			SYS_STATUS_REBOOT       786000
1433
-			SYS_STATUS_SUSPEND      786000
1434
-			SYS_STATUS_VIDEO_1080P  786000
1435
-			SYS_STATUS_VIDEO_4K     786000
1436
-			SYS_STATUS_VIDEO_4K_10B 933000
1437
-			SYS_STATUS_PERFORMANCE  933000
1438
-			SYS_STATUS_BOOST        933000
1439
-		>;
1440
-		auto-min-freq = <786000>;
1441
-		auto-freq-en = <0>;
1442
-		#cooling-cells = <2>;
1443
-		status = "disabled";
1444
-
1445
-		ddr_power_model: ddr_power_model {
1446
-			compatible = "ddr_power_model";
1447
-			dynamic-power-coefficient = <120>;
1448
-			static-power-coefficient = <200>;
1449
-			ts = <32000 4700 (-80) 2>;
1450
-			thermal-zone = "soc-thermal";
1451
-		};
1452
-	};
1453
-
1454
-	dmc_opp_table: dmc-opp-table {
1455
-		compatible = "operating-points-v2";
1456
-
1457
-		rockchip,leakage-voltage-sel = <
1458
-			1   10    0
1459
-			11  254   1
1460
-		>;
1461
-		nvmem-cells = <&logic_leakage>;
1462
-		nvmem-cell-names = "ddr_leakage";
1463
-
1464
-		opp-400000000 {
1465
-			opp-hz = /bits/ 64 <400000000>;
1466
-			opp-microvolt = <950000>;
1467
-			opp-microvolt-L0 = <950000>;
1468
-			opp-microvolt-L1 = <950000>;
1469
-			status = "disabled";
1470
-		};
1471
-		opp-600000000 {
1472
-			opp-hz = /bits/ 64 <600000000>;
1473
-			opp-microvolt = <1025000>;
1474
-			opp-microvolt-L0 = <1025000>;
1475
-			opp-microvolt-L1 = <1000000>;
1476
-			status = "disabled";
1477
-		};
1478
-		opp-786000000 {
1479
-			opp-hz = /bits/ 64 <786000000>;
1480
-			opp-microvolt = <1075000>;
1481
-			opp-microvolt-L0 = <1075000>;
1482
-			opp-microvolt-L1 = <1050000>;
1483
-		};
1484
-		opp-800000000 {
1485
-			opp-hz = /bits/ 64 <800000000>;
1486
-			opp-microvolt = <1075000>;
1487
-			opp-microvolt-L0 = <1075000>;
1488
-			opp-microvolt-L1 = <1050000>;
1489
-		};
1490
-		opp-850000000 {
1491
-			opp-hz = /bits/ 64 <850000000>;
1492
-			opp-microvolt = <1075000>;
1493
-			opp-microvolt-L0 = <1075000>;
1494
-			opp-microvolt-L1 = <1050000>;
1495
-		};
1496
-		opp-933000000 {
1497
-			opp-hz = /bits/ 64 <933000000>;
1498
-			opp-microvolt = <1125000>;
1499
-			opp-microvolt-L0 = <1125000>;
1500
-			opp-microvolt-L1 = <1100000>;
1501
-		};
1502
-		/* 1066M is only for ddr4 */
1503
-		opp-1066000000 {
1504
-			opp-hz = /bits/ 64 <1066000000>;
1505
-			opp-microvolt = <1175000>;
1506
-			opp-microvolt-L0 = <1175000>;
1507
-			opp-microvolt-L1 = <1150000>;
1508
-			status = "disabled";
1509
-		};
15101009 	};
15111010 
15121011 	gic: interrupt-controller@ff811000 {
....@@ -1681,49 +1180,10 @@
16811180 				rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
16821181 						<0 RK_PA6 2 &pcfg_pull_none>;
16831182 			};
1684
-			i2c3_gpio: i2c3-gpio {
1183
+			i2c3_pins: i2c3-pins {
16851184 				rockchip,pins =
16861185 					<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
16871186 					<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1688
-			};
1689
-		};
1690
-
1691
-		tsp {
1692
-			tsp_d0: tsp-d0 {
1693
-				rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
1694
-			};
1695
-			tsp_d1: tsp-d1 {
1696
-				rockchip,pins = <3 RK_PA5 1 &pcfg_pull_none>;
1697
-			};
1698
-			tsp_d2: tsp-d2 {
1699
-				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>;
1700
-			};
1701
-			tsp_d3: tsp-d3 {
1702
-				rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>;
1703
-			};
1704
-			tsp_d4: tsp-d4 {
1705
-				rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>;
1706
-			};
1707
-			tsp_d5: tsp-d5 {
1708
-				rockchip,pins = <2 RK_PC0 3 &pcfg_pull_none>;
1709
-			};
1710
-			tsp_d6: tsp-d6 {
1711
-				rockchip,pins = <2 RK_PC1 3 &pcfg_pull_none>;
1712
-			};
1713
-			tsp_d7: tsp-d7 {
1714
-				rockchip,pins = <2 RK_PC2 3 &pcfg_pull_none>;
1715
-			};
1716
-			tsp_sync: tsp-sync {
1717
-				rockchip,pins = <2 RK_PB7 3 &pcfg_pull_none>;
1718
-			};
1719
-			tsp_clk: tsp-clk {
1720
-				rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>;
1721
-			};
1722
-			tsp_fail: tsp-fail {
1723
-				rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1724
-			};
1725
-			tsp_valid: tsp-valid {
1726
-				rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>;
17271187 			};
17281188 		};
17291189 
....@@ -1791,7 +1251,7 @@
17911251 		};
17921252 
17931253 		tsadc {
1794
-			otp_gpio: otp-gpio {
1254
+			otp_pin: otp-pin {
17951255 				rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
17961256 			};
17971257 
....@@ -1802,7 +1262,7 @@
18021262 
18031263 		uart0 {
18041264 			uart0_xfer: uart0-xfer {
1805
-				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1265
+				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
18061266 						<1 RK_PB0 1 &pcfg_pull_up>;
18071267 			};
18081268 
....@@ -1814,14 +1274,14 @@
18141274 				rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
18151275 			};
18161276 
1817
-			uart0_rts_gpio: uart0-rts-gpio {
1277
+			uart0_rts_pin: uart0-rts-pin {
18181278 				rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
18191279 			};
18201280 		};
18211281 
18221282 		uart1 {
18231283 			uart1_xfer: uart1-xfer {
1824
-				rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1284
+				rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>,
18251285 						<3 RK_PA6 4 &pcfg_pull_up>;
18261286 			};
18271287 
....@@ -1833,21 +1293,21 @@
18331293 				rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
18341294 			};
18351295 
1836
-			uart1_rts_gpio: uart1-rts-gpio {
1296
+			uart1_rts_pin: uart1-rts-pin {
18371297 				rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
18381298 			};
18391299 		};
18401300 
18411301 		uart2-0 {
18421302 			uart2m0_xfer: uart2m0-xfer {
1843
-				rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1303
+				rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>,
18441304 						<1 RK_PA1 2 &pcfg_pull_up>;
18451305 			};
18461306 		};
18471307 
18481308 		uart2-1 {
18491309 			uart2m1_xfer: uart2m1-xfer {
1850
-				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1310
+				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
18511311 						<2 RK_PA1 1 &pcfg_pull_up>;
18521312 			};
18531313 		};
....@@ -2059,7 +1519,7 @@
20591519 				rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
20601520 			};
20611521 
2062
-			sdmmc0m0_gpio: sdmmc0m0-gpio {
1522
+			sdmmc0m0_pin: sdmmc0m0-pin {
20631523 				rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
20641524 			};
20651525 		};
....@@ -2069,7 +1529,7 @@
20691529 				rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
20701530 			};
20711531 
2072
-			sdmmc0m1_gpio: sdmmc0m1-gpio {
1532
+			sdmmc0m1_pin: sdmmc0m1-pin {
20731533 				rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
20741534 			};
20751535 		};
....@@ -2102,7 +1562,7 @@
21021562 						<1 RK_PA3 1 &pcfg_pull_up_8ma>;
21031563 			};
21041564 
2105
-			sdmmc0_gpio: sdmmc0-gpio {
1565
+			sdmmc0_pins: sdmmc0-pins {
21061566 				rockchip,pins =
21071567 					<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
21081568 					<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
....@@ -2144,7 +1604,7 @@
21441604 					<3 RK_PA7 3 &pcfg_pull_up_4ma>;
21451605 			};
21461606 
2147
-			sdmmc0ext_gpio: sdmmc0ext-gpio {
1607
+			sdmmc0ext_pins: sdmmc0ext-pins {
21481608 				rockchip,pins =
21491609 					<3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
21501610 					<3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
....@@ -2189,7 +1649,7 @@
21891649 						<1 RK_PC1 1 &pcfg_pull_up_8ma>;
21901650 			};
21911651 
2192
-			sdmmc1_gpio: sdmmc1-gpio {
1652
+			sdmmc1_pins: sdmmc1-pins {
21931653 				rockchip,pins =
21941654 					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
21951655 					<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
....@@ -2249,21 +1709,11 @@
22491709 			pwm0_pin: pwm0-pin {
22501710 				rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
22511711 			};
2252
-
2253
-			pwm0_pin_pull_up: pwm0-pin-pull-up {
2254
-				rockchip,pins =
2255
-					<2 RK_PA4 1 &pcfg_pull_up>;
2256
-			};
22571712 		};
22581713 
22591714 		pwm1 {
22601715 			pwm1_pin: pwm1-pin {
22611716 				rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
2262
-			};
2263
-
2264
-			pwm1_pin_pull_up: pwm1-pin-pull-up {
2265
-				rockchip,pins =
2266
-					<2 RK_PA5 1 &pcfg_pull_up>;
22671717 			};
22681718 		};
22691719 
....@@ -2368,28 +1818,12 @@
23681818 		};
23691819 
23701820 		gmac2phy {
2371
-			fephyled_speed100: fephyled-speed100 {
2372
-				rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
2373
-			};
2374
-
23751821 			fephyled_speed10: fephyled-speed10 {
23761822 				rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
23771823 			};
23781824 
23791825 			fephyled_duplex: fephyled-duplex {
23801826 				rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
2381
-			};
2382
-
2383
-			fephyled_rxm0: fephyled-rxm0 {
2384
-				rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
2385
-			};
2386
-
2387
-			fephyled_txm0: fephyled-txm0 {
2388
-				rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
2389
-			};
2390
-
2391
-			fephyled_linkm0: fephyled-linkm0 {
2392
-				rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
23931827 			};
23941828 
23951829 			fephyled_rxm1: fephyled-rxm1 {
....@@ -2409,7 +1843,7 @@
24091843 			tsadc_int: tsadc-int {
24101844 				rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
24111845 			};
2412
-			tsadc_gpio: tsadc-gpio {
1846
+			tsadc_pin: tsadc-pin {
24131847 				rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
24141848 			};
24151849 		};