~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,7 +1,6 @@
	1	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
1	2	/*
2		- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3		- *
4		- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	3	+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
5	4	*/
6	5
7	6	#include <dt-bindings/clock/px30-cru.h>
..	..	@@ -42,6 +41,7 @@
42	41	serial5 = &uart5;
43	42	spi0 = &spi0;
44	43	spi1 = &spi1;
	44	+ spi2 = &sfc;
45	45	};
46	46
47	47	cpus {
..	..	@@ -50,39 +50,50 @@
50	50
51	51	cpu0: cpu@0 {
52	52	device_type = "cpu";
53		- compatible = "arm,cortex-a35", "arm,armv8";
	53	+ compatible = "arm,cortex-a35";
54	54	reg = <0x0 0x0>;
55	55	enable-method = "psci";
56	56	clocks = <&cru ARMCLK>;
57	57	#cooling-cells = <2>;
	58	+ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
58	59	dynamic-power-coefficient = <90>;
59	60	operating-points-v2 = <&cpu0_opp_table>;
60		- cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61	61	};
62	62
63	63	cpu1: cpu@1 {
64	64	device_type = "cpu";
65		- compatible = "arm,cortex-a35", "arm,armv8";
	65	+ compatible = "arm,cortex-a35";
66	66	reg = <0x0 0x1>;
67	67	enable-method = "psci";
68		- operating-points-v2 = <&cpu0_opp_table>;
	68	+ clocks = <&cru ARMCLK>;
	69	+ #cooling-cells = <2>;
69	70	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	71	+ dynamic-power-coefficient = <90>;
	72	+ operating-points-v2 = <&cpu0_opp_table>;
70	73	};
	74	+
71	75	cpu2: cpu@2 {
72	76	device_type = "cpu";
73		- compatible = "arm,cortex-a35", "arm,armv8";
	77	+ compatible = "arm,cortex-a35";
74	78	reg = <0x0 0x2>;
75	79	enable-method = "psci";
76		- operating-points-v2 = <&cpu0_opp_table>;
	80	+ clocks = <&cru ARMCLK>;
	81	+ #cooling-cells = <2>;
77	82	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	83	+ dynamic-power-coefficient = <90>;
	84	+ operating-points-v2 = <&cpu0_opp_table>;
78	85	};
	86	+
79	87	cpu3: cpu@3 {
80	88	device_type = "cpu";
81		- compatible = "arm,cortex-a35", "arm,armv8";
	89	+ compatible = "arm,cortex-a35";
82	90	reg = <0x0 0x3>;
83	91	enable-method = "psci";
84		- operating-points-v2 = <&cpu0_opp_table>;
	92	+ clocks = <&cru ARMCLK>;
	93	+ #cooling-cells = <2>;
85	94	cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
	95	+ dynamic-power-coefficient = <90>;
	96	+ operating-points-v2 = <&cpu0_opp_table>;
86	97	};
87	98
88	99	idle-states {
..	..	@@ -335,12 +346,34 @@
335	346	};
336	347
337	348	arm-pmu {
338		- compatible = "arm,cortex-a53-pmu";
	349	+ compatible = "arm,cortex-a35-pmu";
339	350	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
340	351	<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
341	352	<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
342	353	<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
343	354	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	355	+ };
	356	+
	357	+ bus_soc: bus-soc {
	358	+ compatible = "rockchip,px30-bus";
	359	+ rockchip,busfreq-policy = "autocs";
	360	+ soc-bus0 {
	361	+ bus-id = <0>;
	362	+ timer-us = <20>;
	363	+ enable-msk = <0x40f7>;
	364	+ };
	365	+ soc-bus1 {
	366	+ bus-id = <1>;
	367	+ timer-us = <200>;
	368	+ enable-msk = <0x40bf>;
	369	+ status = "disabled";
	370	+ };
	371	+ soc-bus2 {
	372	+ bus-id = <2>;
	373	+ timer-us = <200>;
	374	+ enable-msk = <0x4007>;
	375	+ status = "disabled";
	376	+ };
344	377	};
345	378
346	379	bus_apll: bus-apll {
..	..	@@ -368,7 +401,7 @@
368	401
369	402	cpuinfo {
370	403	compatible = "rockchip,cpuinfo";
371		- nvmem-cells = <&otp_id>;
	404	+ nvmem-cells = <&cpu_id>;
372	405	nvmem-cell-names = "id";
373	406	};
374	407
..	..	@@ -445,6 +478,55 @@
445	478	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
446	479	};
447	480
	481	+ thermal_zones: thermal-zones {
	482	+ soc_thermal: soc-thermal {
	483	+ polling-delay-passive = <20>;
	484	+ polling-delay = <1000>;
	485	+ sustainable-power = <750>;
	486	+ thermal-sensors = <&tsadc 0>;
	487	+
	488	+ trips {
	489	+ threshold: trip-point-0 {
	490	+ temperature = <70000>;
	491	+ hysteresis = <2000>;
	492	+ type = "passive";
	493	+ };
	494	+
	495	+ target: trip-point-1 {
	496	+ temperature = <85000>;
	497	+ hysteresis = <2000>;
	498	+ type = "passive";
	499	+ };
	500	+
	501	+ soc_crit: soc-crit {
	502	+ temperature = <115000>;
	503	+ hysteresis = <2000>;
	504	+ type = "critical";
	505	+ };
	506	+ };
	507	+
	508	+ cooling-maps {
	509	+ map0 {
	510	+ trip = <&target>;
	511	+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	512	+ contribution = <4096>;
	513	+ };
	514	+
	515	+ map1 {
	516	+ trip = <&target>;
	517	+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	518	+ contribution = <4096>;
	519	+ };
	520	+ };
	521	+ };
	522	+
	523	+ gpu_thermal: gpu-thermal {
	524	+ polling-delay-passive = <100>; /* milliseconds */
	525	+ polling-delay = <1000>; /* milliseconds */
	526	+ thermal-sensors = <&tsadc 1>;
	527	+ };
	528	+ };
	529	+
448	530	xin24m: xin24m {
449	531	compatible = "fixed-clock";
450	532	#clock-cells = <0>;
..	..	@@ -475,20 +557,20 @@
475	557	#size-cells = <0>;
476	558
477	559	/* These power domains are grouped by VD_LOGIC */
478		- pd_usb@PX30_PD_USB {
	560	+ power-domain@PX30_PD_USB {
479	561	reg = <PX30_PD_USB>;
480	562	clocks = <&cru HCLK_HOST>,
481	563	<&cru HCLK_OTG>,
482	564	<&cru SCLK_OTG_ADP>;
483	565	pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
484	566	};
485		- pd_sdcard@PX30_PD_SDCARD {
	567	+ power-domain@PX30_PD_SDCARD {
486	568	reg = <PX30_PD_SDCARD>;
487	569	clocks = <&cru HCLK_SDMMC>,
488	570	<&cru SCLK_SDMMC>;
489	571	pm_qos = <&qos_sdmmc>;
490	572	};
491		- pd_gmac@PX30_PD_GMAC {
	573	+ power-domain@PX30_PD_GMAC {
492	574	reg = <PX30_PD_GMAC>;
493	575	clocks = <&cru ACLK_GMAC>,
494	576	<&cru PCLK_GMAC>,
..	..	@@ -496,7 +578,7 @@
496	578	<&cru SCLK_GMAC_RX_TX>;
497	579	pm_qos = <&qos_gmac>;
498	580	};
499		- pd_mmc_nand@PX30_PD_MMC_NAND {
	581	+ power-domain@PX30_PD_MMC_NAND {
500	582	reg = <PX30_PD_MMC_NAND>;
501	583	clocks = <&cru HCLK_NANDC>,
502	584	<&cru HCLK_EMMC>,
..	..	@@ -509,14 +591,14 @@
509	591	pm_qos = <&qos_emmc>, <&qos_nand>,
510	592	<&qos_sdio>, <&qos_sfc>;
511	593	};
512		- pd_vpu@PX30_PD_VPU {
	594	+ power-domain@PX30_PD_VPU {
513	595	reg = <PX30_PD_VPU>;
514	596	clocks = <&cru ACLK_VPU>,
515	597	<&cru HCLK_VPU>,
516	598	<&cru SCLK_CORE_VPU>;
517	599	pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
518	600	};
519		- pd_vo@PX30_PD_VO {
	601	+ power-domain@PX30_PD_VO {
520	602	reg = <PX30_PD_VO>;
521	603	clocks = <&cru ACLK_RGA>,
522	604	<&cru ACLK_VOPB>,
..	..	@@ -532,7 +614,7 @@
532	614	pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
533	615	<&qos_vop_m0>, <&qos_vop_m1>;
534	616	};
535		- pd_vi@PX30_PD_VI {
	617	+ power-domain@PX30_PD_VI {
536	618	reg = <PX30_PD_VI>;
537	619	clocks = <&cru ACLK_CIF>,
538	620	<&cru ACLK_ISP>,
..	..	@@ -543,7 +625,7 @@
543	625	<&qos_isp_wr>, <&qos_isp_m1>,
544	626	<&qos_vip>;
545	627	};
546		- pd_gpu@PX30_PD_GPU {
	628	+ power-domain@PX30_PD_GPU {
547	629	reg = <PX30_PD_GPU>;
548	630	clocks = <&cru SCLK_GPU>;
549	631	pm_qos = <&qos_gpu>;
..	..	@@ -566,12 +648,10 @@
566	648	compatible = "syscon-reboot-mode";
567	649	offset = <0x200>;
568	650	mode-bootloader = <BOOT_BL_DOWNLOAD>;
569		- mode-charge = <BOOT_CHARGING>;
570	651	mode-fastboot = <BOOT_FASTBOOT>;
571	652	mode-loader = <BOOT_BL_DOWNLOAD>;
572	653	mode-normal = <BOOT_NORMAL>;
573	654	mode-recovery = <BOOT_RECOVERY>;
574		- mode-ums = <BOOT_UMS>;
575	655	};
576	656
577	657	pmu_pvtm: pmu-pvtm {
..	..	@@ -594,9 +674,11 @@
594	674	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
595	675	clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
596	676	clock-names = "baudclk", "apb_pclk";
	677	+ dmas = <&dmac 0>, <&dmac 1>;
	678	+ /You can add it to enable dma/
	679	+ /dma-names = "tx", "rx";/
597	680	reg-shift = <2>;
598	681	reg-io-width = <4>;
599		- dmas = <&dmac 0>, <&dmac 1>;
600	682	pinctrl-names = "default";
601	683	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
602	684	status = "disabled";
..	..	@@ -638,13 +720,10 @@
638	720	clock-names = "i2s_clk", "i2s_hclk";
639	721	dmas = <&dmac 18>, <&dmac 19>;
640	722	dma-names = "tx", "rx";
641		- resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>;
642		- reset-names = "reset-m", "reset-h";
643	723	pinctrl-names = "default";
644		- pinctrl-0 = <&i2s1_2ch_sclk
645		- &i2s1_2ch_lrck
646		- &i2s1_2ch_sdi
647		- &i2s1_2ch_sdo>;
	724	+ pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
	725	+ &i2s1_2ch_sdi &i2s1_2ch_sdo>;
	726	+ #sound-dai-cells = <0>;
648	727	status = "disabled";
649	728	};
650	729
..	..	@@ -656,32 +735,10 @@
656	735	clock-names = "i2s_clk", "i2s_hclk";
657	736	dmas = <&dmac 20>, <&dmac 21>;
658	737	dma-names = "tx", "rx";
659		- resets = <&cru SRST_I2S2>, <&cru SRST_I2S2_H>;
660		- reset-names = "reset-m", "reset-h";
661	738	pinctrl-names = "default";
662		- pinctrl-0 = <&i2s2_2ch_sclk
663		- &i2s2_2ch_lrck
664		- &i2s2_2ch_sdi
665		- &i2s2_2ch_sdo>;
666		- status = "disabled";
667		- };
668		-
669		- pdm: pdm@ff0a0000 {
670		- compatible = "rockchip,px30-pdm";
671		- reg = <0x0 0xff0a0000 0x0 0x1000>;
672		- clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
673		- clock-names = "pdm_clk", "pdm_hclk";
674		- dmas = <&dmac 24>;
675		- dma-names = "rx";
676		- resets = <&cru SRST_PDM>;
677		- reset-names = "pdm-m";
678		- pinctrl-names = "default";
679		- pinctrl-0 = <&pdm_clk0m0
680		- &pdm_clk1
681		- &pdm_sdi0m0
682		- &pdm_sdi1
683		- &pdm_sdi2
684		- &pdm_sdi3>;
	739	+ pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
	740	+ &i2s2_2ch_sdi &i2s2_2ch_sdo>;
	741	+ #sound-dai-cells = <0>;
685	742	status = "disabled";
686	743	};
687	744
..	..	@@ -690,7 +747,7 @@
690	747	reg = <0x0 0xff0b0000 0x0 0x400>, <0x0 0xff0b0480 0x0 0x3B80>;
691	748	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
692	749	clocks = <&cru ACLK_CRYPTO >, <&cru HCLK_CRYPTO >,
693		- <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>;
	750	+ <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>;
694	751	clock-names = "aclk", "hclk", "sclk", "apb_pclk";
695	752	resets = <&cru SRST_CRYPTO>;
696	753	reset-names = "crypto-rst";
..	..	@@ -701,13 +758,13 @@
701	758	compatible = "rockchip,cryptov2-rng";
702	759	reg = <0x0 0xff0b0400 0x0 0x80>;
703	760	clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
704		- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
	761	+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
705	762	clock-names = "clk_crypto", "clk_crypto_apk",
706		- "aclk_crypto", "hclk_crypto";
	763	+ "aclk_crypto", "hclk_crypto";
707	764	assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
708		- <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
	765	+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
709	766	assigned-clock-rates = <150000000>, <150000000>,
710		- <200000000>, <200000000>;
	767	+ <200000000>, <200000000>;
711	768	resets = <&cru SRST_CRYPTO>;
712	769	reset-names = "reset";
713	770	status = "disabled";
..	..	@@ -752,12 +809,12 @@
752	809	#address-cells = <1>;
753	810	#size-cells = <0>;
754	811
755		- lvds_in_vopb: endpoint@0 {
	812	+ lvds_vopb_in: endpoint@0 {
756	813	reg = <0>;
757	814	remote-endpoint = <&vopb_out_lvds>;
758	815	};
759	816
760		- lvds_in_vopl: endpoint@1 {
	817	+ lvds_vopl_in: endpoint@1 {
761	818	reg = <1>;
762	819	remote-endpoint = <&vopl_out_lvds>;
763	820	};
..	..	@@ -821,9 +878,11 @@
821	878	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
822	879	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
823	880	clock-names = "baudclk", "apb_pclk";
	881	+ dmas = <&dmac 2>, <&dmac 3>;
	882	+ /You can add it to enable dma/
	883	+ /dma-names = "tx", "rx";/
824	884	reg-shift = <2>;
825	885	reg-io-width = <4>;
826		- dmas = <&dmac 2>, <&dmac 3>;
827	886	pinctrl-names = "default";
828	887	pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
829	888	status = "disabled";
..	..	@@ -835,9 +894,11 @@
835	894	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
836	895	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
837	896	clock-names = "baudclk", "apb_pclk";
	897	+ dmas = <&dmac 4>, <&dmac 5>;
	898	+ /You can add it to enable dma/
	899	+ /dma-names = "tx", "rx";/
838	900	reg-shift = <2>;
839	901	reg-io-width = <4>;
840		- dmas = <&dmac 4>, <&dmac 5>;
841	902	pinctrl-names = "default";
842	903	pinctrl-0 = <&uart2m0_xfer>;
843	904	status = "disabled";
..	..	@@ -849,9 +910,11 @@
849	910	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
850	911	clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
851	912	clock-names = "baudclk", "apb_pclk";
	913	+ dmas = <&dmac 6>, <&dmac 7>;
	914	+ /You can add it to enable dma/
	915	+ /dma-names = "tx", "rx";/
852	916	reg-shift = <2>;
853	917	reg-io-width = <4>;
854		- dmas = <&dmac 6>, <&dmac 7>;
855	918	pinctrl-names = "default";
856	919	pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
857	920	status = "disabled";
..	..	@@ -863,9 +926,11 @@
863	926	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
864	927	clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
865	928	clock-names = "baudclk", "apb_pclk";
	929	+ dmas = <&dmac 8>, <&dmac 9>;
	930	+ /You can add it to enable dma/
	931	+ /dma-names = "tx", "rx";/
866	932	reg-shift = <2>;
867	933	reg-io-width = <4>;
868		- dmas = <&dmac 8>, <&dmac 9>;
869	934	pinctrl-names = "default";
870	935	pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
871	936	status = "disabled";
..	..	@@ -877,16 +942,18 @@
877	942	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
878	943	clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
879	944	clock-names = "baudclk", "apb_pclk";
	945	+ dmas = <&dmac 10>, <&dmac 11>;
	946	+ /You can add it to enable dma/
	947	+ /dma-names = "tx", "rx";/
880	948	reg-shift = <2>;
881	949	reg-io-width = <4>;
882		- dmas = <&dmac 10>, <&dmac 11>;
883	950	pinctrl-names = "default";
884	951	pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
885	952	status = "disabled";
886	953	};
887	954
888	955	i2c0: i2c@ff180000 {
889		- compatible = "rockchip,rk3399-i2c";
	956	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
890	957	reg = <0x0 0xff180000 0x0 0x1000>;
891	958	clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
892	959	clock-names = "i2c", "pclk";
..	..	@@ -899,7 +966,7 @@
899	966	};
900	967
901	968	i2c1: i2c@ff190000 {
902		- compatible = "rockchip,rk3399-i2c";
	969	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
903	970	reg = <0x0 0xff190000 0x0 0x1000>;
904	971	clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
905	972	clock-names = "i2c", "pclk";
..	..	@@ -912,7 +979,7 @@
912	979	};
913	980
914	981	i2c2: i2c@ff1a0000 {
915		- compatible = "rockchip,rk3399-i2c";
	982	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
916	983	reg = <0x0 0xff1a0000 0x0 0x1000>;
917	984	clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
918	985	clock-names = "i2c", "pclk";
..	..	@@ -925,7 +992,7 @@
925	992	};
926	993
927	994	i2c3: i2c@ff1b0000 {
928		- compatible = "rockchip,rk3399-i2c";
	995	+ compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
929	996	reg = <0x0 0xff1b0000 0x0 0x1000>;
930	997	clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
931	998	clock-names = "i2c", "pclk";
..	..	@@ -941,15 +1008,14 @@
941	1008	compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
942	1009	reg = <0x0 0xff1d0000 0x0 0x1000>;
943	1010	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
944		- #address-cells = <1>;
945		- #size-cells = <0>;
946	1011	clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
947	1012	clock-names = "spiclk", "apb_pclk";
948	1013	dmas = <&dmac 12>, <&dmac 13>;
949	1014	dma-names = "tx", "rx";
950		- pinctrl-names = "default", "high_speed";
	1015	+ pinctrl-names = "default";
951	1016	pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
952		- pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>;
	1017	+ #address-cells = <1>;
	1018	+ #size-cells = <0>;
953	1019	status = "disabled";
954	1020	};
955	1021
..	..	@@ -957,15 +1023,14 @@
957	1023	compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
958	1024	reg = <0x0 0xff1d8000 0x0 0x1000>;
959	1025	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
960		- #address-cells = <1>;
961		- #size-cells = <0>;
962	1026	clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
963	1027	clock-names = "spiclk", "apb_pclk";
964	1028	dmas = <&dmac 14>, <&dmac 15>;
965	1029	dma-names = "tx", "rx";
966		- pinctrl-names = "default", "high_speed";
	1030	+ pinctrl-names = "default";
967	1031	pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
968		- pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>;
	1032	+ #address-cells = <1>;
	1033	+ #size-cells = <0>;
969	1034	status = "disabled";
970	1035	};
971	1036
..	..	@@ -974,108 +1039,106 @@
974	1039	reg = <0x0 0xff1e0000 0x0 0x100>;
975	1040	clocks = <&cru PCLK_WDT_NS>;
976	1041	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
977		- resets = <&cru SRST_WDT_NS_P>;
978		- reset-names = "reset";
979	1042	status = "disabled";
980	1043	};
981	1044
982	1045	pwm0: pwm@ff200000 {
983	1046	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
984	1047	reg = <0x0 0xff200000 0x0 0x10>;
985		- #pwm-cells = <3>;
986		- pinctrl-names = "active";
987		- pinctrl-0 = <&pwm0_pin>;
988	1048	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
989	1049	clock-names = "pwm", "pclk";
	1050	+ pinctrl-names = "active";
	1051	+ pinctrl-0 = <&pwm0_pin>;
	1052	+ #pwm-cells = <3>;
990	1053	status = "disabled";
991	1054	};
992	1055
993	1056	pwm1: pwm@ff200010 {
994	1057	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
995	1058	reg = <0x0 0xff200010 0x0 0x10>;
996		- #pwm-cells = <3>;
997		- pinctrl-names = "active";
998		- pinctrl-0 = <&pwm1_pin>;
999	1059	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1000	1060	clock-names = "pwm", "pclk";
	1061	+ pinctrl-names = "active";
	1062	+ pinctrl-0 = <&pwm1_pin>;
	1063	+ #pwm-cells = <3>;
1001	1064	status = "disabled";
1002	1065	};
1003	1066
1004	1067	pwm2: pwm@ff200020 {
1005	1068	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1006	1069	reg = <0x0 0xff200020 0x0 0x10>;
1007		- #pwm-cells = <3>;
1008		- pinctrl-names = "active";
1009		- pinctrl-0 = <&pwm2_pin>;
1010	1070	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1011	1071	clock-names = "pwm", "pclk";
	1072	+ pinctrl-names = "active";
	1073	+ pinctrl-0 = <&pwm2_pin>;
	1074	+ #pwm-cells = <3>;
1012	1075	status = "disabled";
1013	1076	};
1014	1077
1015	1078	pwm3: pwm@ff200030 {
1016	1079	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1017	1080	reg = <0x0 0xff200030 0x0 0x10>;
1018		- #pwm-cells = <3>;
1019		- pinctrl-names = "active";
1020		- pinctrl-0 = <&pwm3_pin>;
1021	1081	clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
1022	1082	clock-names = "pwm", "pclk";
	1083	+ pinctrl-names = "active";
	1084	+ pinctrl-0 = <&pwm3_pin>;
	1085	+ #pwm-cells = <3>;
1023	1086	status = "disabled";
1024	1087	};
1025	1088
1026	1089	pwm4: pwm@ff208000 {
1027	1090	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1028	1091	reg = <0x0 0xff208000 0x0 0x10>;
1029		- #pwm-cells = <3>;
1030		- pinctrl-names = "active";
1031		- pinctrl-0 = <&pwm4_pin>;
1032	1092	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1033	1093	clock-names = "pwm", "pclk";
	1094	+ pinctrl-names = "active";
	1095	+ pinctrl-0 = <&pwm4_pin>;
	1096	+ #pwm-cells = <3>;
1034	1097	status = "disabled";
1035	1098	};
1036	1099
1037	1100	pwm5: pwm@ff208010 {
1038	1101	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1039	1102	reg = <0x0 0xff208010 0x0 0x10>;
1040		- #pwm-cells = <3>;
1041		- pinctrl-names = "active";
1042		- pinctrl-0 = <&pwm5_pin>;
1043	1103	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1044	1104	clock-names = "pwm", "pclk";
	1105	+ pinctrl-names = "active";
	1106	+ pinctrl-0 = <&pwm5_pin>;
	1107	+ #pwm-cells = <3>;
1045	1108	status = "disabled";
1046	1109	};
1047	1110
1048	1111	pwm6: pwm@ff208020 {
1049	1112	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1050	1113	reg = <0x0 0xff208020 0x0 0x10>;
1051		- #pwm-cells = <3>;
1052		- pinctrl-names = "active";
1053		- pinctrl-0 = <&pwm6_pin>;
1054	1114	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1055	1115	clock-names = "pwm", "pclk";
	1116	+ pinctrl-names = "active";
	1117	+ pinctrl-0 = <&pwm6_pin>;
	1118	+ #pwm-cells = <3>;
1056	1119	status = "disabled";
1057	1120	};
1058	1121
1059	1122	pwm7: pwm@ff208030 {
1060	1123	compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
1061	1124	reg = <0x0 0xff208030 0x0 0x10>;
1062		- #pwm-cells = <3>;
1063		- pinctrl-names = "active";
1064		- pinctrl-0 = <&pwm7_pin>;
1065	1125	clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
1066	1126	clock-names = "pwm", "pclk";
	1127	+ pinctrl-names = "active";
	1128	+ pinctrl-0 = <&pwm7_pin>;
	1129	+ #pwm-cells = <3>;
1067	1130	status = "disabled";
1068	1131	};
1069	1132
1070		- rktimer: rktimer@ff210000 {
1071		- compatible = "rockchip,rk3288-timer";
	1133	+ rktimer: timer@ff210000 {
	1134	+ compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
1072	1135	reg = <0x0 0xff210000 0x0 0x1000>;
1073	1136	interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1074	1137	clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
1075	1138	clock-names = "pclk", "timer";
1076	1139	};
1077	1140
1078		- amba {
	1141	+ amba: bus {
1079	1142	compatible = "simple-bus";
1080	1143	#address-cells = <2>;
1081	1144	#size-cells = <2>;
..	..	@@ -1086,59 +1149,10 @@
1086	1149	reg = <0x0 0xff240000 0x0 0x4000>;
1087	1150	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
1088	1151	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	1152	+ arm,pl330-periph-burst;
1089	1153	clocks = <&cru ACLK_DMAC>;
1090	1154	clock-names = "apb_pclk";
1091	1155	#dma-cells = <1>;
1092		- arm,pl330-periph-burst;
1093		- };
1094		- };
1095		-
1096		- thermal_zones: thermal-zones {
1097		-
1098		- soc_thermal: soc-thermal {
1099		- polling-delay-passive = <20>;
1100		- polling-delay = <1000>;
1101		- sustainable-power = <750>;
1102		-
1103		- thermal-sensors = <&tsadc 0>;
1104		-
1105		- trips {
1106		- threshold: trip-point-0 {
1107		- temperature = <70000>;
1108		- hysteresis = <2000>;
1109		- type = "passive";
1110		- };
1111		- target: trip-point-1 {
1112		- temperature = <85000>;
1113		- hysteresis = <2000>;
1114		- type = "passive";
1115		- };
1116		- soc_crit: soc-crit {
1117		- temperature = <115000>;
1118		- hysteresis = <2000>;
1119		- type = "critical";
1120		- };
1121		- };
1122		-
1123		- cooling-maps {
1124		- map0 {
1125		- trip = <&target>;
1126		- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1127		- contribution = <4096>;
1128		- };
1129		- map1 {
1130		- trip = <&target>;
1131		- cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1132		- contribution = <4096>;
1133		- };
1134		- };
1135		- };
1136		-
1137		- gpu_thermal: gpu-thermal {
1138		- polling-delay-passive = <100>; /* milliseconds */
1139		- polling-delay = <1000>; /* milliseconds */
1140		-
1141		- thermal-sensors = <&tsadc 1>;
1142	1156	};
1143	1157	};
1144	1158
..	..	@@ -1146,15 +1160,19 @@
1146	1160	compatible = "rockchip,px30-tsadc";
1147	1161	reg = <0x0 0xff280000 0x0 0x100>;
1148	1162	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1149		- rockchip,grf = <&grf>;
1150		- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
1151		- clock-names = "tsadc", "apb_pclk";
1152	1163	assigned-clocks = <&cru SCLK_TSADC>;
1153	1164	assigned-clock-rates = <50000>;
	1165	+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	1166	+ clock-names = "tsadc", "apb_pclk";
1154	1167	resets = <&cru SRST_TSADC>;
1155	1168	reset-names = "tsadc-apb";
1156		- #thermal-sensor-cells = <1>;
	1169	+ rockchip,grf = <&grf>;
1157	1170	rockchip,hw-tshut-temp = <120000>;
	1171	+ pinctrl-names = "init", "default", "sleep";
	1172	+ pinctrl-0 = <&tsadc_otp_pin>;
	1173	+ pinctrl-1 = <&tsadc_otp_out>;
	1174	+ pinctrl-2 = <&tsadc_otp_pin>;
	1175	+ #thermal-sensor-cells = <1>;
1158	1176	status = "disabled";
1159	1177	};
1160	1178
..	..	@@ -1170,19 +1188,19 @@
1170	1188	status = "disabled";
1171	1189	};
1172	1190
1173		- otp: otp@ff290000 {
	1191	+ otp: nvmem@ff290000 {
1174	1192	compatible = "rockchip,px30-otp";
1175	1193	reg = <0x0 0xff290000 0x0 0x4000>;
1176		- #address-cells = <1>;
1177		- #size-cells = <1>;
1178	1194	clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
1179	1195	<&cru PCLK_OTP_PHY>;
1180	1196	clock-names = "otp", "apb_pclk", "phy";
1181	1197	resets = <&cru SRST_OTP_PHY>;
1182		- reset-names = "otp_phy";
	1198	+ reset-names = "phy";
	1199	+ #address-cells = <1>;
	1200	+ #size-cells = <1>;
1183	1201
1184	1202	/* Data cells */
1185		- otp_id: id@7 {
	1203	+ cpu_id: id@7 {
1186	1204	reg = <0x07 0x10>;
1187	1205	};
1188	1206	cpu_leakage: cpu-leakage@17 {
..	..	@@ -1198,27 +1216,14 @@
1198	1216	compatible = "rockchip,px30-cru";
1199	1217	reg = <0x0 0xff2b0000 0x0 0x1000>;
1200	1218	rockchip,grf = <&grf>;
1201		- rockchip,boost = <&cpu_boost>;
1202	1219	#clock-cells = <1>;
1203	1220	#reset-cells = <1>;
	1221	+
	1222	+ assigned-clocks = <&cru PLL_NPLL>;
	1223	+ assigned-clock-rates = <1188000000>;
1204	1224	};
1205	1225
1206		- cpu_boost: cpu-boost@ff2b8000 {
1207		- compatible = "syscon";
1208		- reg = <0x0 0xff2b8000 0x0 0x1000>;
1209		- rockchip,boost-low-con0 = <0x1032>;
1210		- rockchip,boost-low-con1 = <0x1441>;
1211		- rockchip,boost-high-con0 = <0x1036>;
1212		- rockchip,boost-high-con1 = <0x1441>;
1213		- rockchip,boost-backup-pll = <1>;
1214		- rockchip,boost-backup-pll-usage = <0>;
1215		- rockchip,boost-switch-threshold = <0x249f00>;
1216		- rockchip,boost-statis-threshold = <0x100>;
1217		- rockchip,boost-statis-enable = <0>;
1218		- rockchip,boost-enable = <0>;
1219		- };
1220		-
1221		- pmucru: pmu-clock-controller@ff2bc000 {
	1226	+ pmucru: clock-controller@ff2bc000 {
1222	1227	compatible = "rockchip,px30-pmucru";
1223	1228	reg = <0x0 0xff2bc000 0x0 0x1000>;
1224	1229	rockchip,grf = <&grf>;
..	..	@@ -1247,9 +1252,8 @@
1247	1252	#size-cells = <1>;
1248	1253
1249	1254	u2phy: usb2-phy@100 {
1250		- compatible = "rockchip,px30-usb2phy",
1251		- "rockchip,rk3328-usb2phy";
1252		- reg = <0x100 0x10>;
	1255	+ compatible = "rockchip,px30-usb2phy";
	1256	+ reg = <0x100 0x20>;
1253	1257	clocks = <&pmucru SCLK_USBPHY_REF>;
1254	1258	clock-names = "phyclk";
1255	1259	#clock-cells = <0>;
..	..	@@ -1277,18 +1281,18 @@
1277	1281	};
1278	1282	};
1279	1283
1280		- video_phy: video-phy@ff2e0000 {
1281		- compatible = "rockchip,px30-video-phy";
	1284	+ video_phy: dsi_dphy: phy@ff2e0000 {
	1285	+ compatible = "rockchip,px30-dsi-dphy", "rockchip,px30-video-phy";
1282	1286	reg = <0x0 0xff2e0000 0x0 0x10000>,
1283	1287	<0x0 0xff450000 0x0 0x10000>;
	1288	+ reg-names = "phy", "host";
1284	1289	clocks = <&pmucru SCLK_MIPIDSIPHY_REF>,
1285	1290	<&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
1286		- clock-names = "ref", "pclk_phy", "pclk_host";
1287		- #clock-cells = <0>;
	1291	+ clock-names = "ref", "pclk", "pclk_host";
1288	1292	resets = <&cru SRST_MIPIDSIPHY_P>;
1289		- reset-names = "rst";
1290		- power-domains = <&power PX30_PD_VO>;
	1293	+ reset-names = "apb";
1291	1294	#phy-cells = <0>;
	1295	+ power-domains = <&power PX30_PD_VO>;
1292	1296	status = "disabled";
1293	1297	};
1294	1298
..	..	@@ -1309,14 +1313,13 @@
1309	1313	interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1310	1314	clocks = <&cru HCLK_OTG>;
1311	1315	clock-names = "otg";
1312		- power-domains = <&power PX30_PD_USB>;
1313	1316	dr_mode = "otg";
1314	1317	g-np-tx-fifo-size = <16>;
1315	1318	g-rx-fifo-size = <280>;
1316	1319	g-tx-fifo-size = <256 128 128 64 32 16>;
1317		- g-use-dma;
1318	1320	phys = <&u2phy_otg>;
1319	1321	phy-names = "usb2-phy";
	1322	+ power-domains = <&power PX30_PD_USB>;
1320	1323	status = "disabled";
1321	1324	};
1322	1325
..	..	@@ -1326,9 +1329,9 @@
1326	1329	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1327	1330	clocks = <&cru HCLK_HOST>, <&u2phy>;
1328	1331	clock-names = "usbhost", "utmi";
1329		- power-domains = <&power PX30_PD_USB>;
1330	1332	phys = <&u2phy_host>;
1331	1333	phy-names = "usb";
	1334	+ power-domains = <&power PX30_PD_USB>;
1332	1335	status = "disabled";
1333	1336	};
1334	1337
..	..	@@ -1338,16 +1341,15 @@
1338	1341	interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1339	1342	clocks = <&cru HCLK_HOST>, <&u2phy>;
1340	1343	clock-names = "usbhost", "utmi";
1341		- power-domains = <&power PX30_PD_USB>;
1342	1344	phys = <&u2phy_host>;
1343	1345	phy-names = "usb";
	1346	+ power-domains = <&power PX30_PD_USB>;
1344	1347	status = "disabled";
1345	1348	};
1346	1349
1347	1350	gmac: ethernet@ff360000 {
1348	1351	compatible = "rockchip,px30-gmac";
1349	1352	reg = <0x0 0xff360000 0x0 0x10000>;
1350		- rockchip,grf = <&grf>;
1351	1353	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1352	1354	interrupt-names = "macirq";
1353	1355	clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
..	..	@@ -1358,61 +1360,72 @@
1358	1360	"mac_clk_tx", "clk_mac_ref",
1359	1361	"clk_mac_refout", "aclk_mac",
1360	1362	"pclk_mac", "clk_mac_speed";
	1363	+ rockchip,grf = <&grf>;
1361	1364	phy-mode = "rmii";
1362	1365	pinctrl-names = "default";
1363	1366	pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
	1367	+ power-domains = <&power PX30_PD_GMAC>;
1364	1368	resets = <&cru SRST_GMAC_A>;
1365	1369	reset-names = "stmmaceth";
1366		- power-domains = <&power PX30_PD_GMAC>;
1367	1370	status = "disabled";
1368	1371	};
1369	1372
1370	1373	sdmmc: dwmmc@ff370000 {
1371	1374	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1372	1375	reg = <0x0 0xff370000 0x0 0x4000>;
1373		- max-frequency = <150000000>;
	1376	+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1374	1377	clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
1375	1378	<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
1376		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1377		- assigned-clocks = <&cru SCLK_SDMMC>;
1378		- assigned-clock-parents = <&cru SCLK_SDMMC_DIV50>;
1379		- power-domains = <&power PX30_PD_SDCARD>;
	1379	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	1380	+ bus-width = <4>;
1380	1381	fifo-depth = <0x100>;
1381		- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	1382	+ max-frequency = <150000000>;
1382	1383	pinctrl-names = "default";
1383	1384	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
	1385	+ power-domains = <&power PX30_PD_SDCARD>;
1384	1386	status = "disabled";
1385	1387	};
1386	1388
1387	1389	sdio: dwmmc@ff380000 {
1388	1390	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1389	1391	reg = <0x0 0xff380000 0x0 0x4000>;
1390		- max-frequency = <150000000>;
	1392	+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1391	1393	clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1392	1394	<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1393		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1394		- assigned-clocks = <&cru SCLK_SDIO>;
1395		- assigned-clock-parents = <&cru SCLK_SDIO_DIV50>;
1396		- power-domains = <&power PX30_PD_MMC_NAND>;
	1395	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	1396	+ bus-width = <4>;
1397	1397	fifo-depth = <0x100>;
1398		- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	1398	+ max-frequency = <150000000>;
1399	1399	pinctrl-names = "default";
1400	1400	pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
	1401	+ power-domains = <&power PX30_PD_MMC_NAND>;
1401	1402	status = "disabled";
1402	1403	};
1403	1404
1404	1405	emmc: dwmmc@ff390000 {
1405	1406	compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1406	1407	reg = <0x0 0xff390000 0x0 0x4000>;
1407		- max-frequency = <150000000>;
	1408	+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1408	1409	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1409	1410	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1410		- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1411		- assigned-clocks = <&cru SCLK_EMMC>;
1412		- assigned-clock-parents = <&cru SCLK_EMMC_DIV50>;
1413		- power-domains = <&power PX30_PD_MMC_NAND>;
	1411	+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
	1412	+ bus-width = <8>;
1414	1413	fifo-depth = <0x100>;
1415		- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	1414	+ max-frequency = <150000000>;
	1415	+ pinctrl-names = "default";
	1416	+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	1417	+ power-domains = <&power PX30_PD_MMC_NAND>;
	1418	+ status = "disabled";
	1419	+ };
	1420	+
	1421	+ sfc: spi@ff3a0000 {
	1422	+ compatible = "rockchip,sfc";
	1423	+ reg = <0x0 0xff3a0000 0x0 0x4000>;
	1424	+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	1425	+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
	1426	+ clock-names = "clk_sfc", "hclk_sfc";
	1427	+ assigned-clocks = <&cru SCLK_SFC>;
	1428	+ assigned-clock-rates = <100000000>;
1416	1429	status = "disabled";
1417	1430	};
1418	1431
..	..	@@ -1430,23 +1443,18 @@
1430	1443	};
1431	1444
1432	1445	gpu: gpu@ff400000 {
1433		- compatible = "arm,mali-bifrost";
	1446	+ compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1434	1447	reg = <0x0 0xff400000 0x0 0x4000>;
1435		-
1436	1448	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1437	1449	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1438	1450	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1439	1451	interrupt-names = "GPU", "MMU", "JOB";
1440		-
	1452	+ clocks = <&cru SCLK_GPU>;
	1453	+ #cooling-cells = <2>;
	1454	+ power-domains = <&power PX30_PD_GPU>;
	1455	+ operating-points-v2 = <&gpu_opp_table>;
1441	1456	upthreshold = <40>;
1442	1457	downdifferential = <10>;
1443		-
1444		- clocks = <&cru SCLK_GPU>;
1445		- clock-names = "clk_mali";
1446		- power-domains = <&power PX30_PD_GPU>;
1447		- #cooling-cells = <2>;
1448		- operating-points-v2 = <&gpu_opp_table>;
1449		-
1450	1458	status = "disabled";
1451	1459	power_model {
1452	1460	compatible = "arm,mali-simple-power-model";
..	..	@@ -1455,7 +1463,6 @@
1455	1463	ts = <32000 4700 (-80) 2>;
1456	1464	thermal-zone = "gpu-thermal";
1457	1465	};
1458		-
1459	1466	};
1460	1467
1461	1468	gpu_opp_table: gpu-opp-table {
..	..	@@ -1586,6 +1593,7 @@
1586	1593	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1587	1594	clock-names = "aclk", "iface";
1588	1595	power-domains = <&power PX30_PD_VPU>;
	1596	+ rockchip,shootdown-entire;
1589	1597	#iommu-cells = <0>;
1590	1598	status = "disabled";
1591	1599	};
..	..	@@ -1615,10 +1623,11 @@
1615	1623	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>;
1616	1624	clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
1617	1625	resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>,
1618		- <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>,
1619		- <&cru SRST_VPU_CORE>;
	1626	+ <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>,
	1627	+ <&cru SRST_VPU_CORE>;
1620	1628	reset-names = "shared_video_a", "shared_video_h",
1621		- "niu_a", "niu_h", "video_core";
	1629	+ "niu_a", "niu_h",
	1630	+ "video_core";
1622	1631	iommus = <&hevc_mmu>;
1623	1632	rockchip,srv = <&mpp_srv>;
1624	1633	rockchip,taskqueue-node = <0>;
..	..	@@ -1635,6 +1644,7 @@
1635	1644	clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1636	1645	clock-names = "aclk", "iface";
1637	1646	power-domains = <&power PX30_PD_VPU>;
	1647	+ rockchip,shootdown-entire;
1638	1648	#iommu-cells = <0>;
1639	1649	status = "disabled";
1640	1650	};
..	..	@@ -1643,13 +1653,13 @@
1643	1653	compatible = "rockchip,px30-mipi-dsi";
1644	1654	reg = <0x0 0xff450000 0x0 0x10000>;
1645	1655	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1646		- clocks = <&cru PCLK_MIPI_DSI>, <&video_phy>;
1647		- clock-names = "pclk", "hs_clk";
	1656	+ clocks = <&cru PCLK_MIPI_DSI>;
	1657	+ clock-names = "pclk";
	1658	+ phys = <&video_phy>;
	1659	+ phy-names = "dphy";
	1660	+ power-domains = <&power PX30_PD_VO>;
1648	1661	resets = <&cru SRST_MIPIDSI_HOST_P>;
1649	1662	reset-names = "apb";
1650		- phys = <&video_phy>;
1651		- phy-names = "mipi_dphy";
1652		- power-domains = <&power PX30_PD_VO>;
1653	1663	rockchip,grf = <&grf>;
1654	1664	#address-cells = <1>;
1655	1665	#size-cells = <0>;
..	..	@@ -1686,22 +1696,24 @@
1686	1696	clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1687	1697	<&cru HCLK_VOPB>;
1688	1698	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1689		- power-domains = <&power PX30_PD_VO>;
	1699	+ resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
	1700	+ reset-names = "axi", "ahb", "dclk";
1690	1701	iommus = <&vopb_mmu>;
	1702	+ power-domains = <&power PX30_PD_VO>;
1691	1703	status = "disabled";
1692	1704
1693	1705	vopb_out: port {
1694	1706	#address-cells = <1>;
1695	1707	#size-cells = <0>;
1696	1708
1697		- vopb_out_lvds: endpoint@0 {
	1709	+ vopb_out_dsi: endpoint@0 {
1698	1710	reg = <0>;
1699		- remote-endpoint = <&lvds_in_vopb>;
	1711	+ remote-endpoint = <&dsi_in_vopb>;
1700	1712	};
1701	1713
1702		- vopb_out_dsi: endpoint@1 {
	1714	+ vopb_out_lvds: endpoint@1 {
1703	1715	reg = <1>;
1704		- remote-endpoint = <&dsi_in_vopb>;
	1716	+ remote-endpoint = <&lvds_vopb_in>;
1705	1717	};
1706	1718
1707	1719	vopb_out_rgb: endpoint@2 {
..	..	@@ -1733,22 +1745,24 @@
1733	1745	clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1734	1746	<&cru HCLK_VOPL>;
1735	1747	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1736		- power-domains = <&power PX30_PD_VO>;
	1748	+ resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
	1749	+ reset-names = "axi", "ahb", "dclk";
1737	1750	iommus = <&vopl_mmu>;
	1751	+ power-domains = <&power PX30_PD_VO>;
1738	1752	status = "disabled";
1739	1753
1740	1754	vopl_out: port {
1741	1755	#address-cells = <1>;
1742	1756	#size-cells = <0>;
1743	1757
1744		- vopl_out_lvds: endpoint@0 {
	1758	+ vopl_out_dsi: endpoint@0 {
1745	1759	reg = <0>;
1746		- remote-endpoint = <&lvds_in_vopl>;
	1760	+ remote-endpoint = <&dsi_in_vopl>;
1747	1761	};
1748	1762
1749		- vopl_out_dsi: endpoint@1 {
	1763	+ vopl_out_lvds: endpoint@1 {
1750	1764	reg = <1>;
1751		- remote-endpoint = <&dsi_in_vopl>;
	1765	+ remote-endpoint = <&lvds_vopl_in>;
1752	1766	};
1753	1767
1754	1768	vopl_out_rgb: endpoint@2 {
..	..	@@ -1828,9 +1842,9 @@
1828	1842	reg = <0x0 0xff4a0000 0x0 0x8000>;
1829	1843	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1830	1844	clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>,
1831		- <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
	1845	+ <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>;
1832	1846	clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe",
1833		- "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
	1847	+ "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
1834	1848	resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>;
1835	1849	reset-names = "rst_isp", "rst_mipicsiphy";
1836	1850	power-domains = <&power PX30_PD_VI>;
..	..	@@ -1856,9 +1870,9 @@
1856	1870	<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1857	1871	interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
1858	1872	clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1859		- <&cru SCLK_ISP>, <&cru PCLK_ISP>;
	1873	+ <&cru SCLK_ISP>, <&cru PCLK_ISP>;
1860	1874	clock-names = "aclk_isp", "hclk_isp",
1861		- "clk_isp", "pclk_isp";
	1875	+ "clk_isp", "pclk_isp";
1862	1876	devfreq = <&dmc>;
1863	1877	power-domains = <&power PX30_PD_VI>;
1864	1878	iommus = <&isp_mmu>;
..	..	@@ -1999,11 +2013,11 @@
1999	2013	downdifferential = <20>;
2000	2014	system-status-freq = <
2001	2015	/system status freq(KHz)/
2002		- SYS_STATUS_NORMAL 528000
	2016	+ SYS_STATUS_NORMAL 666000
2003	2017	SYS_STATUS_REBOOT 450000
2004	2018	SYS_STATUS_SUSPEND 194000
2005	2019	SYS_STATUS_VIDEO_1080P 450000
2006		- SYS_STATUS_BOOST 528000
	2020	+ SYS_STATUS_BOOST 666000
2007	2021	SYS_STATUS_ISP 666000
2008	2022	SYS_STATUS_PERFORMANCE 1056000
2009	2023	>;
..	..	@@ -2073,14 +2087,6 @@
2073	2087	opp-microvolt-L2 = <950000>;
2074	2088	opp-microvolt-L3 = <950000>;
2075	2089	};
2076		- opp-528000000 {
2077		- opp-hz = /bits/ 64 <528000000>;
2078		- opp-microvolt = <975000>;
2079		- opp-microvolt-L0 = <975000>;
2080		- opp-microvolt-L1 = <975000>;
2081		- opp-microvolt-L2 = <950000>;
2082		- opp-microvolt-L3 = <950000>;
2083		- };
2084	2090	opp-666000000 {
2085	2091	opp-hz = /bits/ 64 <666000000>;
2086	2092	opp-microvolt = <1050000>;
..	..	@@ -2110,11 +2116,6 @@
2110	2116	opp-328000000 {
2111	2117	opp-hz = /bits/ 64 <328000000>;
2112	2118	opp-microvolt = <950000>;
2113		- };
2114		- opp-528000000 {
2115		- opp-hz = /bits/ 64 <528000000>;
2116		- opp-microvolt = <950000>;
2117		- status = "disabled";
2118	2119	};
2119	2120	opp-666000000 {
2120	2121	opp-hz = /bits/ 64 <666000000>;
..	..	@@ -2318,7 +2319,7 @@
2318	2319	};
2319	2320
2320	2321	tsadc {
2321		- tsadc_otp_gpio: tsadc-otp-gpio {
	2322	+ tsadc_otp_gpio: tsadc_otp_pin: tsadc-otp-pin {
2322	2323	rockchip,pins =
2323	2324	<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2324	2325	};
..	..	@@ -2344,11 +2345,6 @@
2344	2345	uart0_rts: uart0-rts {
2345	2346	rockchip,pins =
2346	2347	<0 RK_PB5 1 &pcfg_pull_none>;
2347		- };
2348		-
2349		- uart0_rts_gpio: uart0-rts-gpio {
2350		- rockchip,pins =
2351		- <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
2352	2348	};
2353	2349	};
2354	2350
..	..	@@ -2407,11 +2403,6 @@
2407	2403	rockchip,pins =
2408	2404	<0 RK_PC3 2 &pcfg_pull_none>;
2409	2405	};
2410		-
2411		- uart3m0_rts_gpio: uart3m0-rts-gpio {
2412		- rockchip,pins =
2413		- <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
2414		- };
2415	2406	};
2416	2407
2417	2408	uart3-m1 {
..	..	@@ -2430,15 +2421,9 @@
2430	2421	rockchip,pins =
2431	2422	<1 RK_PB5 2 &pcfg_pull_none>;
2432	2423	};
2433		-
2434		- uart3m1_rts_gpio: uart3m1-rts-gpio {
2435		- rockchip,pins =
2436		- <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
2437		- };
2438	2424	};
2439	2425
2440	2426	uart4 {
2441		-
2442	2427	uart4_xfer: uart4-xfer {
2443	2428	rockchip,pins =
2444	2429	<1 RK_PD4 2 &pcfg_pull_up>,
..	..	@@ -2448,7 +2433,6 @@
2448	2433	uart4_cts: uart4-cts {
2449	2434	rockchip,pins =
2450	2435	<1 RK_PD6 2 &pcfg_pull_none>;
2451		-
2452	2436	};
2453	2437
2454	2438	uart4_rts: uart4-rts {
..	..	@@ -2458,7 +2442,6 @@
2458	2442	};
2459	2443
2460	2444	uart5 {
2461		-
2462	2445	uart5_xfer: uart5-xfer {
2463	2446	rockchip,pins =
2464	2447	<3 RK_PA2 4 &pcfg_pull_up>,
..	..	@@ -2468,7 +2451,6 @@
2468	2451	uart5_cts: uart5-cts {
2469	2452	rockchip,pins =
2470	2453	<3 RK_PA3 4 &pcfg_pull_none>;
2471		-
2472	2454	};
2473	2455
2474	2456	uart5_rts: uart5-rts {
..	..	@@ -2641,27 +2623,27 @@
2641	2623	i2s0 {
2642	2624	i2s0_8ch_mclk: i2s0-8ch-mclk {
2643	2625	rockchip,pins =
2644		- <3 RK_PC1 2 &pcfg_pull_none>;
	2626	+ <3 RK_PC1 2 &pcfg_pull_none_smt>;
2645	2627	};
2646	2628
2647	2629	i2s0_8ch_sclktx: i2s0-8ch-sclktx {
2648	2630	rockchip,pins =
2649		- <3 RK_PC3 2 &pcfg_pull_none>;
	2631	+ <3 RK_PC3 2 &pcfg_pull_none_smt>;
2650	2632	};
2651	2633
2652	2634	i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
2653	2635	rockchip,pins =
2654		- <3 RK_PB4 2 &pcfg_pull_none>;
	2636	+ <3 RK_PB4 2 &pcfg_pull_none_smt>;
2655	2637	};
2656	2638
2657	2639	i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
2658	2640	rockchip,pins =
2659		- <3 RK_PC2 2 &pcfg_pull_none>;
	2641	+ <3 RK_PC2 2 &pcfg_pull_none_smt>;
2660	2642	};
2661	2643
2662	2644	i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
2663	2645	rockchip,pins =
2664		- <3 RK_PB5 2 &pcfg_pull_none>;
	2646	+ <3 RK_PB5 2 &pcfg_pull_none_smt>;
2665	2647	};
2666	2648
2667	2649	i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
..	..	@@ -2708,17 +2690,17 @@
2708	2690	i2s1 {
2709	2691	i2s1_2ch_mclk: i2s1-2ch-mclk {
2710	2692	rockchip,pins =
2711		- <2 RK_PC3 1 &pcfg_pull_none>;
	2693	+ <2 RK_PC3 1 &pcfg_pull_none_smt>;
2712	2694	};
2713	2695
2714	2696	i2s1_2ch_sclk: i2s1-2ch-sclk {
2715	2697	rockchip,pins =
2716		- <2 RK_PC2 1 &pcfg_pull_none>;
	2698	+ <2 RK_PC2 1 &pcfg_pull_none_smt>;
2717	2699	};
2718	2700
2719	2701	i2s1_2ch_lrck: i2s1-2ch-lrck {
2720	2702	rockchip,pins =
2721		- <2 RK_PC1 1 &pcfg_pull_none>;
	2703	+ <2 RK_PC1 1 &pcfg_pull_none_smt>;
2722	2704	};
2723	2705
2724	2706	i2s1_2ch_sdi: i2s1-2ch-sdi {
..	..	@@ -2735,17 +2717,17 @@
2735	2717	i2s2 {
2736	2718	i2s2_2ch_mclk: i2s2-2ch-mclk {
2737	2719	rockchip,pins =
2738		- <3 RK_PA1 2 &pcfg_pull_none>;
	2720	+ <3 RK_PA1 2 &pcfg_pull_none_smt>;
2739	2721	};
2740	2722
2741	2723	i2s2_2ch_sclk: i2s2-2ch-sclk {
2742	2724	rockchip,pins =
2743		- <3 RK_PA2 2 &pcfg_pull_none>;
	2725	+ <3 RK_PA2 2 &pcfg_pull_none_smt>;
2744	2726	};
2745	2727
2746	2728	i2s2_2ch_lrck: i2s2-2ch-lrck {
2747	2729	rockchip,pins =
2748		- <3 RK_PA3 2 &pcfg_pull_none>;
	2730	+ <3 RK_PA3 2 &pcfg_pull_none_smt>;
2749	2731	};
2750	2732
2751	2733	i2s2_2ch_sdi: i2s2-2ch-sdi {
..	..	@@ -2787,16 +2769,6 @@
2787	2769	<1 RK_PD4 1 &pcfg_pull_up_8ma>,
2788	2770	<1 RK_PD5 1 &pcfg_pull_up_8ma>;
2789	2771	};
2790		-
2791		- sdmmc_gpio: sdmmc-gpio {
2792		- rockchip,pins =
2793		- <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2794		- <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2795		- <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2796		- <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2797		- <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
2798		- <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
2799		- };
2800	2772	};
2801	2773
2802	2774	sdio {
..	..	@@ -2817,16 +2789,6 @@
2817	2789	<1 RK_PD0 1 &pcfg_pull_up>,
2818	2790	<1 RK_PD1 1 &pcfg_pull_up>;
2819	2791	};
2820		-
2821		- sdio_gpio: sdio-gpio {
2822		- rockchip,pins =
2823		- <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
2824		- <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
2825		- <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
2826		- <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
2827		- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
2828		- <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
2829		- };
2830	2792	};
2831	2793
2832	2794	emmc {
..	..	@@ -2838,11 +2800,6 @@
2838	2800	emmc_cmd: emmc-cmd {
2839	2801	rockchip,pins =
2840	2802	<1 RK_PB2 2 &pcfg_pull_up_8ma>;
2841		- };
2842		-
2843		- emmc_pwren: emmc-pwren {
2844		- rockchip,pins =
2845		- <1 RK_PB0 2 &pcfg_pull_none>;
2846	2803	};
2847	2804
2848	2805	emmc_rstnout: emmc-rstnout {
..	..	@@ -3055,24 +3012,15 @@
3055	3012	gmac {
3056	3013	rmii_pins: rmii-pins {
3057	3014	rockchip,pins =
3058		- /* mac_txen */
3059		- <2 RK_PA0 2 &pcfg_pull_none_12ma>,
3060		- /* mac_txd1 */
3061		- <2 RK_PA1 2 &pcfg_pull_none_12ma>,
3062		- /* mac_txd0 */
3063		- <2 RK_PA2 2 &pcfg_pull_none_12ma>,
3064		- /* mac_rxd0 */
3065		- <2 RK_PA3 2 &pcfg_pull_none>,
3066		- /* mac_rxd1 */
3067		- <2 RK_PA4 2 &pcfg_pull_none>,
3068		- /* mac_rxer */
3069		- <2 RK_PA5 2 &pcfg_pull_none>,
3070		- /* mac_rxdv */
3071		- <2 RK_PA6 2 &pcfg_pull_none>,
3072		- /* mac_mdio */
3073		- <2 RK_PA7 2 &pcfg_pull_none>,
3074		- /* mac_mdc */
3075		- <2 RK_PB1 2 &pcfg_pull_none>;
	3015	+ <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
	3016	+ <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
	3017	+ <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
	3018	+ <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
	3019	+ <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
	3020	+ <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
	3021	+ <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
	3022	+ <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
	3023	+ <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
3076	3024	};
3077	3025
3078	3026	mac_refclk_12ma: mac-refclk-12ma {
..	..	@@ -3088,75 +3036,78 @@
3088	3036
3089	3037	cif-m0 {
3090	3038	cif_clkout_m0: cif-clkout-m0 {
3091		- rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */
	3039	+ rockchip,pins =
	3040	+ <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */
3092	3041	};
3093	3042
3094	3043	dvp_d2d9_m0: dvp-d2d9-m0 {
3095	3044	rockchip,pins =
3096		- <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */
3097		- <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */
3098		- <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */
3099		- <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */
3100		- <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */
3101		- <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */
3102		- <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */
3103		- <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */
3104		- <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */
3105		- <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */
3106		- <2 RK_PB2 1 &pcfg_pull_none>,/* cif_clkin */
3107		- <2 RK_PB3 1 &pcfg_pull_none>;/* cif_clkout */
	3045	+ <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
	3046	+ <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
	3047	+ <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
	3048	+ <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
	3049	+ <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
	3050	+ <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
	3051	+ <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
	3052	+ <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
	3053	+ <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
	3054	+ <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
	3055	+ <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
	3056	+ <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
3108	3057	};
3109	3058
3110	3059	dvp_d0d1_m0: dvp-d0d1-m0 {
3111	3060	rockchip,pins =
3112		- <2 RK_PB4 1 &pcfg_pull_none>,/* cif_data0 */
3113		- <2 RK_PB6 1 &pcfg_pull_none>;/* cif_data1 */
	3061	+ <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
	3062	+ <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
3114	3063	};
3115	3064
3116	3065	dvp_d10d11_m0:d10-d11-m0 {
3117	3066	rockchip,pins =
3118		- <2 RK_PB7 1 &pcfg_pull_none>,/* cif_data10 */
3119		- <2 RK_PC0 1 &pcfg_pull_none>;/* cif_data11 */
	3067	+ <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
	3068	+ <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
3120	3069	};
3121	3070	};
3122	3071
3123	3072	cif-m1 {
3124	3073	cif_clkout_m1: cif-clkout-m1 {
3125		- rockchip,pins = <3 RK_PD0 3 &pcfg_pull_none>;/* cif_clkout */
	3074	+ rockchip,pins =
	3075	+ <3 RK_PD0 3 &pcfg_pull_none>;
3126	3076	};
3127	3077
3128	3078	dvp_d2d9_m1: dvp-d2d9-m1 {
3129	3079	rockchip,pins =
3130		- <3 RK_PA3 3 &pcfg_pull_none>,/* cif_data2 */
3131		- <3 RK_PA5 3 &pcfg_pull_none>,/* cif_data3 */
3132		- <3 RK_PA7 3 &pcfg_pull_none>,/* cif_data4 */
3133		- <3 RK_PB0 3 &pcfg_pull_none>,/* cif_data5 */
3134		- <3 RK_PB1 3 &pcfg_pull_none>,/* cif_data6 */
3135		- <3 RK_PB4 3 &pcfg_pull_none>,/* cif_data7 */
3136		- <3 RK_PB6 3 &pcfg_pull_none>,/* cif_data8 */
3137		- <3 RK_PB7 3 &pcfg_pull_none>,/* cif_data9 */
3138		- <3 RK_PD1 3 &pcfg_pull_none>,/* cif_sync */
3139		- <3 RK_PD2 3 &pcfg_pull_none>,/* cif_href */
3140		- <3 RK_PD3 3 &pcfg_pull_none>,/* cif_clkin */
3141		- <3 RK_PD0 3 &pcfg_pull_none>;/* cif_clkout */
	3080	+ <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
	3081	+ <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
	3082	+ <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
	3083	+ <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
	3084	+ <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
	3085	+ <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
	3086	+ <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
	3087	+ <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
	3088	+ <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
	3089	+ <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
	3090	+ <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
	3091	+ <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
3142	3092	};
3143	3093
3144	3094	dvp_d0d1_m1: dvp-d0d1-m1 {
3145	3095	rockchip,pins =
3146		- <3 RK_PA1 3 &pcfg_pull_none>,/* cif_data0 */
3147		- <3 RK_PA2 3 &pcfg_pull_none>;/* cif_data1 */
	3096	+ <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
	3097	+ <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
3148	3098	};
3149	3099
3150	3100	dvp_d10d11_m1:d10-d11-m1 {
3151	3101	rockchip,pins =
3152		- <3 RK_PC6 3 &pcfg_pull_none>,/* cif_data10 */
3153		- <3 RK_PC7 3 &pcfg_pull_none>;/* cif_data11 */
	3102	+ <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
	3103	+ <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
3154	3104	};
3155	3105	};
3156	3106
3157	3107	isp {
3158	3108	isp_prelight: isp-prelight {
3159		- rockchip,pins = <3 RK_PD1 4 &pcfg_pull_none>;/* ISP_PRELIGHTTRIG */
	3109	+ rockchip,pins =
	3110	+ <3 RK_PD1 4 &pcfg_pull_none>;
3160	3111	};
3161	3112	};
3162	3113	};