| .. | .. |
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| 7 | 7 | * Copyright (C) 2014 Ulrich Hecht |
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| 8 | 8 | */ |
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| 9 | 9 | |
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| 10 | | -#include <linux/clk-provider.h> |
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| 11 | 10 | #include <linux/clocksource.h> |
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| 12 | 11 | #include <linux/device.h> |
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| 13 | | -#include <linux/dma-contiguous.h> |
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| 12 | +#include <linux/dma-map-ops.h> |
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| 14 | 13 | #include <linux/io.h> |
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| 15 | 14 | #include <linux/kernel.h> |
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| 16 | 15 | #include <linux/memblock.h> |
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| 17 | 16 | #include <linux/of.h> |
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| 17 | +#include <linux/of_clk.h> |
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| 18 | 18 | #include <linux/of_fdt.h> |
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| 19 | 19 | #include <linux/of_platform.h> |
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| 20 | +#include <linux/psci.h> |
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| 20 | 21 | #include <asm/mach/arch.h> |
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| 21 | 22 | #include <asm/secure_cntvoff.h> |
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| 22 | 23 | #include "common.h" |
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| 23 | 24 | #include "rcar-gen2.h" |
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| 24 | 25 | |
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| 25 | 26 | static const struct of_device_id cpg_matches[] __initconst = { |
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| 26 | | - { .compatible = "renesas,rcar-gen2-cpg-clocks", }, |
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| 27 | + { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" }, |
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| 27 | 28 | { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" }, |
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| 29 | + { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" }, |
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| 28 | 30 | { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" }, |
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| 29 | 31 | { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" }, |
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| 30 | 32 | { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" }, |
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| .. | .. |
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| 57 | 59 | #define CNTCR 0 |
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| 58 | 60 | #define CNTFID0 0x20 |
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| 59 | 61 | |
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| 60 | | -void __init rcar_gen2_timer_init(void) |
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| 62 | +static void __init rcar_gen2_timer_init(void) |
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| 61 | 63 | { |
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| 64 | + bool need_update = true; |
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| 62 | 65 | void __iomem *base; |
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| 63 | 66 | u32 freq; |
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| 67 | + |
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| 68 | + /* |
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| 69 | + * If PSCI is available then most likely we are running on PSCI-enabled |
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| 70 | + * U-Boot which, we assume, has already taken care of resetting CNTVOFF |
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| 71 | + * and updating counter module before switching to non-secure mode |
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| 72 | + * and we don't need to. |
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| 73 | + */ |
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| 74 | +#ifdef CONFIG_ARM_PSCI_FW |
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| 75 | + if (psci_ops.cpu_on) |
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| 76 | + need_update = false; |
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| 77 | +#endif |
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| 78 | + |
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| 79 | + if (need_update == false) |
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| 80 | + goto skip_update; |
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| 64 | 81 | |
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| 65 | 82 | secure_cntvoff_init(); |
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| 66 | 83 | |
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| .. | .. |
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| 101 | 118 | |
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| 102 | 119 | iounmap(base); |
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| 103 | 120 | |
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| 121 | +skip_update: |
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| 104 | 122 | of_clk_init(NULL); |
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| 105 | 123 | timer_probe(); |
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| 106 | 124 | } |
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| .. | .. |
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| 156 | 174 | return 0; |
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| 157 | 175 | } |
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| 158 | 176 | |
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| 159 | | -void __init rcar_gen2_reserve(void) |
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| 177 | +static void __init rcar_gen2_reserve(void) |
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| 160 | 178 | { |
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| 161 | 179 | struct memory_reserve_config mrc; |
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| 162 | 180 | |
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| .. | .. |
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| 192 | 210 | MACHINE_END |
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| 193 | 211 | |
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| 194 | 212 | static const char * const rz_g1_boards_compat_dt[] __initconst = { |
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| 213 | + "renesas,r8a7742", |
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| 195 | 214 | "renesas,r8a7743", |
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| 215 | + "renesas,r8a7744", |
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| 196 | 216 | "renesas,r8a7745", |
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| 197 | 217 | "renesas,r8a77470", |
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| 198 | 218 | NULL, |
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