enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arm/mach-imx/anatop.c
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@@ -1,13 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
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  * Copyright 2017-2018 NXP.
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- *
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- * The code contained herein is licensed under the GNU General Public
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- * License. You may obtain a copy of the GNU General Public License
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- * Version 2 or later at the following locations:
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- *
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- * http://www.opensource.org/licenses/gpl-license.html
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- * http://www.gnu.org/copyleft/gpl.html
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  */
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6
 
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 #include <linux/err.h>
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@@ -25,11 +19,11 @@
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 #define ANADIG_REG_2P5		0x130
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 #define ANADIG_REG_CORE		0x140
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 #define ANADIG_ANA_MISC0	0x150
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-#define ANADIG_USB1_CHRG_DETECT	0x1b0
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-#define ANADIG_USB2_CHRG_DETECT	0x210
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 #define ANADIG_DIGPROG		0x260
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 #define ANADIG_DIGPROG_IMX6SL	0x280
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 #define ANADIG_DIGPROG_IMX7D	0x800
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+
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+#define SRC_SBMR2		0x1c
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27
 
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 #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG	0x40000
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 #define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN	0x8
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@@ -37,8 +31,6 @@
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 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG	0x1000
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 /* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
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 #define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS	0x2000
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-#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B	0x80000
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-#define BM_ANADIG_USB_CHRG_DETECT_EN_B		0x100000
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 static struct regmap *anatop;
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36
 
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@@ -97,22 +89,11 @@
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 	if (cpu_is_imx6sl())
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 		imx_anatop_disconnect_high_snvs(false);
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-
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-}
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-
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-static void imx_anatop_usb_chrg_detect_disable(void)
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-{
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-	regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
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-		BM_ANADIG_USB_CHRG_DETECT_EN_B
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-		| BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
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-	regmap_write(anatop, ANADIG_USB2_CHRG_DETECT,
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-		BM_ANADIG_USB_CHRG_DETECT_EN_B |
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-		BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
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 }
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 void __init imx_init_revision_from_anatop(void)
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 {
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-	struct device_node *np;
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+	struct device_node *np, *src_np;
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 	void __iomem *anatop_base;
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 	unsigned int revision;
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 	u32 digprog;
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@@ -148,7 +129,27 @@
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 		major_part = (digprog >> 8) & 0xf;
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 		minor_part = digprog & 0xf;
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 		revision = ((major_part + 1) << 4) | minor_part;
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+
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+		if ((digprog >> 16) == MXC_CPU_IMX6ULL) {
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+			void __iomem *src_base;
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+			u32 sbmr2;
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+
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+			src_np = of_find_compatible_node(NULL, NULL,
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+						     "fsl,imx6ul-src");
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+			src_base = of_iomap(src_np, 0);
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+			of_node_put(src_np);
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+			WARN_ON(!src_base);
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+			sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
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+			iounmap(src_base);
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+
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+			/* src_sbmr2 bit 6 is to identify if it is i.MX6ULZ */
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+			if (sbmr2 & (1 << 6)) {
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+				digprog &= ~(0xff << 16);
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+				digprog |= (MXC_CPU_IMX6ULZ << 16);
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+			}
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+		}
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 	}
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+	of_node_put(np);
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 	mxc_set_cpu_type(digprog >> 16 & 0xff);
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 	imx_set_soc_revision(revision);
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@@ -157,10 +158,6 @@
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 void __init imx_anatop_init(void)
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 {
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 	anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
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-	if (IS_ERR(anatop)) {
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+	if (IS_ERR(anatop))
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 		pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
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-		return;
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-	}
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-
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-	imx_anatop_usb_chrg_detect_disable();
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 }