forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/arch/arm/mach-davinci/dm355.c
....@@ -15,6 +15,8 @@
1515 #include <linux/dma-mapping.h>
1616 #include <linux/dmaengine.h>
1717 #include <linux/init.h>
18
+#include <linux/io.h>
19
+#include <linux/irqchip/irq-davinci-aintc.h>
1820 #include <linux/platform_data/edma.h>
1921 #include <linux/platform_data/gpio-davinci.h>
2022 #include <linux/platform_data/spi-davinci.h>
....@@ -26,13 +28,14 @@
2628 
2729 #include <mach/common.h>
2830 #include <mach/cputype.h>
29
-#include <mach/irqs.h>
3031 #include <mach/mux.h>
3132 #include <mach/serial.h>
32
-#include <mach/time.h>
33
+
34
+#include <clocksource/timer-davinci.h>
3335 
3436 #include "asp.h"
3537 #include "davinci.h"
38
+#include "irqs.h"
3639 #include "mux.h"
3740 
3841 #define DM355_UART2_BASE	(IO_PHYS + 0x206000)
....@@ -53,7 +56,7 @@
5356 		.flags = IORESOURCE_MEM,
5457 	},
5558 	{
56
-		.start = IRQ_DM355_SPINT0_0,
59
+		.start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
5760 		.flags = IORESOURCE_IRQ,
5861 	},
5962 };
....@@ -273,12 +276,12 @@
273276 	},
274277 	{
275278 		.name	= "edma3_ccint",
276
-		.start	= IRQ_CCINT0,
279
+		.start	= DAVINCI_INTC_IRQ(IRQ_CCINT0),
277280 		.flags	= IORESOURCE_IRQ,
278281 	},
279282 	{
280283 		.name	= "edma3_ccerrint",
281
-		.start	= IRQ_CCERRINT,
284
+		.start	= DAVINCI_INTC_IRQ(IRQ_CCERRINT),
282285 		.flags	= IORESOURCE_IRQ,
283286 	},
284287 	/* not using (or muxing) TC*_ERR */
....@@ -358,13 +361,13 @@
358361 
359362 static struct resource vpfe_resources[] = {
360363 	{
361
-		.start          = IRQ_VDINT0,
362
-		.end            = IRQ_VDINT0,
364
+		.start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
365
+		.end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
363366 		.flags          = IORESOURCE_IRQ,
364367 	},
365368 	{
366
-		.start          = IRQ_VDINT1,
367
-		.end            = IRQ_VDINT1,
369
+		.start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
370
+		.end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
368371 		.flags          = IORESOURCE_IRQ,
369372 	},
370373 };
....@@ -422,8 +425,8 @@
422425 
423426 static struct resource dm355_venc_resources[] = {
424427 	{
425
-		.start	= IRQ_VENCINT,
426
-		.end	= IRQ_VENCINT,
428
+		.start	= DAVINCI_INTC_IRQ(IRQ_VENCINT),
429
+		.end	= DAVINCI_INTC_IRQ(IRQ_VENCINT),
427430 		.flags	= IORESOURCE_IRQ,
428431 	},
429432 	/* venc registers io space */
....@@ -442,8 +445,8 @@
442445 
443446 static struct resource dm355_v4l2_disp_resources[] = {
444447 	{
445
-		.start	= IRQ_VENCINT,
446
-		.end	= IRQ_VENCINT,
448
+		.start	= DAVINCI_INTC_IRQ(IRQ_VENCINT),
449
+		.end	= DAVINCI_INTC_IRQ(IRQ_VENCINT),
447450 		.flags	= IORESOURCE_IRQ,
448451 	},
449452 	/* venc registers io space */
....@@ -547,43 +550,45 @@
547550 		.flags	= IORESOURCE_MEM,
548551 	},
549552 	{	/* interrupt */
550
-		.start	= IRQ_DM355_GPIOBNK0,
551
-		.end	= IRQ_DM355_GPIOBNK0,
553
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
554
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
552555 		.flags	= IORESOURCE_IRQ,
553556 	},
554557 	{
555
-		.start	= IRQ_DM355_GPIOBNK1,
556
-		.end	= IRQ_DM355_GPIOBNK1,
558
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
559
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
557560 		.flags	= IORESOURCE_IRQ,
558561 	},
559562 	{
560
-		.start	= IRQ_DM355_GPIOBNK2,
561
-		.end	= IRQ_DM355_GPIOBNK2,
563
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
564
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
562565 		.flags	= IORESOURCE_IRQ,
563566 	},
564567 	{
565
-		.start	= IRQ_DM355_GPIOBNK3,
566
-		.end	= IRQ_DM355_GPIOBNK3,
568
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
569
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
567570 		.flags	= IORESOURCE_IRQ,
568571 	},
569572 	{
570
-		.start	= IRQ_DM355_GPIOBNK4,
571
-		.end	= IRQ_DM355_GPIOBNK4,
573
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
574
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
572575 		.flags	= IORESOURCE_IRQ,
573576 	},
574577 	{
575
-		.start	= IRQ_DM355_GPIOBNK5,
576
-		.end	= IRQ_DM355_GPIOBNK5,
578
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
579
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
577580 		.flags	= IORESOURCE_IRQ,
578581 	},
579582 	{
580
-		.start	= IRQ_DM355_GPIOBNK6,
581
-		.end	= IRQ_DM355_GPIOBNK6,
583
+		.start	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
584
+		.end	= DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
582585 		.flags	= IORESOURCE_IRQ,
583586 	},
584587 };
585588 
586589 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
590
+	.no_auto_base	= true,
591
+	.base		= 0,
587592 	.ngpio		= 104,
588593 };
589594 
....@@ -616,21 +621,21 @@
616621 };
617622 
618623 /*
619
- * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
620
- * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
621
- * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
622
- * T1_TOP: Timer 1, top   :  <unused>
624
+ * Bottom half of timer0 is used for clockevent, top half is used for
625
+ * clocksource.
623626  */
624
-static struct davinci_timer_info dm355_timer_info = {
625
-	.timers		= davinci_timer_instance,
626
-	.clockevent_id	= T0_BOT,
627
-	.clocksource_id	= T0_TOP,
627
+static const struct davinci_timer_cfg dm355_timer_cfg = {
628
+	.reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
629
+	.irq = {
630
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
631
+		DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
632
+	},
628633 };
629634 
630635 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
631636 	{
632637 		.mapbase	= DAVINCI_UART0_BASE,
633
-		.irq		= IRQ_UARTINT0,
638
+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT0),
634639 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
635640 				  UPF_IOREMAP,
636641 		.iotype		= UPIO_MEM,
....@@ -643,7 +648,7 @@
643648 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
644649 	{
645650 		.mapbase	= DAVINCI_UART1_BASE,
646
-		.irq		= IRQ_UARTINT1,
651
+		.irq		= DAVINCI_INTC_IRQ(IRQ_UARTINT1),
647652 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
648653 				  UPF_IOREMAP,
649654 		.iotype		= UPIO_MEM,
....@@ -656,7 +661,7 @@
656661 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
657662 	{
658663 		.mapbase	= DM355_UART2_BASE,
659
-		.irq		= IRQ_DM355_UARTINT2,
664
+		.irq		= DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
660665 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
661666 				  UPF_IOREMAP,
662667 		.iotype		= UPIO_MEM,
....@@ -702,11 +707,6 @@
702707 	.pinmux_base		= DAVINCI_SYSTEM_MODULE_BASE,
703708 	.pinmux_pins		= dm355_pins,
704709 	.pinmux_pins_num	= ARRAY_SIZE(dm355_pins),
705
-	.intc_base		= DAVINCI_ARM_INTC_BASE,
706
-	.intc_type		= DAVINCI_INTC_TYPE_AINTC,
707
-	.intc_irq_prios		= dm355_default_priorities,
708
-	.intc_irq_num		= DAVINCI_N_AINTC_IRQ,
709
-	.timer_info		= &dm355_timer_info,
710710 	.sram_dma		= 0x00010000,
711711 	.sram_len		= SZ_32K,
712712 };
....@@ -733,6 +733,7 @@
733733 {
734734 	void __iomem *pll1, *psc;
735735 	struct clk *clk;
736
+	int rv;
736737 
737738 	clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
738739 
....@@ -743,8 +744,13 @@
743744 	dm355_psc_init(NULL, psc);
744745 
745746 	clk = clk_get(NULL, "timer0");
747
+	if (WARN_ON(IS_ERR(clk))) {
748
+		pr_err("Unable to get the timer clock\n");
749
+		return;
750
+	}
746751 
747
-	davinci_timer_init(clk);
752
+	rv = davinci_timer_register(clk, &dm355_timer_cfg);
753
+	WARN(rv, "Unable to register the timer: %d\n", rv);
748754 }
749755 
750756 static struct resource dm355_pll2_resources[] = {
....@@ -791,6 +797,21 @@
791797 	return 0;
792798 }
793799 
800
+static const struct davinci_aintc_config dm355_aintc_config = {
801
+	.reg = {
802
+		.start		= DAVINCI_ARM_INTC_BASE,
803
+		.end		= DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
804
+		.flags		= IORESOURCE_MEM,
805
+	},
806
+	.num_irqs		= 64,
807
+	.prios			= dm355_default_priorities,
808
+};
809
+
810
+void __init dm355_init_irq(void)
811
+{
812
+	davinci_aintc_init(&dm355_aintc_config);
813
+}
814
+
794815 static int __init dm355_init_devices(void)
795816 {
796817 	struct platform_device *edma_pdev;