enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arm/mach-davinci/board-neuros-osd2.c
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@@ -90,7 +90,7 @@
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 	.core_chipsel	= 0,
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 	.parts		= davinci_ntosd2_nandflash_partition,
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 	.nr_parts	= ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
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-	.ecc_mode	= NAND_ECC_HW,
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+	.engine_type	= NAND_ECC_ENGINE_TYPE_ON_HOST,
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 	.ecc_bits	= 1,
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 	.bbt_options	= NAND_BBT_USE_FLASH,
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 };
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@@ -130,10 +130,10 @@
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 };
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 static const struct gpio_led ntosd2_leds[] = {
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-	{ .name = "led1_green", .gpio = GPIO(10), },
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-	{ .name = "led1_red",   .gpio = GPIO(11), },
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-	{ .name = "led2_green", .gpio = GPIO(12), },
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-	{ .name = "led2_red",   .gpio = GPIO(13), },
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+	{ .name = "led1_green", .gpio = 10, },
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+	{ .name = "led1_red",   .gpio = 11, },
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+	{ .name = "led2_green", .gpio = 12, },
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+	{ .name = "led2_red",   .gpio = 13, },
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 };
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 static struct gpio_led_platform_data ntosd2_leds_data = {
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@@ -214,7 +214,7 @@
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 	 * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
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 	 * The AEAWx are five new AEAW pins that can be muxed by separately.
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 	 * They are a bitmask for GPIO management. According TI
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-	 * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
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+	 * documentation (https://www.ti.com/lit/gpn/tms320dm6446) to employ
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 	 * gpio(10,11,12,13) for leds any combination of bits works except
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 	 * four last. So we are to reset all five.
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 	 */
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@@ -231,7 +231,7 @@
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 	/* Maintainer: Neuros Technologies <neuros@groups.google.com> */
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 	.atag_offset	= 0x100,
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 	.map_io		 = davinci_ntosd2_map_io,
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-	.init_irq	= davinci_irq_init,
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+	.init_irq	= dm644x_init_irq,
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 	.init_time	= dm644x_init_time,
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 	.init_machine = davinci_ntosd2_init,
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 	.init_late	= davinci_init_late,