forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/arch/arm/boot/dts/tegra124.dtsi
....@@ -6,6 +6,7 @@
66 #include <dt-bindings/interrupt-controller/arm-gic.h>
77 #include <dt-bindings/reset/tegra124-car.h>
88 #include <dt-bindings/thermal/tegra124-soctherm.h>
9
+#include <dt-bindings/soc/tegra-pmc.h>
910 
1011 / {
1112 	compatible = "nvidia,tegra124";
....@@ -21,9 +22,9 @@
2122 	pcie@1003000 {
2223 		compatible = "nvidia,tegra124-pcie";
2324 		device_type = "pci";
24
-		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
25
-		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
26
-		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
25
+		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
26
+		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
27
+		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
2728 		reg-names = "pads", "afi", "cs";
2829 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2930 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
....@@ -37,11 +38,11 @@
3738 		#address-cells = <3>;
3839 		#size-cells = <2>;
3940 
40
-		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
41
-			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
42
-			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
43
-			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
44
-			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
41
+		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
42
+			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
43
+			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
44
+			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
45
+			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
4546 
4647 		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
4748 			 <&tegra_car TEGRA124_CLK_AFI>,
....@@ -84,11 +85,13 @@
8485 	};
8586 
8687 	host1x@50000000 {
87
-		compatible = "nvidia,tegra124-host1x", "simple-bus";
88
+		compatible = "nvidia,tegra124-host1x";
8889 		reg = <0x0 0x50000000 0x0 0x00034000>;
8990 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
9091 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
92
+		interrupt-names = "syncpt", "host1x";
9193 		clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
94
+		clock-names = "host1x";
9295 		resets = <&tegra_car 28>;
9396 		reset-names = "host1x";
9497 		iommus = <&mc TEGRA_SWGROUP_HC>;
....@@ -102,9 +105,8 @@
102105 			compatible = "nvidia,tegra124-dc";
103106 			reg = <0x0 0x54200000 0x0 0x00040000>;
104107 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
105
-			clocks = <&tegra_car TEGRA124_CLK_DISP1>,
106
-				 <&tegra_car TEGRA124_CLK_PLL_P>;
107
-			clock-names = "dc", "parent";
108
+			clocks = <&tegra_car TEGRA124_CLK_DISP1>;
109
+			clock-names = "dc";
108110 			resets = <&tegra_car 27>;
109111 			reset-names = "dc";
110112 
....@@ -117,9 +119,8 @@
117119 			compatible = "nvidia,tegra124-dc";
118120 			reg = <0x0 0x54240000 0x0 0x00040000>;
119121 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
120
-			clocks = <&tegra_car TEGRA124_CLK_DISP2>,
121
-				 <&tegra_car TEGRA124_CLK_PLL_P>;
122
-			clock-names = "dc", "parent";
122
+			clocks = <&tegra_car TEGRA124_CLK_DISP2>;
123
+			clock-names = "dc";
123124 			resets = <&tegra_car 26>;
124125 			reset-names = "dc";
125126 
....@@ -140,15 +141,28 @@
140141 			status = "disabled";
141142 		};
142143 
144
+		vic@54340000 {
145
+			compatible = "nvidia,tegra124-vic";
146
+			reg = <0x0 0x54340000 0x0 0x00040000>;
147
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
148
+			clocks = <&tegra_car TEGRA124_CLK_VIC03>;
149
+			clock-names = "vic";
150
+			resets = <&tegra_car 178>;
151
+			reset-names = "vic";
152
+
153
+			iommus = <&mc TEGRA_SWGROUP_VIC>;
154
+		};
155
+
143156 		sor@54540000 {
144157 			compatible = "nvidia,tegra124-sor";
145158 			reg = <0x0 0x54540000 0x0 0x00040000>;
146159 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
147160 			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
161
+				 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
148162 				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
149163 				 <&tegra_car TEGRA124_CLK_PLL_DP>,
150164 				 <&tegra_car TEGRA124_CLK_CLK_M>;
151
-			clock-names = "sor", "parent", "dp", "safe";
165
+			clock-names = "sor", "out", "parent", "dp", "safe";
152166 			resets = <&tegra_car 182>;
153167 			reset-names = "sor";
154168 			status = "disabled";
....@@ -164,6 +178,11 @@
164178 			resets = <&tegra_car 181>;
165179 			reset-names = "dpaux";
166180 			status = "disabled";
181
+
182
+			i2c-bus {
183
+				#address-cells = <1>;
184
+				#size-cells = <0>;
185
+			};
167186 		};
168187 	};
169188 
....@@ -582,11 +601,12 @@
582601 		clocks = <&tegra_car TEGRA124_CLK_RTC>;
583602 	};
584603 
585
-	pmc@7000e400 {
604
+	tegra_pmc: pmc@7000e400 {
586605 		compatible = "nvidia,tegra124-pmc";
587606 		reg = <0x0 0x7000e400 0x0 0x400>;
588607 		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
589608 		clock-names = "pclk", "clk32k_in";
609
+		#clock-cells = <1>;
590610 	};
591611 
592612 	fuse@7000f800 {
....@@ -607,11 +627,14 @@
607627 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
608628 
609629 		#iommu-cells = <1>;
630
+		#reset-cells = <1>;
610631 	};
611632 
612
-	emc: emc@7001b000 {
633
+	emc: external-memory-controller@7001b000 {
613634 		compatible = "nvidia,tegra124-emc";
614635 		reg = <0x0 0x7001b000 0x0 0x1000>;
636
+		clocks = <&tegra_car TEGRA124_CLK_EMC>;
637
+		clock-names = "emc";
615638 
616639 		nvidia,memory-controller = <&mc>;
617640 	};
....@@ -662,8 +685,8 @@
662685 			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
663686 			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
664687 			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
665
-			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
666688 			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
689
+			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
667690 			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
668691 			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
669692 			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
....@@ -671,7 +694,7 @@
671694 			 <&tegra_car TEGRA124_CLK_PLL_E>;
672695 		clock-names = "xusb_host", "xusb_host_src",
673696 			      "xusb_falcon_src", "xusb_ss",
674
-			      "xusb_ss_div2", "xusb_ss_src",
697
+			      "xusb_ss_src", "xusb_ss_div2",
675698 			      "xusb_hs_src", "xusb_fs_src",
676699 			      "pll_u_480m", "clk_m", "pll_e";
677700 		resets = <&tegra_car 89>, <&tegra_car 156>,
....@@ -816,41 +839,45 @@
816839 		};
817840 	};
818841 
819
-	sdhci@700b0000 {
842
+	mmc@700b0000 {
820843 		compatible = "nvidia,tegra124-sdhci";
821844 		reg = <0x0 0x700b0000 0x0 0x200>;
822845 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
823846 		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
847
+		clock-names = "sdhci";
824848 		resets = <&tegra_car 14>;
825849 		reset-names = "sdhci";
826850 		status = "disabled";
827851 	};
828852 
829
-	sdhci@700b0200 {
853
+	mmc@700b0200 {
830854 		compatible = "nvidia,tegra124-sdhci";
831855 		reg = <0x0 0x700b0200 0x0 0x200>;
832856 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
833857 		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
858
+		clock-names = "sdhci";
834859 		resets = <&tegra_car 9>;
835860 		reset-names = "sdhci";
836861 		status = "disabled";
837862 	};
838863 
839
-	sdhci@700b0400 {
864
+	mmc@700b0400 {
840865 		compatible = "nvidia,tegra124-sdhci";
841866 		reg = <0x0 0x700b0400 0x0 0x200>;
842867 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
843868 		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
869
+		clock-names = "sdhci";
844870 		resets = <&tegra_car 69>;
845871 		reset-names = "sdhci";
846872 		status = "disabled";
847873 	};
848874 
849
-	sdhci@700b0600 {
875
+	mmc@700b0600 {
850876 		compatible = "nvidia,tegra124-sdhci";
851877 		reg = <0x0 0x700b0600 0x0 0x200>;
852878 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
853879 		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
880
+		clock-names = "sdhci";
854881 		resets = <&tegra_car 15>;
855882 		reset-names = "sdhci";
856883 		status = "disabled";
....@@ -868,8 +895,8 @@
868895 
869896 	soctherm: thermal-sensor@700e2000 {
870897 		compatible = "nvidia,tegra124-soctherm";
871
-		reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
872
-			0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
898
+		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
899
+		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
873900 		reg-names = "soctherm-reg", "car-reg";
874901 		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
875902 		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
....@@ -1039,6 +1066,7 @@
10391066 		clock-names = "reg", "pll_u", "utmi-pads";
10401067 		resets = <&tegra_car 22>, <&tegra_car 22>;
10411068 		reset-names = "usb", "utmi-pads";
1069
+		#phy-cells = <0>;
10421070 		nvidia,hssync-start-delay = <0>;
10431071 		nvidia,idle-wait-delay = <17>;
10441072 		nvidia,elastic-limit = <16>;
....@@ -1076,6 +1104,7 @@
10761104 		clock-names = "reg", "pll_u", "utmi-pads";
10771105 		resets = <&tegra_car 58>, <&tegra_car 22>;
10781106 		reset-names = "usb", "utmi-pads";
1107
+		#phy-cells = <0>;
10791108 		nvidia,hssync-start-delay = <0>;
10801109 		nvidia,idle-wait-delay = <17>;
10811110 		nvidia,elastic-limit = <16>;
....@@ -1112,6 +1141,7 @@
11121141 		clock-names = "reg", "pll_u", "utmi-pads";
11131142 		resets = <&tegra_car 59>, <&tegra_car 22>;
11141143 		reset-names = "usb", "utmi-pads";
1144
+		#phy-cells = <0>;
11151145 		nvidia,hssync-start-delay = <0>;
11161146 		nvidia,idle-wait-delay = <17>;
11171147 		nvidia,elastic-limit = <16>;