forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/arch/arm/boot/dts/sun9i-a80.dtsi
....@@ -56,6 +56,10 @@
5656 	#size-cells = <2>;
5757 	interrupt-parent = <&gic>;
5858 
59
+	aliases {
60
+		ethernet0 = &gmac;
61
+	};
62
+
5963 	cpus {
6064 		#address-cells = <1>;
6165 		#size-cells = <0>;
....@@ -183,6 +187,37 @@
183187 			clock-output-names = "osc32k";
184188 		};
185189 
190
+		/*
191
+		 * The following two are dummy clocks, placeholders
192
+		 * used in the gmac_tx clock. The gmac driver will
193
+		 * choose one parent depending on the PHY interface
194
+		 * mode, using clk_set_rate auto-reparenting.
195
+		 *
196
+		 * The actual TX clock rate is not controlled by the
197
+		 * gmac_tx clock.
198
+		 */
199
+		mii_phy_tx_clk: mii_phy_tx_clk {
200
+			#clock-cells = <0>;
201
+			compatible = "fixed-clock";
202
+			clock-frequency = <25000000>;
203
+			clock-output-names = "mii_phy_tx";
204
+		};
205
+
206
+		gmac_int_tx_clk: gmac_int_tx_clk {
207
+			#clock-cells = <0>;
208
+			compatible = "fixed-clock";
209
+			clock-frequency = <125000000>;
210
+			clock-output-names = "gmac_int_tx";
211
+		};
212
+
213
+		gmac_tx_clk: clk@800030 {
214
+			#clock-cells = <0>;
215
+			compatible = "allwinner,sun7i-a20-gmac-clk";
216
+			reg = <0x00800030 0x4>;
217
+			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
218
+			clock-output-names = "gmac_tx";
219
+		};
220
+
186221 		cpus_clk: clk@8001410 {
187222 			compatible = "allwinner,sun9i-a80-cpus-clk";
188223 			reg = <0x08001410 0x4>;
....@@ -254,7 +289,7 @@
254289 		status = "disabled";
255290 	};
256291 
257
-	soc {
292
+	soc@20000 {
258293 		compatible = "simple-bus";
259294 		#address-cells = <1>;
260295 		#size-cells = <1>;
....@@ -280,6 +315,27 @@
280315 				 */
281316 				compatible = "allwinner,sun9i-a80-smp-sram";
282317 				reg = <0x1000 0x8>;
318
+			};
319
+		};
320
+
321
+		gmac: ethernet@830000 {
322
+			compatible = "allwinner,sun7i-a20-gmac";
323
+			reg = <0x00830000 0x1054>;
324
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
325
+			interrupt-names = "macirq";
326
+			clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
327
+			clock-names = "stmmaceth", "allwinner_gmac_tx";
328
+			resets = <&ccu RST_BUS_GMAC>;
329
+			reset-names = "stmmaceth";
330
+			snps,pbl = <2>;
331
+			snps,fixed-burst;
332
+			snps,force_sf_dma_mode;
333
+			status = "disabled";
334
+
335
+			mdio: mdio {
336
+				compatible = "snps,dwmac-mdio";
337
+				#address-cells = <1>;
338
+				#size-cells = <0>;
283339 			};
284340 		};
285341 
....@@ -331,16 +387,16 @@
331387 		usbphy2: phy@a01800 {
332388 			compatible = "allwinner,sun9i-a80-usb-phy";
333389 			reg = <0x00a01800 0x4>;
334
-			clocks = <&usb_clocks CLK_USB1_HSIC>,
390
+			clocks = <&usb_clocks CLK_USB1_PHY>,
335391 				 <&usb_clocks CLK_USB_HSIC>,
336
-				 <&usb_clocks CLK_USB1_PHY>;
337
-			clock-names = "hsic_480M",
392
+				 <&usb_clocks CLK_USB1_HSIC>;
393
+			clock-names = "phy",
338394 				      "hsic_12M",
339
-				      "phy";
340
-			resets = <&usb_clocks RST_USB1_HSIC>,
341
-				 <&usb_clocks RST_USB1_PHY>;
342
-			reset-names = "hsic",
343
-				      "phy";
395
+				      "hsic_480M";
396
+			resets = <&usb_clocks RST_USB1_PHY>,
397
+				 <&usb_clocks RST_USB1_HSIC>;
398
+			reset-names = "phy",
399
+				      "hsic";
344400 			status = "disabled";
345401 			#phy-cells = <0>;
346402 			/* usb1 is always used with HSIC */
....@@ -373,16 +429,16 @@
373429 		usbphy3: phy@a02800 {
374430 			compatible = "allwinner,sun9i-a80-usb-phy";
375431 			reg = <0x00a02800 0x4>;
376
-			clocks = <&usb_clocks CLK_USB2_HSIC>,
432
+			clocks = <&usb_clocks CLK_USB2_PHY>,
377433 				 <&usb_clocks CLK_USB_HSIC>,
378
-				 <&usb_clocks CLK_USB2_PHY>;
379
-			clock-names = "hsic_480M",
434
+				 <&usb_clocks CLK_USB2_HSIC>;
435
+			clock-names = "phy",
380436 				      "hsic_12M",
381
-				      "phy";
382
-			resets = <&usb_clocks RST_USB2_HSIC>,
383
-				 <&usb_clocks RST_USB2_PHY>;
384
-			reset-names = "hsic",
385
-				      "phy";
437
+				      "hsic_480M";
438
+			resets = <&usb_clocks RST_USB2_PHY>,
439
+				 <&usb_clocks RST_USB2_HSIC>;
440
+			reset-names = "phy",
441
+				      "hsic";
386442 			status = "disabled";
387443 			#phy-cells = <0>;
388444 		};
....@@ -399,6 +455,15 @@
399455 		cpucfg@1700000 {
400456 			compatible = "allwinner,sun9i-a80-cpucfg";
401457 			reg = <0x01700000 0x100>;
458
+		};
459
+
460
+		crypto: crypto@1c02000 {
461
+			compatible = "allwinner,sun9i-a80-crypto";
462
+			reg = <0x01c02000 0x1000>;
463
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
464
+			resets = <&ccu RST_BUS_SS>;
465
+			clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
466
+			clock-names = "bus", "mod";
402467 		};
403468 
404469 		mmc0: mmc@1c0f000 {
....@@ -465,9 +530,7 @@
465530 			compatible = "allwinner,sun9i-a80-mmc-config-clk";
466531 			reg = <0x01c13000 0x10>;
467532 			clocks = <&ccu CLK_BUS_MMC>;
468
-			clock-names = "ahb";
469533 			resets = <&ccu RST_BUS_MMC>;
470
-			reset-names = "ahb";
471534 			#clock-cells = <1>;
472535 			#reset-cells = <1>;
473536 			clock-output-names = "mmc0_config", "mmc1_config",
....@@ -475,7 +538,7 @@
475538 		};
476539 
477540 		gic: interrupt-controller@1c41000 {
478
-			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
541
+			compatible = "arm,gic-400";
479542 			reg = <0x01c41000 0x1000>,
480543 			      <0x01c42000 0x2000>,
481544 			      <0x01c44000 0x2000>,
....@@ -544,12 +607,9 @@
544607 				#size-cells = <0>;
545608 
546609 				fe0_out: port@1 {
547
-					#address-cells = <1>;
548
-					#size-cells = <0>;
549610 					reg = <1>;
550611 
551
-					fe0_out_deu0: endpoint@0 {
552
-						reg = <0>;
612
+					fe0_out_deu0: endpoint {
553613 						remote-endpoint = <&deu0_in_fe0>;
554614 					};
555615 				};
....@@ -571,12 +631,9 @@
571631 				#size-cells = <0>;
572632 
573633 				fe1_out: port@1 {
574
-					#address-cells = <1>;
575
-					#size-cells = <0>;
576634 					reg = <1>;
577635 
578
-					fe1_out_deu1: endpoint@0 {
579
-						reg = <0>;
636
+					fe1_out_deu1: endpoint {
580637 						remote-endpoint = <&deu1_in_fe1>;
581638 					};
582639 				};
....@@ -614,12 +671,9 @@
614671 				};
615672 
616673 				be0_out: port@1 {
617
-					#address-cells = <1>;
618
-					#size-cells = <0>;
619674 					reg = <1>;
620675 
621
-					be0_out_drc0: endpoint@0 {
622
-						reg = <0>;
676
+					be0_out_drc0: endpoint {
623677 						remote-endpoint = <&drc0_in_be0>;
624678 					};
625679 				};
....@@ -657,12 +711,9 @@
657711 				};
658712 
659713 				be1_out: port@1 {
660
-					#address-cells = <1>;
661
-					#size-cells = <0>;
662714 					reg = <1>;
663715 
664
-					be1_out_drc1: endpoint@0 {
665
-						reg = <0>;
716
+					be1_out_drc1: endpoint {
666717 						remote-endpoint = <&drc1_in_be1>;
667718 					};
668719 				};
....@@ -686,12 +737,9 @@
686737 				#size-cells = <0>;
687738 
688739 				deu0_in: port@0 {
689
-					#address-cells = <1>;
690
-					#size-cells = <0>;
691740 					reg = <0>;
692741 
693
-					deu0_in_fe0: endpoint@0 {
694
-						reg = <0>;
742
+					deu0_in_fe0: endpoint {
695743 						remote-endpoint = <&fe0_out_deu0>;
696744 					};
697745 				};
....@@ -731,12 +779,9 @@
731779 				#size-cells = <0>;
732780 
733781 				deu1_in: port@0 {
734
-					#address-cells = <1>;
735
-					#size-cells = <0>;
736782 					reg = <0>;
737783 
738
-					deu1_in_fe1: endpoint@0 {
739
-						reg = <0>;
784
+					deu1_in_fe1: endpoint {
740785 						remote-endpoint = <&fe1_out_deu1>;
741786 					};
742787 				};
....@@ -776,23 +821,17 @@
776821 				#size-cells = <0>;
777822 
778823 				drc0_in: port@0 {
779
-					#address-cells = <1>;
780
-					#size-cells = <0>;
781824 					reg = <0>;
782825 
783
-					drc0_in_be0: endpoint@0 {
784
-						reg = <0>;
826
+					drc0_in_be0: endpoint {
785827 						remote-endpoint = <&be0_out_drc0>;
786828 					};
787829 				};
788830 
789831 				drc0_out: port@1 {
790
-					#address-cells = <1>;
791
-					#size-cells = <0>;
792832 					reg = <1>;
793833 
794
-					drc0_out_tcon0: endpoint@0 {
795
-						reg = <0>;
834
+					drc0_out_tcon0: endpoint {
796835 						remote-endpoint = <&tcon0_in_drc0>;
797836 					};
798837 				};
....@@ -816,23 +855,17 @@
816855 				#size-cells = <0>;
817856 
818857 				drc1_in: port@0 {
819
-					#address-cells = <1>;
820
-					#size-cells = <0>;
821858 					reg = <0>;
822859 
823
-					drc1_in_be1: endpoint@0 {
824
-						reg = <0>;
860
+					drc1_in_be1: endpoint {
825861 						remote-endpoint = <&be1_out_drc1>;
826862 					};
827863 				};
828864 
829865 				drc1_out: port@1 {
830
-					#address-cells = <1>;
831
-					#size-cells = <0>;
832866 					reg = <1>;
833867 
834
-					drc1_out_tcon1: endpoint@0 {
835
-						reg = <0>;
868
+					drc1_out_tcon1: endpoint {
836869 						remote-endpoint = <&tcon1_in_drc1>;
837870 					};
838871 				};
....@@ -845,28 +878,28 @@
845878 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
846879 			clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
847880 			clock-names = "ahb", "tcon-ch0";
848
-			resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
849
-			reset-names = "lcd", "edp";
881
+			resets = <&ccu RST_BUS_LCD0>,
882
+				 <&ccu RST_BUS_EDP>,
883
+				 <&ccu RST_BUS_LVDS>;
884
+			reset-names = "lcd",
885
+				      "edp",
886
+				      "lvds";
850887 			clock-output-names = "tcon0-pixel-clock";
888
+			#clock-cells = <0>;
851889 
852890 			ports {
853891 				#address-cells = <1>;
854892 				#size-cells = <0>;
855893 
856894 				tcon0_in: port@0 {
857
-					#address-cells = <1>;
858
-					#size-cells = <0>;
859895 					reg = <0>;
860896 
861
-					tcon0_in_drc0: endpoint@0 {
862
-						reg = <0>;
897
+					tcon0_in_drc0: endpoint {
863898 						remote-endpoint = <&drc0_out_tcon0>;
864899 					};
865900 				};
866901 
867902 				tcon0_out: port@1 {
868
-					#address-cells = <1>;
869
-					#size-cells = <0>;
870903 					reg = <1>;
871904 				};
872905 			};
....@@ -886,19 +919,14 @@
886919 				#size-cells = <0>;
887920 
888921 				tcon1_in: port@0 {
889
-					#address-cells = <1>;
890
-					#size-cells = <0>;
891922 					reg = <0>;
892923 
893
-					tcon1_in_drc1: endpoint@0 {
894
-						reg = <0>;
924
+					tcon1_in_drc1: endpoint {
895925 						remote-endpoint = <&drc1_out_tcon1>;
896926 					};
897927 				};
898928 
899929 				tcon1_out: port@1 {
900
-					#address-cells = <1>;
901
-					#size-cells = <0>;
902930 					reg = <1>;
903931 				};
904932 			};
....@@ -930,6 +958,7 @@
930958 			compatible = "allwinner,sun6i-a31-wdt";
931959 			reg = <0x06000ca0 0x20>;
932960 			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
961
+			clocks = <&osc24M>;
933962 		};
934963 
935964 		pio: pinctrl@6000800 {
....@@ -945,8 +974,19 @@
945974 			gpio-controller;
946975 			interrupt-controller;
947976 			#interrupt-cells = <3>;
948
-			#size-cells = <0>;
949977 			#gpio-cells = <3>;
978
+
979
+			gmac_rgmii_pins: gmac-rgmii-pins {
980
+				pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
981
+				       "PA7", "PA8", "PA9", "PA10", "PA12",
982
+				       "PA13", "PA15", "PA16", "PA17";
983
+				function = "gmac";
984
+				/*
985
+				 * data lines in RGMII mode use DDR mode
986
+				 * and need a higher signal drive strength
987
+				 */
988
+				drive-strength = <40>;
989
+			};
950990 
951991 			i2c3_pins: i2c3-pins {
952992 				pins = "PG10", "PG11";
....@@ -1126,6 +1166,7 @@
11261166 			compatible = "allwinner,sun6i-a31-wdt";
11271167 			reg = <0x08001000 0x20>;
11281168 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1169
+			clocks = <&osc24M>;
11291170 		};
11301171 
11311172 		prcm@8001400 {
....@@ -1148,7 +1189,7 @@
11481189 		};
11491190 
11501191 		r_ir: ir@8002000 {
1151
-			compatible = "allwinner,sun5i-a13-ir";
1192
+			compatible = "allwinner,sun6i-a31-ir";
11521193 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
11531194 			pinctrl-names = "default";
11541195 			pinctrl-0 = <&r_ir_pins>;