forked from ~ljy/RK356X_SDK_RELEASE
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hc
2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87 
 kernel/arch/arm/boot/dts/sun6i-a31.dtsi
....@@ -42,8 +42,6 @@
4242  *     OTHER DEALINGS IN THE SOFTWARE.
4343  */
4444 
45
-#include "skeleton.dtsi"
46
-
4745 #include <dt-bindings/interrupt-controller/arm-gic.h>
4846 #include <dt-bindings/thermal/thermal.h>
4947 
....@@ -52,6 +50,8 @@
5250 
5351 / {
5452 	interrupt-parent = <&gic>;
53
+	#address-cells = <1>;
54
+	#size-cells = <1>;
5555 
5656 	aliases {
5757 		ethernet0 = &gmac;
....@@ -62,7 +62,7 @@
6262 		#size-cells = <1>;
6363 		ranges;
6464 
65
-		simplefb_hdmi: framebuffer@0 {
65
+		simplefb_hdmi: framebuffer-lcd0-hdmi {
6666 			compatible = "allwinner,simple-framebuffer",
6767 				     "simple-framebuffer";
6868 			allwinner,pipeline = "de_be0-lcd0-hdmi";
....@@ -73,7 +73,7 @@
7373 			status = "disabled";
7474 		};
7575 
76
-		simplefb_lcd: framebuffer@1 {
76
+		simplefb_lcd: framebuffer-lcd0 {
7777 			compatible = "allwinner,simple-framebuffer",
7878 				     "simple-framebuffer";
7979 			allwinner,pipeline = "de_be0-lcd0";
....@@ -115,7 +115,7 @@
115115 			#cooling-cells = <2>;
116116 		};
117117 
118
-		cpu@1 {
118
+		cpu1: cpu@1 {
119119 			compatible = "arm,cortex-a7";
120120 			device_type = "cpu";
121121 			reg = <1>;
....@@ -131,7 +131,7 @@
131131 			#cooling-cells = <2>;
132132 		};
133133 
134
-		cpu@2 {
134
+		cpu2: cpu@2 {
135135 			compatible = "arm,cortex-a7";
136136 			device_type = "cpu";
137137 			reg = <2>;
....@@ -147,7 +147,7 @@
147147 			#cooling-cells = <2>;
148148 		};
149149 
150
-		cpu@3 {
150
+		cpu3: cpu@3 {
151151 			compatible = "arm,cortex-a7";
152152 			device_type = "cpu";
153153 			reg = <3>;
....@@ -174,7 +174,10 @@
174174 			cooling-maps {
175175 				map0 {
176176 					trip = <&cpu_alert0>;
177
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
177
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
178
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
179
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
180
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
178181 				};
179182 			};
180183 
....@@ -196,10 +199,6 @@
196199 		};
197200 	};
198201 
199
-	memory {
200
-		reg = <0x40000000 0x80000000>;
201
-	};
202
-
203202 	pmu {
204203 		compatible = "arm,cortex-a7-pmu";
205204 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
....@@ -213,17 +212,20 @@
213212 		#size-cells = <1>;
214213 		ranges;
215214 
216
-		osc24M: osc24M {
215
+		osc24M: clk-24M {
217216 			#clock-cells = <0>;
218217 			compatible = "fixed-clock";
219218 			clock-frequency = <24000000>;
219
+			clock-accuracy = <50000>;
220
+			clock-output-names = "osc24M";
220221 		};
221222 
222
-		osc32k: clk@0 {
223
+		osc32k: clk-32k {
223224 			#clock-cells = <0>;
224225 			compatible = "fixed-clock";
225226 			clock-frequency = <32768>;
226
-			clock-output-names = "osc32k";
227
+			clock-accuracy = <50000>;
228
+			clock-output-names = "ext_osc32k";
227229 		};
228230 
229231 		/*
....@@ -235,14 +237,14 @@
235237 		 * The actual TX clock rate is not controlled by the
236238 		 * gmac_tx clock.
237239 		 */
238
-		mii_phy_tx_clk: clk@1 {
240
+		mii_phy_tx_clk: clk-mii-phy-tx {
239241 			#clock-cells = <0>;
240242 			compatible = "fixed-clock";
241243 			clock-frequency = <25000000>;
242244 			clock-output-names = "mii_phy_tx";
243245 		};
244246 
245
-		gmac_int_tx_clk: clk@2 {
247
+		gmac_int_tx_clk: clk-gmac-int-tx {
246248 			#clock-cells = <0>;
247249 			compatible = "fixed-clock";
248250 			clock-frequency = <125000000>;
....@@ -264,7 +266,7 @@
264266 		status = "disabled";
265267 	};
266268 
267
-	soc@1c00000 {
269
+	soc {
268270 		compatible = "simple-bus";
269271 		#address-cells = <1>;
270272 		#size-cells = <1>;
....@@ -283,15 +285,21 @@
283285 			compatible = "allwinner,sun6i-a31-tcon";
284286 			reg = <0x01c0c000 0x1000>;
285287 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
286
-			resets = <&ccu RST_AHB1_LCD0>;
287
-			reset-names = "lcd";
288
+			dmas = <&dma 11>;
289
+			resets = <&ccu RST_AHB1_LCD0>,
290
+				 <&ccu RST_AHB1_LVDS>;
291
+			reset-names = "lcd",
292
+				      "lvds";
288293 			clocks = <&ccu CLK_AHB1_LCD0>,
289294 				 <&ccu CLK_LCD0_CH0>,
290
-				 <&ccu CLK_LCD0_CH1>;
295
+				 <&ccu CLK_LCD0_CH1>,
296
+				 <&ccu 15>;
291297 			clock-names = "ahb",
292298 				      "tcon-ch0",
293
-				      "tcon-ch1";
299
+				      "tcon-ch1",
300
+				      "lvds-alt";
294301 			clock-output-names = "tcon0-pixel-clock";
302
+			#clock-cells = <0>;
295303 
296304 			ports {
297305 				#address-cells = <1>;
....@@ -331,15 +339,20 @@
331339 			compatible = "allwinner,sun6i-a31-tcon";
332340 			reg = <0x01c0d000 0x1000>;
333341 			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
334
-			resets = <&ccu RST_AHB1_LCD1>;
335
-			reset-names = "lcd";
342
+			dmas = <&dma 12>;
343
+			resets = <&ccu RST_AHB1_LCD1>,
344
+				 <&ccu RST_AHB1_LVDS>;
345
+			reset-names = "lcd", "lvds";
336346 			clocks = <&ccu CLK_AHB1_LCD1>,
337347 				 <&ccu CLK_LCD1_CH0>,
338
-				 <&ccu CLK_LCD1_CH1>;
348
+				 <&ccu CLK_LCD1_CH1>,
349
+				 <&ccu 15>;
339350 			clock-names = "ahb",
340351 				      "tcon-ch0",
341
-				      "tcon-ch1";
352
+				      "tcon-ch1",
353
+				      "lvds-alt";
342354 			clock-output-names = "tcon1-pixel-clock";
355
+			#clock-cells = <0>;
343356 
344357 			ports {
345358 				#address-cells = <1>;
....@@ -389,6 +402,8 @@
389402 			resets = <&ccu RST_AHB1_MMC0>;
390403 			reset-names = "ahb";
391404 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
405
+			pinctrl-names = "default";
406
+			pinctrl-0 = <&mmc0_pins>;
392407 			status = "disabled";
393408 			#address-cells = <1>;
394409 			#size-cells = <0>;
....@@ -408,6 +423,8 @@
408423 			resets = <&ccu RST_AHB1_MMC1>;
409424 			reset-names = "ahb";
410425 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
426
+			pinctrl-names = "default";
427
+			pinctrl-0 = <&mmc1_pins>;
411428 			status = "disabled";
412429 			#address-cells = <1>;
413430 			#size-cells = <0>;
....@@ -461,7 +478,6 @@
461478 				 <&ccu CLK_PLL_VIDEO1_2X>;
462479 			clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
463480 			resets = <&ccu RST_AHB1_HDMI>;
464
-			reset-names = "ahb";
465481 			dma-names = "ddc-tx", "ddc-rx", "audio-tx";
466482 			dmas = <&dma 13>, <&dma 13>, <&dma 14>;
467483 			status = "disabled";
....@@ -487,8 +503,6 @@
487503 				};
488504 
489505 				hdmi_out: port@1 {
490
-					#address-cells = <1>;
491
-					#size-cells = <0>;
492506 					reg = <1>;
493507 				};
494508 			};
....@@ -504,6 +518,7 @@
504518 			phys = <&usbphy 0>;
505519 			phy-names = "usb";
506520 			extcon = <&usbphy 0>;
521
+			dr_mode = "otg";
507522 			status = "disabled";
508523 		};
509524 
....@@ -587,7 +602,7 @@
587602 		ccu: clock@1c20000 {
588603 			compatible = "allwinner,sun6i-a31-ccu";
589604 			reg = <0x01c20000 0x400>;
590
-			clocks = <&osc24M>, <&osc32k>;
605
+			clocks = <&osc24M>, <&rtc 0>;
591606 			clock-names = "hosc", "losc";
592607 			#clock-cells = <1>;
593608 			#reset-cells = <1>;
....@@ -600,14 +615,14 @@
600615 				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
601616 				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
602617 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
603
-			clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
618
+			clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
604619 			clock-names = "apb", "hosc", "losc";
605620 			gpio-controller;
606621 			interrupt-controller;
607622 			#interrupt-cells = <3>;
608623 			#gpio-cells = <3>;
609624 
610
-			gmac_pins_gmii_a: gmac_gmii@0 {
625
+			gmac_gmii_pins: gmac-gmii-pins {
611626 				pins = "PA0", "PA1", "PA2", "PA3",
612627 						"PA4", "PA5", "PA6", "PA7",
613628 						"PA8", "PA9", "PA10", "PA11",
....@@ -623,7 +638,7 @@
623638 				drive-strength = <30>;
624639 			};
625640 
626
-			gmac_pins_mii_a: gmac_mii@0 {
641
+			gmac_mii_pins: gmac-mii-pins {
627642 				pins = "PA0", "PA1", "PA2", "PA3",
628643 						"PA8", "PA9", "PA11",
629644 						"PA12", "PA13", "PA14", "PA19",
....@@ -632,7 +647,7 @@
632647 				function = "gmac";
633648 			};
634649 
635
-			gmac_pins_rgmii_a: gmac_rgmii@0 {
650
+			gmac_rgmii_pins: gmac-rgmii-pins {
636651 				pins = "PA0", "PA1", "PA2", "PA3",
637652 						"PA9", "PA10", "PA11",
638653 						"PA12", "PA13", "PA14", "PA19",
....@@ -645,22 +660,22 @@
645660 				drive-strength = <40>;
646661 			};
647662 
648
-			i2c0_pins_a: i2c0@0 {
663
+			i2c0_pins: i2c0-pins {
649664 				pins = "PH14", "PH15";
650665 				function = "i2c0";
651666 			};
652667 
653
-			i2c1_pins_a: i2c1@0 {
668
+			i2c1_pins: i2c1-pins {
654669 				pins = "PH16", "PH17";
655670 				function = "i2c1";
656671 			};
657672 
658
-			i2c2_pins_a: i2c2@0 {
673
+			i2c2_pins: i2c2-pins {
659674 				pins = "PH18", "PH19";
660675 				function = "i2c2";
661676 			};
662677 
663
-			lcd0_rgb888_pins: lcd0_rgb888 {
678
+			lcd0_rgb888_pins: lcd0-rgb888-pins {
664679 				pins = "PD0", "PD1", "PD2", "PD3",
665680 						 "PD4", "PD5", "PD6", "PD7",
666681 						 "PD8", "PD9", "PD10", "PD11",
....@@ -671,7 +686,7 @@
671686 				function = "lcd0";
672687 			};
673688 
674
-			mmc0_pins_a: mmc0@0 {
689
+			mmc0_pins: mmc0-pins {
675690 				pins = "PF0", "PF1", "PF2",
676691 						 "PF3", "PF4", "PF5";
677692 				function = "mmc0";
....@@ -679,7 +694,7 @@
679694 				bias-pull-up;
680695 			};
681696 
682
-			mmc1_pins_a: mmc1@0 {
697
+			mmc1_pins: mmc1-pins {
683698 				pins = "PG0", "PG1", "PG2", "PG3",
684699 						 "PG4", "PG5";
685700 				function = "mmc1";
....@@ -687,7 +702,7 @@
687702 				bias-pull-up;
688703 			};
689704 
690
-			mmc2_pins_a: mmc2@0 {
705
+			mmc2_4bit_pins: mmc2-4bit-pins {
691706 				pins = "PC6", "PC7", "PC8", "PC9",
692707 						 "PC10", "PC11";
693708 				function = "mmc2";
....@@ -695,7 +710,7 @@
695710 				bias-pull-up;
696711 			};
697712 
698
-			mmc2_8bit_emmc_pins: mmc2@1 {
713
+			mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
699714 				pins = "PC6", "PC7", "PC8", "PC9",
700715 						 "PC10", "PC11", "PC12",
701716 						 "PC13", "PC14", "PC15",
....@@ -705,7 +720,7 @@
705720 				bias-pull-up;
706721 			};
707722 
708
-			mmc3_8bit_emmc_pins: mmc3@1 {
723
+			mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
709724 				pins = "PC6", "PC7", "PC8", "PC9",
710725 						 "PC10", "PC11", "PC12",
711726 						 "PC13", "PC14", "PC15",
....@@ -715,12 +730,12 @@
715730 				bias-pull-up;
716731 			};
717732 
718
-			spdif_pins_a: spdif@0 {
733
+			spdif_tx_pin: spdif-tx-pin {
719734 				pins = "PH28";
720735 				function = "spdif";
721736 			};
722737 
723
-			uart0_pins_a: uart0@0 {
738
+			uart0_ph_pins: uart0-ph-pins {
724739 				pins = "PH20", "PH21";
725740 				function = "uart0";
726741 			};
....@@ -733,13 +748,16 @@
733748 				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
734749 				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
735750 				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
736
-				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
751
+				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
752
+				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
737753 			clocks = <&osc24M>;
738754 		};
739755 
740756 		wdt1: watchdog@1c20ca0 {
741757 			compatible = "allwinner,sun6i-a31-wdt";
742758 			reg = <0x01c20ca0 0x20>;
759
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
760
+			clocks = <&osc24M>;
743761 		};
744762 
745763 		spdif: spdif@1c21000 {
....@@ -879,6 +897,8 @@
879897 			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
880898 			clocks = <&ccu CLK_APB2_I2C0>;
881899 			resets = <&ccu RST_APB2_I2C0>;
900
+			pinctrl-names = "default";
901
+			pinctrl-0 = <&i2c0_pins>;
882902 			status = "disabled";
883903 			#address-cells = <1>;
884904 			#size-cells = <0>;
....@@ -890,6 +910,8 @@
890910 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
891911 			clocks = <&ccu CLK_APB2_I2C1>;
892912 			resets = <&ccu RST_APB2_I2C1>;
913
+			pinctrl-names = "default";
914
+			pinctrl-0 = <&i2c1_pins>;
893915 			status = "disabled";
894916 			#address-cells = <1>;
895917 			#size-cells = <0>;
....@@ -901,6 +923,8 @@
901923 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
902924 			clocks = <&ccu CLK_APB2_I2C2>;
903925 			resets = <&ccu RST_APB2_I2C2>;
926
+			pinctrl-names = "default";
927
+			pinctrl-0 = <&i2c2_pins>;
904928 			status = "disabled";
905929 			#address-cells = <1>;
906930 			#size-cells = <0>;
....@@ -930,8 +954,12 @@
930954 			snps,fixed-burst;
931955 			snps,force_sf_dma_mode;
932956 			status = "disabled";
933
-			#address-cells = <1>;
934
-			#size-cells = <0>;
957
+
958
+			mdio: mdio {
959
+				compatible = "snps,dwmac-mdio";
960
+				#address-cells = <1>;
961
+				#size-cells = <0>;
962
+			};
935963 		};
936964 
937965 		crypto: crypto-engine@1c15000 {
....@@ -980,6 +1008,8 @@
9801008 			dma-names = "rx", "tx";
9811009 			resets = <&ccu RST_AHB1_SPI0>;
9821010 			status = "disabled";
1011
+			#address-cells = <1>;
1012
+			#size-cells = <0>;
9831013 		};
9841014 
9851015 		spi1: spi@1c69000 {
....@@ -992,6 +1022,8 @@
9921022 			dma-names = "rx", "tx";
9931023 			resets = <&ccu RST_AHB1_SPI1>;
9941024 			status = "disabled";
1025
+			#address-cells = <1>;
1026
+			#size-cells = <0>;
9951027 		};
9961028 
9971029 		spi2: spi@1c6a000 {
....@@ -1004,6 +1036,8 @@
10041036 			dma-names = "rx", "tx";
10051037 			resets = <&ccu RST_AHB1_SPI2>;
10061038 			status = "disabled";
1039
+			#address-cells = <1>;
1040
+			#size-cells = <0>;
10071041 		};
10081042 
10091043 		spi3: spi@1c6b000 {
....@@ -1016,10 +1050,12 @@
10161050 			dma-names = "rx", "tx";
10171051 			resets = <&ccu RST_AHB1_SPI3>;
10181052 			status = "disabled";
1053
+			#address-cells = <1>;
1054
+			#size-cells = <0>;
10191055 		};
10201056 
10211057 		gic: interrupt-controller@1c81000 {
1022
-			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1058
+			compatible = "arm,gic-400";
10231059 			reg = <0x01c81000 0x1000>,
10241060 			      <0x01c82000 0x2000>,
10251061 			      <0x01c84000 0x2000>,
....@@ -1103,9 +1139,6 @@
11031139 				      "ram";
11041140 			resets = <&ccu RST_AHB1_BE1>;
11051141 
1106
-			assigned-clocks = <&ccu CLK_BE1>;
1107
-			assigned-clock-rates = <300000000>;
1108
-
11091142 			ports {
11101143 				#address-cells = <1>;
11111144 				#size-cells = <0>;
....@@ -1148,9 +1181,6 @@
11481181 			clock-names = "ahb", "mod",
11491182 				      "ram";
11501183 			resets = <&ccu RST_AHB1_DRC1>;
1151
-
1152
-			assigned-clocks = <&ccu CLK_IEP_DRC1>;
1153
-			assigned-clock-rates = <300000000>;
11541184 
11551185 			ports {
11561186 				#address-cells = <1>;
....@@ -1195,9 +1225,6 @@
11951225 				      "ram";
11961226 			resets = <&ccu RST_AHB1_BE0>;
11971227 
1198
-			assigned-clocks = <&ccu CLK_BE0>;
1199
-			assigned-clock-rates = <300000000>;
1200
-
12011228 			ports {
12021229 				#address-cells = <1>;
12031230 				#size-cells = <0>;
....@@ -1219,12 +1246,9 @@
12191246 				};
12201247 
12211248 				be0_out: port@1 {
1222
-					#address-cells = <1>;
1223
-					#size-cells = <0>;
12241249 					reg = <1>;
12251250 
1226
-					be0_out_drc0: endpoint@0 {
1227
-						reg = <0>;
1251
+					be0_out_drc0: endpoint {
12281252 						remote-endpoint = <&drc0_in_be0>;
12291253 					};
12301254 				};
....@@ -1241,20 +1265,14 @@
12411265 				      "ram";
12421266 			resets = <&ccu RST_AHB1_DRC0>;
12431267 
1244
-			assigned-clocks = <&ccu CLK_IEP_DRC0>;
1245
-			assigned-clock-rates = <300000000>;
1246
-
12471268 			ports {
12481269 				#address-cells = <1>;
12491270 				#size-cells = <0>;
12501271 
12511272 				drc0_in: port@0 {
1252
-					#address-cells = <1>;
1253
-					#size-cells = <0>;
12541273 					reg = <0>;
12551274 
1256
-					drc0_in_be0: endpoint@0 {
1257
-						reg = <0>;
1275
+					drc0_in_be0: endpoint {
12581276 						remote-endpoint = <&be0_out_drc0>;
12591277 					};
12601278 				};
....@@ -1278,10 +1296,13 @@
12781296 		};
12791297 
12801298 		rtc: rtc@1f00000 {
1299
+			#clock-cells = <1>;
12811300 			compatible = "allwinner,sun6i-a31-rtc";
12821301 			reg = <0x01f00000 0x54>;
12831302 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
12841303 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1304
+			clocks = <&osc32k>;
1305
+			clock-output-names = "osc32k";
12851306 		};
12861307 
12871308 		nmi_intc: interrupt-controller@1f00c00 {
....@@ -1299,7 +1320,7 @@
12991320 			ar100: ar100_clk {
13001321 				compatible = "allwinner,sun6i-a31-ar100-clk";
13011322 				#clock-cells = <0>;
1302
-				clocks = <&osc32k>, <&osc24M>,
1323
+				clocks = <&rtc 0>, <&osc24M>,
13031324 					 <&ccu CLK_PLL_PERIPH>,
13041325 					 <&ccu CLK_PLL_PERIPH>;
13051326 				clock-output-names = "ar100";
....@@ -1334,7 +1355,7 @@
13341355 			ir_clk: ir_clk {
13351356 				#clock-cells = <0>;
13361357 				compatible = "allwinner,sun4i-a10-mod0-clk";
1337
-				clocks = <&osc32k>, <&osc24M>;
1358
+				clocks = <&rtc 0>, <&osc24M>;
13381359 				clock-output-names = "ir";
13391360 			};
13401361 
....@@ -1350,7 +1371,7 @@
13501371 		};
13511372 
13521373 		ir: ir@1f02000 {
1353
-			compatible = "allwinner,sun5i-a13-ir";
1374
+			compatible = "allwinner,sun6i-a31-ir";
13541375 			clocks = <&apb0_gates 1>, <&ir_clk>;
13551376 			clock-names = "apb", "ir";
13561377 			resets = <&apb0_rst 1>;
....@@ -1364,21 +1385,20 @@
13641385 			reg = <0x01f02c00 0x400>;
13651386 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
13661387 				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1367
-			clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
1388
+			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
13681389 			clock-names = "apb", "hosc", "losc";
13691390 			resets = <&apb0_rst 0>;
13701391 			gpio-controller;
13711392 			interrupt-controller;
13721393 			#interrupt-cells = <3>;
1373
-			#size-cells = <0>;
13741394 			#gpio-cells = <3>;
13751395 
1376
-			ir_pins_a: ir@0 {
1396
+			s_ir_rx_pin: s-ir-rx-pin {
13771397 				pins = "PL4";
13781398 				function = "s_ir";
13791399 			};
13801400 
1381
-			p2wi_pins: p2wi {
1401
+			s_p2wi_pins: s-p2wi-pins {
13821402 				pins = "PL0", "PL1";
13831403 				function = "s_p2wi";
13841404 			};
....@@ -1392,7 +1412,7 @@
13921412 			clock-frequency = <100000>;
13931413 			resets = <&apb0_rst 3>;
13941414 			pinctrl-names = "default";
1395
-			pinctrl-0 = <&p2wi_pins>;
1415
+			pinctrl-0 = <&s_p2wi_pins>;
13961416 			status = "disabled";
13971417 			#address-cells = <1>;
13981418 			#size-cells = <0>;