enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arm/boot/dts/dm816x.dtsi
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@@ -4,6 +4,8 @@
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  * kind, whether express or implied.
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  */
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+#include <dt-bindings/bus/ti-sysc.h>
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+#include <dt-bindings/clock/dm816.h>
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 #include <dt-bindings/gpio/gpio.h>
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 #include <dt-bindings/pinctrl/omap.h>
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..
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@@ -138,13 +140,123 @@
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 			};
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 		};
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-		edma: edma@49000000 {
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-			compatible = "ti,edma3";
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-			ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
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-			reg =   <0x49000000 0x10000>,
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-			        <0x44e10f90 0x40>;
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-			interrupts = <12 13 14>;
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-			#dma-cells = <1>;
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+		target-module@49000000 {
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+			compatible = "ti,sysc-omap4", "ti,sysc";
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+			reg = <0x49000000 0x4>;
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+			reg-names = "rev";
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+			clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
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+			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x49000000 0x10000>;
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+
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+			edma: dma@0 {
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+				compatible = "ti,edma3-tpcc";
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+				reg = <0 0x10000>;
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+				reg-names = "edma3_cc";
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+				interrupts = <12 13 14>;
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+				interrupt-names = "edma3_ccint", "edma3_mperr",
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+						  "edma3_ccerrint";
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+				dma-requests = <64>;
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+				#dma-cells = <2>;
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+
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+				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
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+					   <&edma_tptc2 3>, <&edma_tptc3 0>;
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+
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+				ti,edma-memcpy-channels = <20 21>;
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+			};
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+		};
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+
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+		target-module@49800000 {
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+			compatible = "ti,sysc-omap4", "ti,sysc";
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+			reg = <0x49800000 0x4>,
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+			      <0x49800010 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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+			ti,sysc-midle = <SYSC_IDLE_FORCE>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_SMART>;
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+			clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
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+			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x49800000 0x100000>;
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+
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+			edma_tptc0: dma@0 {
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+				compatible = "ti,edma3-tptc";
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+				reg = <0 0x100000>;
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+				interrupts = <112>;
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+				interrupt-names = "edma3_tcerrint";
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+			};
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+		};
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+
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+		target-module@49900000 {
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+			compatible = "ti,sysc-omap4", "ti,sysc";
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+			reg = <0x49900000 0x4>,
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+			      <0x49900010 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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+			ti,sysc-midle = <SYSC_IDLE_FORCE>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_SMART>;
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+			clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
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+			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x49900000 0x100000>;
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+
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+			edma_tptc1: dma@0 {
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+				compatible = "ti,edma3-tptc";
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+				reg = <0 0x100000>;
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+				interrupts = <113>;
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+				interrupt-names = "edma3_tcerrint";
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+			};
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+		};
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+
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+		target-module@49a00000 {
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+			compatible = "ti,sysc-omap4", "ti,sysc";
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+			reg = <0x49a00000 0x4>,
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+			      <0x49a00010 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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+			ti,sysc-midle = <SYSC_IDLE_FORCE>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_SMART>;
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+			clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
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+			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x49a00000 0x100000>;
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+
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+			edma_tptc2: dma@0 {
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+				compatible = "ti,edma3-tptc";
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+				reg = <0 0x100000>;
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+				interrupts = <114>;
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+				interrupt-names = "edma3_tcerrint";
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+			};
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+		};
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+
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+		target-module@49b00000 {
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+			compatible = "ti,sysc-omap4", "ti,sysc";
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+			reg = <0x49b00000 0x4>,
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+			      <0x49b00010 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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+			ti,sysc-midle = <SYSC_IDLE_FORCE>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_SMART>;
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+			clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
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+			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x49b00000 0x100000>;
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+
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+			edma_tptc3: dma@0 {
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+				compatible = "ti,edma3-tptc";
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+				reg = <0 0x100000>;
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+				interrupts = <115>;
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+				interrupt-names = "edma3_tcerrint";
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+			};
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 		};
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 		elm: elm@48080000 {
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@@ -185,7 +297,7 @@
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 			#address-cells = <2>;
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 			#size-cells = <1>;
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 			interrupts = <100>;
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-			dmas = <&edma 52>;
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+			dmas = <&edma 52 0>;
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 			dma-names = "rxtx";
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 			gpmc,num-cs = <6>;
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 			gpmc,num-waitpins = <2>;
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@@ -202,7 +314,7 @@
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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 			interrupts = <70>;
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-			dmas = <&edma 58 &edma 59>;
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+			dmas = <&edma 58 0 &edma 59 0>;
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 			dma-names = "tx", "rx";
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 		};
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@@ -213,7 +325,7 @@
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 			#address-cells = <1>;
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 			#size-cells = <0>;
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 			interrupts = <71>;
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-			dmas = <&edma 60 &edma 61>;
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+			dmas = <&edma 60 0 &edma 61 0>;
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 			dma-names = "tx", "rx";
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 		};
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@@ -239,7 +351,7 @@
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 			#mbox-cells = <1>;
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 			ti,mbox-num-users = <4>;
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 			ti,mbox-num-fifos = <12>;
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-			mbox_dsp: mbox_dsp {
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+			mbox_dsp: mbox-dsp {
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 				ti,mbox-tx = <3 0 0>;
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 				ti,mbox-rx = <0 0 0>;
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 			};
..
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@@ -311,10 +423,10 @@
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 			interrupts = <65>;
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 			ti,spi-num-cs = <4>;
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 			ti,hwmods = "mcspi1";
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-			dmas = <&edma 16 &edma 17
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-				&edma 18 &edma 19
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-				&edma 20 &edma 21
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-				&edma 22 &edma 23>;
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+			dmas = <&edma 16 0 &edma 17 0
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+				&edma 18 0 &edma 19 0
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+				&edma 20 0 &edma 21 0
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+				&edma 22 0 &edma 23 0>;
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 			dma-names = "tx0", "rx0", "tx1", "rx1",
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 				    "tx2", "rx2", "tx3", "rx3";
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 		};
..
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@@ -324,27 +436,59 @@
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 			reg = <0x48060000 0x11000>;
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 			ti,hwmods = "mmc1";
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 			interrupts = <64>;
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-			dmas = <&edma 24 &edma 25>;
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+			dmas = <&edma 24 0 &edma 25 0>;
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 			dma-names = "tx", "rx";
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 		};
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-		timer1: timer@4802e000 {
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-			compatible = "ti,dm816-timer";
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-			reg = <0x4802e000 0x2000>;
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-			interrupts = <67>;
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-			ti,hwmods = "timer1";
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-			ti,timer-alwon;
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-			clocks = <&timer1_fck>;
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+		timer1_target: target-module@4802e000 {
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+			compatible = "ti,sysc-omap4-timer", "ti,sysc";
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+			reg = <0x4802e000 0x4>,
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+			      <0x4802e010 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>,
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+					<SYSC_IDLE_SMART_WKUP>;
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+			clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
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 			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x4802e000 0x1000>;
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+
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+			timer1: timer@0 {
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+				compatible = "ti,dm816-timer";
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+				reg = <0 0x1000>;
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+				interrupts = <67>;
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+				ti,timer-alwon;
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+				clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
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+				clock-names = "fck";
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+			};
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 		};
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-		timer2: timer@48040000 {
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-			compatible = "ti,dm816-timer";
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-			reg = <0x48040000 0x2000>;
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-			interrupts = <68>;
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-			ti,hwmods = "timer2";
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-			clocks = <&timer2_fck>;
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+		timer2_target: target-module@48040000 {
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+			compatible = "ti,sysc-omap4-timer", "ti,sysc";
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+			reg = <0x48040000 0x4>,
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+			      <0x48040010 0x4>;
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+			reg-names = "rev", "sysc";
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+			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
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+			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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+					<SYSC_IDLE_NO>,
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+					<SYSC_IDLE_SMART>,
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+					<SYSC_IDLE_SMART_WKUP>;
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+			clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
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 			clock-names = "fck";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0x0 0x48040000 0x1000>;
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+
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+			timer2: timer@0 {
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+				compatible = "ti,dm816-timer";
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+				reg = <0 0x1000>;
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+				interrupts = <68>;
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+				clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
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+				clock-names = "fck";
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+			};
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 		};
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 		timer3: timer@48042000 {
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@@ -392,7 +536,7 @@
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 			reg = <0x48020000 0x2000>;
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 			clock-frequency = <48000000>;
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 			interrupts = <72>;
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-			dmas = <&edma 26 &edma 27>;
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+			dmas = <&edma 26 0 &edma 27 0>;
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 			dma-names = "tx", "rx";
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 		};
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@@ -402,7 +546,7 @@
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 			reg = <0x48022000 0x2000>;
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 			clock-frequency = <48000000>;
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 			interrupts = <73>;
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-			dmas = <&edma 28 &edma 29>;
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+			dmas = <&edma 28 0 &edma 29 0>;
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 			dma-names = "tx", "rx";
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 		};
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@@ -412,7 +556,7 @@
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 			reg = <0x48024000 0x2000>;
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 			clock-frequency = <48000000>;
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 			interrupts = <74>;
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-			dmas = <&edma 30 &edma 31>;
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+			dmas = <&edma 30 0 &edma 31 0>;
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 			dma-names = "tx", "rx";
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 		};
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@@ -530,3 +674,23 @@
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 };
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 #include "dm816x-clocks.dtsi"
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+
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+/* Preferred always-on timer for clocksource */
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+&timer1_target {
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+	ti,no-reset-on-init;
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+	ti,no-idle;
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+	timer@0 {
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+		assigned-clocks = <&timer1_fck>;
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+		assigned-clock-parents = <&sys_clkin_ck>;
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+	};
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+};
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+
688
+/* Preferred timer for clockevent */
689
+&timer2_target {
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+	ti,no-reset-on-init;
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+	ti,no-idle;
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+	timer@0 {
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+		assigned-clocks = <&timer2_fck>;
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+		assigned-clock-parents = <&sys_clkin_ck>;
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+	};
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+};