enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arm/boot/dts/bcm2837.dtsi
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@@ -1,4 +1,6 @@
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 #include "bcm283x.dtsi"
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+#include "bcm2835-common.dtsi"
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+#include "bcm2835-rpi-common.dtsi"
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 / {
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 	compatible = "brcm,bcm2837";
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@@ -38,12 +40,26 @@
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 		#size-cells = <0>;
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 		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
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+		/* Source for d/i-cache-line-size and d/i-cache-sets
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+		 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
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+		 * /about-the-l1-memory-system?lang=en
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+		 *
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+		 * Source for d/i-cache-size
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+		 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
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+		 */
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 		cpu0: cpu@0 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a53";
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 			reg = <0>;
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 			enable-method = "spin-table";
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 			cpu-release-addr = <0x0 0x000000d8>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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+			i-cache-size = <0x8000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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+			next-level-cache = <&l2>;
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 		};
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 		cpu1: cpu@1 {
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@@ -52,6 +68,13 @@
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 			reg = <1>;
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 			enable-method = "spin-table";
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 			cpu-release-addr = <0x0 0x000000e0>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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+			i-cache-size = <0x8000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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+			next-level-cache = <&l2>;
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 		};
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 		cpu2: cpu@2 {
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@@ -60,6 +83,13 @@
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 			reg = <2>;
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 			enable-method = "spin-table";
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 			cpu-release-addr = <0x0 0x000000e8>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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+			i-cache-size = <0x8000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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+			next-level-cache = <&l2>;
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 		};
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 		cpu3: cpu@3 {
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@@ -68,6 +98,27 @@
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 			reg = <3>;
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 			enable-method = "spin-table";
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 			cpu-release-addr = <0x0 0x000000f0>;
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+			d-cache-size = <0x8000>;
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+			d-cache-line-size = <64>;
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+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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+			i-cache-size = <0x8000>;
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+			i-cache-line-size = <64>;
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+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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+			next-level-cache = <&l2>;
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+		};
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+
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+		/* Source for cache-line-size + cache-sets
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+		 * https://developer.arm.com/documentation/ddi0500
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+		 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
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+		 * Source for cache-size
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+		 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
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+		 */
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+		l2: l2-cache0 {
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+			compatible = "cache";
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+			cache-size = <0x80000>;
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+			cache-line-size = <64>;
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+			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
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+			cache-level = <2>;
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 		};
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 	};
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 };