enable docker ppp

hc

2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arm/boot/dts/armada-38x.dtsi
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@@ -9,13 +9,15 @@
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  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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  */
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-#include "skeleton.dtsi"
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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 #include <dt-bindings/interrupt-controller/irq.h>
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 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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+
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 	model = "Marvell Armada 38x family SoC";
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 	compatible = "marvell,armada380";
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@@ -101,6 +103,11 @@
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 			#size-cells = <1>;
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 			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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+			sdramc: sdramc@1400 {
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+				compatible = "marvell,armada-xp-sdram-controller";
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+				reg = <0x1400 0x500>;
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+			};
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+
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 			L2: cache-controller@8000 {
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 				compatible = "arm,pl310-cache";
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 				reg = <0x8000 0x1000>;
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@@ -146,7 +153,6 @@
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 				#address-cells = <1>;
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 				#size-cells = <0>;
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 				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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-				timeout-ms = <1000>;
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 				clocks = <&coreclk 0>;
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 				status = "disabled";
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 			};
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@@ -157,7 +163,6 @@
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 				#address-cells = <1>;
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 				#size-cells = <0>;
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 				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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-				timeout-ms = <1000>;
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 				clocks = <&coreclk 0>;
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 				status = "disabled";
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 			};
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@@ -335,6 +340,44 @@
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 				#clock-cells = <1>;
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 			};
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+			comphy: phy@18300 {
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+				compatible = "marvell,armada-380-comphy";
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+				reg-names = "comphy", "conf";
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+				reg = <0x18300 0x100>, <0x18460 4>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				comphy0: phy@0 {
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+					reg = <0>;
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+					#phy-cells = <1>;
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+				};
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+
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+				comphy1: phy@1 {
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+					reg = <1>;
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+					#phy-cells = <1>;
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+				};
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+
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+				comphy2: phy@2 {
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+					reg = <2>;
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+					#phy-cells = <1>;
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+				};
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+
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+				comphy3: phy@3 {
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+					reg = <3>;
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+					#phy-cells = <1>;
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+				};
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+
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+				comphy4: phy@4 {
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+					reg = <4>;
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+					#phy-cells = <1>;
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+				};
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+
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+				comphy5: phy@5 {
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+					reg = <5>;
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+					#phy-cells = <1>;
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+				};
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+			};
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+
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 			coreclk: mvebu-sar@18600 {
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 				compatible = "marvell,armada-380-core-clock";
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 				reg = <0x18600 0x04>;
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@@ -376,6 +419,8 @@
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 				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
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 				clocks = <&coreclk 2>, <&refclk>;
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 				clock-names = "nbclk", "fixed";
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+				interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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+						      <&gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>;
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 			};
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 			cpurst: cpurst@20800 {