enable docker ppp

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2023-12-09 95099d4622f8cb224d94e314c7a8e0df60b13f87

 kernel/arch/arc/include/asm/arcregs.h
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@@ -1,9 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #ifndef _ASM_ARC_ARCREGS_H
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@@ -42,6 +39,8 @@
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 #define ARC_REG_CLUSTER_BCR	0xcf
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 #define ARC_REG_AUX_ICCM	0x208	/* ICCM Base Addr (ARCv2) */
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 #define ARC_REG_LPB_CTRL	0x488	/* ARCv2 Loop Buffer control */
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+#define ARC_REG_FPU_CTRL	0x300
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+#define ARC_REG_FPU_STATUS	0x301
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 /* Common for ARCompact and ARCv2 status register */
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 #define ARC_REG_STATUS32	0x0A
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@@ -82,6 +81,7 @@
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 #define ECR_V_DTLB_MISS			0x05
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 #define ECR_V_PROTV			0x06
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 #define ECR_V_TRAP			0x09
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+#define ECR_V_MISALIGN			0x0d
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 #endif
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 /* DTLB Miss and Protection Violation Cause Codes */
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@@ -117,6 +117,32 @@
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 #define ARC_AUX_DPFP_2L         0x303
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 #define ARC_AUX_DPFP_2H         0x304
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 #define ARC_AUX_DPFP_STAT       0x305
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+
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+/*
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+ * DSP-related registers
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+ * Registers names must correspond to dsp_callee_regs structure fields names
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+ * for automatic offset calculation in DSP_AUX_SAVE_RESTORE macros.
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+ */
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+#define ARC_AUX_DSP_BUILD	0x7A
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+#define ARC_AUX_ACC0_LO		0x580
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+#define ARC_AUX_ACC0_GLO	0x581
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+#define ARC_AUX_ACC0_HI		0x582
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+#define ARC_AUX_ACC0_GHI	0x583
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+#define ARC_AUX_DSP_BFLY0	0x598
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+#define ARC_AUX_DSP_CTRL	0x59F
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+#define ARC_AUX_DSP_FFT_CTRL	0x59E
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+
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+#define ARC_AUX_AGU_BUILD	0xCC
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+#define ARC_AUX_AGU_AP0		0x5C0
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+#define ARC_AUX_AGU_AP1		0x5C1
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+#define ARC_AUX_AGU_AP2		0x5C2
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+#define ARC_AUX_AGU_AP3		0x5C3
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+#define ARC_AUX_AGU_OS0		0x5D0
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+#define ARC_AUX_AGU_OS1		0x5D1
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+#define ARC_AUX_AGU_MOD0	0x5E0
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+#define ARC_AUX_AGU_MOD1	0x5E1
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+#define ARC_AUX_AGU_MOD2	0x5E2
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+#define ARC_AUX_AGU_MOD3	0x5E3
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 #ifndef __ASSEMBLY__
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@@ -167,14 +193,6 @@
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 #endif
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 };
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-struct bcr_extn_xymem {
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-#ifdef CONFIG_CPU_BIG_ENDIAN
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-	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
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-#else
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-	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
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-#endif
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-};
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-
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 struct bcr_iccm_arcompact {
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 #ifdef CONFIG_CPU_BIG_ENDIAN
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 	unsigned int base:16, pad:5, sz:3, ver:8;
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@@ -221,6 +239,14 @@
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 	unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
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 #else
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 	unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
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+#endif
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+};
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+
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+struct bcr_actionpoint {
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+#ifdef CONFIG_CPU_BIG_ENDIAN
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+	unsigned int pad:21, min:1, num:2, ver:8;
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+#else
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+	unsigned int ver:8, num:2, min:1, pad:21;
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 #endif
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 };
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@@ -291,7 +317,7 @@
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 };
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 struct cpuinfo_arc_bpu {
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-	unsigned int ver, full, num_cache, num_pred;
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+	unsigned int ver, full, num_cache, num_pred, ret_stk;
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 };
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 struct cpuinfo_arc_ccm {
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@@ -304,17 +330,16 @@
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 	struct cpuinfo_arc_bpu bpu;
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 	struct bcr_identity core;
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 	struct bcr_isa_arcv2 isa;
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-	const char *details, *name;
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+	const char *release, *name;
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 	unsigned int vec_base;
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 	struct cpuinfo_arc_ccm iccm, dccm;
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 	struct {
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 		unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
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 			     fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
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-			     debug:1, ap:1, smart:1, rtt:1, pad3:4,
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+			     ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
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 			     timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
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 	} extn;
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 	struct bcr_mpy extn_mpy;
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-	struct bcr_extn_xymem extn_xymem;
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 };
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 extern struct cpuinfo_arc cpuinfo_arc700[];