AX88772C_eeprom and ax8872c build together

hc

2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb

 kernel/tools/perf/pmu-events/arch/x86/sandybridge/other.json
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@@ -9,6 +9,15 @@
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         "CounterHTOff": "0,1,2,3,4,5,6,7"
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     },
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     {
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+        "EventCode": "0x4E",
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+        "Counter": "0,1,2,3",
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+        "UMask": "0x2",
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+        "EventName": "HW_PRE_REQ.DL1_MISS",
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+        "SampleAfterValue": "2000003",
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+        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
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+        "CounterHTOff": "0,1,2,3,4,5,6,7"
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+    },
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+    {
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         "EventCode": "0x5C",
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         "Counter": "0,1,2,3",
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         "UMask": "0x1",
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@@ -35,15 +44,6 @@
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         "EventName": "CPL_CYCLES.RING123",
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         "SampleAfterValue": "2000003",
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         "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
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-        "CounterHTOff": "0,1,2,3,4,5,6,7"
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-    },
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-    {
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-        "EventCode": "0x4E",
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-        "Counter": "0,1,2,3",
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-        "UMask": "0x2",
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-        "EventName": "HW_PRE_REQ.DL1_MISS",
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-        "SampleAfterValue": "2000003",
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-        "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
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         "CounterHTOff": "0,1,2,3,4,5,6,7"
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     },
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     {