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2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb 
 kernel/sound/soc/codecs/rk3328_codec.h
....@@ -1,24 +1,14 @@
1
+/* SPDX-License-Identifier: GPL-2.0 */
12 /*
2
- * rk3328_codec.h  --  rk3328 ALSA Soc Audio driver
3
+ * rk3328 ALSA SoC Audio driver
34  *
45  * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd All rights reserved.
5
- *
6
- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
8
- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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- *
186  */
197 
208 #ifndef _RK3328_CODEC_H
219 #define _RK3328_CODEC_H
10
+
11
+#include <linux/bitfield.h>
2212 
2313 /* codec register */
2414 #define CODEC_RESET			(0x00 << 2)
....@@ -36,178 +26,180 @@
3626 #define HPOUT_POP_CTRL			(0x2a << 2)
3727 
3828 /* REG00: CODEC_RESET */
39
-#define PWR_RST_BYPASS_DIS		BIT(6)
40
-#define PWR_RST_BYPASS_EN		BIT(6)
41
-#define DIG_CORE_RST			(0 << 1)
42
-#define DIG_CORE_WORK			BIT(1)
43
-#define SYS_RST				(0)
44
-#define SYS_WORK			BIT(0)
29
+#define PWR_RST_BYPASS_DIS		(0x0 << 6)
30
+#define PWR_RST_BYPASS_EN		(0x1 << 6)
31
+#define DIG_CORE_RST			(0x0 << 1)
32
+#define DIG_CORE_WORK			(0x1 << 1)
33
+#define SYS_RST				(0x0 << 0)
34
+#define SYS_WORK			(0x1 << 0)
4535 
4636 /* REG03: DAC_INIT_CTRL1 */
4737 #define PIN_DIRECTION_MASK		BIT(5)
48
-#define PIN_DIRECTION_IN		(0 << 5)
49
-#define PIN_DIRECTION_OUT		BIT(5)
38
+#define PIN_DIRECTION_IN		(0x0 << 5)
39
+#define PIN_DIRECTION_OUT		(0x1 << 5)
5040 #define DAC_I2S_MODE_MASK		BIT(4)
51
-#define DAC_I2S_MODE_SLAVE		(0 << 4)
52
-#define DAC_I2S_MODE_MASTER		BIT(4)
41
+#define DAC_I2S_MODE_SLAVE		(0x0 << 4)
42
+#define DAC_I2S_MODE_MASTER		(0x1 << 4)
5343 
5444 /* REG04: DAC_INIT_CTRL2 */
5545 #define DAC_I2S_LRP_MASK		BIT(7)
56
-#define DAC_I2S_LRP_NORMAL		(0 << 7)
57
-#define DAC_I2S_LRP_REVERSAL		BIT(7)
58
-#define DAC_VDL_MASK			(3 << 5)
59
-#define DAC_VDL_16BITS			(0 << 5)
60
-#define DAC_VDL_20BITS			BIT(5)
61
-#define DAC_VDL_24BITS			(2 << 5)
62
-#define DAC_VDL_32BITS			(3 << 5)
63
-#define DAC_MODE_MASK			(3 << 3)
64
-#define DAC_MODE_RJM			(0 << 3)
65
-#define DAC_MODE_LJM			BIT(3)
66
-#define DAC_MODE_I2S			(2 << 3)
67
-#define DAC_MODE_PCM			(3 << 3)
46
+#define DAC_I2S_LRP_NORMAL		(0x0 << 7)
47
+#define DAC_I2S_LRP_REVERSAL		(0x1 << 7)
48
+#define DAC_VDL_MASK			GENMASK(6, 5)
49
+#define DAC_VDL_16BITS			(0x0 << 5)
50
+#define DAC_VDL_20BITS			(0x1 << 5)
51
+#define DAC_VDL_24BITS			(0x2 << 5)
52
+#define DAC_VDL_32BITS			(0x3 << 5)
53
+#define DAC_MODE_MASK			GENMASK(4, 3)
54
+#define DAC_MODE_RJM			(0x0 << 3)
55
+#define DAC_MODE_LJM			(0x1 << 3)
56
+#define DAC_MODE_I2S			(0x2 << 3)
57
+#define DAC_MODE_PCM			(0x3 << 3)
6858 #define DAC_LR_SWAP_MASK		BIT(2)
69
-#define DAC_LR_SWAP_DIS			(0 << 2)
70
-#define DAC_LR_SWAP_EN			BIT(2)
59
+#define DAC_LR_SWAP_DIS			(0x0 << 2)
60
+#define DAC_LR_SWAP_EN			(0x1 << 2)
7161 
7262 /* REG05: DAC_INIT_CTRL3 */
73
-#define DAC_WL_MASK			(3 << 2)
74
-#define DAC_WL_16BITS			(0 << 2)
75
-#define DAC_WL_20BITS			BIT(2)
76
-#define DAC_WL_24BITS			(2 << 2)
77
-#define DAC_WL_32BITS			(3 << 2)
63
+#define DAC_WL_MASK			GENMASK(3, 2)
64
+#define DAC_WL_16BITS			(0x0 << 2)
65
+#define DAC_WL_20BITS			(0x1 << 2)
66
+#define DAC_WL_24BITS			(0x2 << 2)
67
+#define DAC_WL_32BITS			(0x3 << 2)
7868 #define DAC_RST_MASK			BIT(1)
79
-#define DAC_RST_EN			(0 << 1)
80
-#define DAC_RST_DIS			BIT(1)
69
+#define DAC_RST_EN			(0x0 << 1)
70
+#define DAC_RST_DIS			(0x1 << 1)
8171 #define DAC_BCP_MASK			BIT(0)
82
-#define DAC_BCP_NORMAL			(0 << 0)
83
-#define DAC_BCP_REVERSAL		BIT(0)
72
+#define DAC_BCP_NORMAL			(0x0 << 0)
73
+#define DAC_BCP_REVERSAL		(0x1 << 0)
8474 
8575 /* REG22: DAC_PRECHARGE_CTRL */
86
-#define DAC_CHARGE_PRECHARGE		BIT(7)
87
-#define DAC_CHARGE_DISCHARGE		(0 << 7)
8876 #define DAC_CHARGE_XCHARGE_MASK		BIT(7)
89
-#define DAC_CHARGE_CURRENT_64I		BIT(6)
77
+#define DAC_CHARGE_DISCHARGE		(0x0 << 7)
78
+#define DAC_CHARGE_PRECHARGE		(0x1 << 7)
9079 #define DAC_CHARGE_CURRENT_64I_MASK	BIT(6)
91
-#define DAC_CHARGE_CURRENT_32I		BIT(5)
80
+#define DAC_CHARGE_CURRENT_64I		(0x1 << 6)
9281 #define DAC_CHARGE_CURRENT_32I_MASK	BIT(5)
93
-#define DAC_CHARGE_CURRENT_16I		BIT(4)
82
+#define DAC_CHARGE_CURRENT_32I		(0x1 << 5)
9483 #define DAC_CHARGE_CURRENT_16I_MASK	BIT(4)
95
-#define DAC_CHARGE_CURRENT_08I		BIT(3)
84
+#define DAC_CHARGE_CURRENT_16I		(0x1 << 4)
9685 #define DAC_CHARGE_CURRENT_08I_MASK	BIT(3)
97
-#define DAC_CHARGE_CURRENT_04I		BIT(2)
86
+#define DAC_CHARGE_CURRENT_08I		(0x1 << 3)
9887 #define DAC_CHARGE_CURRENT_04I_MASK	BIT(2)
99
-#define DAC_CHARGE_CURRENT_02I		BIT(1)
88
+#define DAC_CHARGE_CURRENT_04I		(0x1 << 2)
10089 #define DAC_CHARGE_CURRENT_02I_MASK	BIT(1)
101
-#define DAC_CHARGE_CURRENT_I		BIT(0)
90
+#define DAC_CHARGE_CURRENT_02I		(0x1 << 1)
10291 #define DAC_CHARGE_CURRENT_I_MASK	BIT(0)
103
-#define DAC_CHARGE_CURRENT_ALL_MASK	(0x7f)
104
-#define DAC_CHARGE_CURRENT_ALL_OFF	(0x0)
105
-#define DAC_CHARGE_CURRENT_ALL_ON	(0x7f)
92
+#define DAC_CHARGE_CURRENT_I		(0x1 << 0)
93
+#define DAC_CHARGE_CURRENT_ALL_MASK	GENMASK(6, 0)
94
+#define DAC_CHARGE_CURRENT_ALL_OFF	0x00
95
+#define DAC_CHARGE_CURRENT_ALL_ON	0x7f
10696 
10797 /* REG23: DAC_PWR_CTRL */
108
-#define DAC_PWR_OFF			(0 << 6)
109
-#define DAC_PWR_ON			BIT(6)
11098 #define DAC_PWR_MASK			BIT(6)
111
-#define DACL_PATH_REFV_OFF		(0 << 5)
112
-#define DACL_PATH_REFV_ON		BIT(5)
99
+#define DAC_PWR_OFF			(0x0 << 6)
100
+#define DAC_PWR_ON			(0x1 << 6)
113101 #define DACL_PATH_REFV_MASK		BIT(5)
114
-#define HPOUTL_ZERO_CROSSING_OFF	(0 << 4)
115
-#define HPOUTL_ZERO_CROSSING_ON		BIT(4)
116
-#define DACR_PATH_REFV_OFF		(0 << 1)
117
-#define DACR_PATH_REFV_ON		BIT(1)
102
+#define DACL_PATH_REFV_OFF		(0x0 << 5)
103
+#define DACL_PATH_REFV_ON		(0x1 << 5)
104
+#define HPOUTL_ZERO_CROSSING_MASK	BIT(4)
105
+#define HPOUTL_ZERO_CROSSING_OFF	(0x0 << 4)
106
+#define HPOUTL_ZERO_CROSSING_ON		(0x1 << 4)
118107 #define DACR_PATH_REFV_MASK		BIT(1)
119
-#define HPOUTR_ZERO_CROSSING_OFF	(0 << 0)
120
-#define HPOUTR_ZERO_CROSSING_ON		BIT(0)
108
+#define DACR_PATH_REFV_OFF		(0x0 << 1)
109
+#define DACR_PATH_REFV_ON		(0x1 << 1)
110
+#define HPOUTR_ZERO_CROSSING_MASK	BIT(0)
111
+#define HPOUTR_ZERO_CROSSING_OFF	(0x0 << 0)
112
+#define HPOUTR_ZERO_CROSSING_ON		(0x1 << 0)
121113 
122114 /* REG24: DAC_CLK_CTRL */
123
-#define DACL_REFV_OFF			(0 << 7)
124
-#define DACL_REFV_ON			BIT(7)
125115 #define DACL_REFV_MASK			BIT(7)
126
-#define DACL_CLK_OFF			(0 << 6)
127
-#define DACL_CLK_ON			BIT(6)
116
+#define DACL_REFV_OFF			(0x0 << 7)
117
+#define DACL_REFV_ON			(0x1 << 7)
128118 #define DACL_CLK_MASK			BIT(6)
129
-#define DACL_OFF			(0 << 5)
130
-#define DACL_ON				BIT(5)
119
+#define DACL_CLK_OFF			(0x0 << 6)
120
+#define DACL_CLK_ON			(0x1 << 6)
131121 #define DACL_MASK			BIT(5)
132
-#define DACL_INIT_OFF			(0 << 4)
133
-#define DACL_INIT_ON			BIT(4)
122
+#define DACL_OFF			(0x0 << 5)
123
+#define DACL_ON				(0x1 << 5)
134124 #define DACL_INIT_MASK			BIT(4)
135
-#define DACR_REFV_OFF			(0 << 3)
136
-#define DACR_REFV_ON			BIT(3)
125
+#define DACL_INIT_OFF			(0x0 << 4)
126
+#define DACL_INIT_ON			(0x1 << 4)
137127 #define DACR_REFV_MASK			BIT(3)
138
-#define DACR_CLK_OFF			(0 << 2)
139
-#define DACR_CLK_ON			BIT(2)
128
+#define DACR_REFV_OFF			(0x0 << 3)
129
+#define DACR_REFV_ON			(0x1 << 3)
140130 #define DACR_CLK_MASK			BIT(2)
141
-#define DACR_OFF			(0 << 1)
142
-#define DACR_ON				BIT(1)
131
+#define DACR_CLK_OFF			(0x0 << 2)
132
+#define DACR_CLK_ON			(0x1 << 2)
143133 #define DACR_MASK			BIT(1)
144
-#define DACR_INIT_OFF			(0 << 0)
145
-#define DACR_INIT_ON			BIT(0)
134
+#define DACR_OFF			(0x0 << 1)
135
+#define DACR_ON				(0x1 << 1)
146136 #define DACR_INIT_MASK			BIT(0)
137
+#define DACR_INIT_OFF			(0x0 << 0)
138
+#define DACR_INIT_ON			(0x1 << 0)
147139 
148140 /* REG25: HPMIX_CTRL*/
149
-#define HPMIXL_DIS			(0 << 6)
150
-#define HPMIXL_EN			BIT(6)
151141 #define HPMIXL_MASK			BIT(6)
152
-#define HPMIXL_INIT_DIS			(0 << 5)
153
-#define HPMIXL_INIT_EN			BIT(5)
142
+#define HPMIXL_DIS			(0x0 << 6)
143
+#define HPMIXL_EN			(0x1 << 6)
154144 #define HPMIXL_INIT_MASK		BIT(5)
155
-#define HPMIXL_INIT2_DIS		(0 << 4)
156
-#define HPMIXL_INIT2_EN			BIT(4)
145
+#define HPMIXL_INIT_DIS			(0x0 << 5)
146
+#define HPMIXL_INIT_EN			(0x1 << 5)
157147 #define HPMIXL_INIT2_MASK		BIT(4)
158
-#define HPMIXR_DIS			(0 << 2)
159
-#define HPMIXR_EN			BIT(2)
148
+#define HPMIXL_INIT2_DIS		(0x0 << 4)
149
+#define HPMIXL_INIT2_EN			(0x1 << 4)
160150 #define HPMIXR_MASK			BIT(2)
161
-#define HPMIXR_INIT_DIS			(0 << 1)
162
-#define HPMIXR_INIT_EN			BIT(1)
151
+#define HPMIXR_DIS			(0x0 << 2)
152
+#define HPMIXR_EN			(0x1 << 2)
163153 #define HPMIXR_INIT_MASK		BIT(1)
164
-#define HPMIXR_INIT2_DIS		(0 << 0)
165
-#define HPMIXR_INIT2_EN			BIT(0)
154
+#define HPMIXR_INIT_DIS			(0x0 << 1)
155
+#define HPMIXR_INIT_EN			(0x1 << 1)
166156 #define HPMIXR_INIT2_MASK		BIT(0)
157
+#define HPMIXR_INIT2_DIS		(0x0 << 0)
158
+#define HPMIXR_INIT2_EN			(0x1 << 0)
167159 
168160 /* REG26: DAC_SELECT */
169
-#define DACL_SELECT			BIT(4)
170161 #define DACL_SELECT_MASK		BIT(4)
171
-#define DACL_UNSELECT			(0 << 4)
172
-#define DACR_SELECT			BIT(0)
162
+#define DACL_UNSELECT			(0x0 << 4)
163
+#define DACL_SELECT			(0x1 << 4)
173164 #define DACR_SELECT_MASK		BIT(0)
174
-#define DACR_UNSELECT			(0 << 0)
165
+#define DACR_UNSELECT			(0x0 << 0)
166
+#define DACR_SELECT			(0x1 << 0)
175167 
176168 /* REG27: HPOUT_CTRL */
177
-#define HPOUTL_DIS			(0 << 7)
178
-#define HPOUTL_EN			BIT(7)
179169 #define HPOUTL_MASK			BIT(7)
180
-#define HPOUTL_INIT_DIS			(0 << 6)
181
-#define HPOUTL_INIT_EN			BIT(6)
170
+#define HPOUTL_DIS			(0x0 << 7)
171
+#define HPOUTL_EN			(0x1 << 7)
182172 #define HPOUTL_INIT_MASK		BIT(6)
183
-#define HPOUTL_MUTE			(0 << 5)
184
-#define HPOUTL_UNMUTE			BIT(5)
173
+#define HPOUTL_INIT_DIS			(0x0 << 6)
174
+#define HPOUTL_INIT_EN			(0x1 << 6)
185175 #define HPOUTL_MUTE_MASK		BIT(5)
186
-#define HPOUTR_DIS			(0 << 4)
187
-#define HPOUTR_EN			BIT(4)
176
+#define HPOUTL_MUTE			(0x0 << 5)
177
+#define HPOUTL_UNMUTE			(0x1 << 5)
188178 #define HPOUTR_MASK			BIT(4)
189
-#define HPOUTR_INIT_DIS			(0 << 3)
190
-#define HPOUTR_INIT_EN			BIT(3)
179
+#define HPOUTR_DIS			(0x0 << 4)
180
+#define HPOUTR_EN			(0x1 << 4)
191181 #define HPOUTR_INIT_MASK		BIT(3)
192
-#define HPOUTR_MUTE			(0 << 2)
193
-#define HPOUTR_UNMUTE			BIT(2)
182
+#define HPOUTR_INIT_DIS			(0x0 << 3)
183
+#define HPOUTR_INIT_EN			(0x1 << 3)
194184 #define HPOUTR_MUTE_MASK		BIT(2)
185
+#define HPOUTR_MUTE			(0x0 << 2)
186
+#define HPOUTR_UNMUTE			(0x1 << 2)
195187 
196188 /* REG28: HPOUTL_GAIN_CTRL */
197
-#define HPOUTL_GAIN_MASK		(0X1f << 0)
189
+#define HPOUTL_GAIN_MASK		GENMASK(4, 0)
198190 
199191 /* REG29: HPOUTR_GAIN_CTRL */
200
-#define HPOUTR_GAIN_MASK		(0X1f << 0)
192
+#define HPOUTR_GAIN_MASK		GENMASK(4, 0)
201193 
202194 /* REG2a: HPOUT_POP_CTRL */
203
-#define HPOUTR_POP_XCHARGE		BIT(4)
204
-#define HPOUTR_POP_WORK			(2 << 4)
205
-#define HPOUTR_POP_MASK			(3 << 4)
206
-#define HPOUTL_POP_XCHARGE		BIT(0)
207
-#define HPOUTL_POP_WORK			(2 << 0)
208
-#define HPOUTL_POP_MASK			(3 << 0)
195
+#define HPOUTR_POP_MASK			GENMASK(5, 4)
196
+#define HPOUTR_POP_XCHARGE		(0x1 << 4)
197
+#define HPOUTR_POP_WORK			(0x2 << 4)
198
+#define HPOUTL_POP_MASK			GENMASK(1, 0)
199
+#define HPOUTL_POP_XCHARGE		(0x1 << 0)
200
+#define HPOUTL_POP_WORK			(0x2 << 0)
209201 
210
-#define RK3328_HIFI			(0)
202
+#define RK3328_HIFI			0
211203 
212204 struct rk3328_reg_msk_val {
213205 	unsigned int reg;