forked from ~ljy/RK356X_SDK_RELEASE
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hc
2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb 
 kernel/drivers/spi/spi-imx.c
....@@ -8,25 +8,31 @@
88 #include <linux/dmaengine.h>
99 #include <linux/dma-mapping.h>
1010 #include <linux/err.h>
11
-#include <linux/gpio.h>
1211 #include <linux/interrupt.h>
1312 #include <linux/io.h>
1413 #include <linux/irq.h>
1514 #include <linux/kernel.h>
1615 #include <linux/module.h>
16
+#include <linux/pinctrl/consumer.h>
1717 #include <linux/platform_device.h>
18
+#include <linux/pm_runtime.h>
1819 #include <linux/slab.h>
1920 #include <linux/spi/spi.h>
2021 #include <linux/spi/spi_bitbang.h>
2122 #include <linux/types.h>
2223 #include <linux/of.h>
2324 #include <linux/of_device.h>
24
-#include <linux/of_gpio.h>
25
+#include <linux/property.h>
2526 
2627 #include <linux/platform_data/dma-imx.h>
27
-#include <linux/platform_data/spi-imx.h>
2828 
2929 #define DRIVER_NAME "spi_imx"
30
+
31
+static bool use_dma = true;
32
+module_param(use_dma, bool, 0644);
33
+MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
34
+
35
+#define MXC_RPM_TIMEOUT		2000 /* 2000ms */
3036 
3137 #define MXC_CSPIRXDATA		0x00
3238 #define MXC_CSPITXDATA		0x04
....@@ -39,8 +45,8 @@
3945 #define MXC_INT_TE	(1 << 1) /* Transmit FIFO empty interrupt */
4046 #define MXC_INT_RDR	BIT(4) /* Receive date threshold interrupt */
4147 
42
-/* The maximum  bytes that a sdma BD can transfer.*/
43
-#define MAX_SDMA_BD_BYTES  (1 << 15)
48
+/* The maximum bytes that a sdma BD can transfer. */
49
+#define MAX_SDMA_BD_BYTES (1 << 15)
4450 #define MX51_ECSPI_CTRL_MAX_BURST	512
4551 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
4652 #define MX53_MAX_TRANSFER_BYTES		512
....@@ -59,11 +65,14 @@
5965 
6066 struct spi_imx_devtype_data {
6167 	void (*intctrl)(struct spi_imx_data *, int);
62
-	int (*config)(struct spi_device *);
68
+	int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
69
+	int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *);
6370 	void (*trigger)(struct spi_imx_data *);
6471 	int (*rx_available)(struct spi_imx_data *);
6572 	void (*reset)(struct spi_imx_data *);
73
+	void (*setup_wml)(struct spi_imx_data *);
6674 	void (*disable)(struct spi_imx_data *);
75
+	void (*disable_dma)(struct spi_imx_data *);
6776 	bool has_dmamode;
6877 	bool has_slavemode;
6978 	unsigned int fifo_size;
....@@ -84,7 +93,6 @@
8493 	unsigned long spi_clk;
8594 	unsigned int spi_bus_clk;
8695 
87
-	unsigned int speed_hz;
8896 	unsigned int bits_per_word;
8997 	unsigned int spi_drctl;
9098 
....@@ -216,7 +224,9 @@
216224 			 struct spi_transfer *transfer)
217225 {
218226 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
219
-	unsigned int bytes_per_word, i;
227
+
228
+	if (!use_dma || master->fallback)
229
+		return false;
220230 
221231 	if (!master->dma_rx)
222232 		return false;
....@@ -224,18 +234,25 @@
224234 	if (spi_imx->slave_mode)
225235 		return false;
226236 
227
-	bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
237
+	if (transfer->len < spi_imx->devtype_data->fifo_size)
238
+		return false;
228239 
229
-	for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
230
-		if (!(transfer->len % (i * bytes_per_word)))
231
-			break;
232
-	}
233
-
234
-	spi_imx->wml = i;
235240 	spi_imx->dynamic_burst = 0;
236241 
237242 	return true;
238243 }
244
+
245
+/*
246
+ * Note the number of natively supported chip selects for MX51 is 4. Some
247
+ * devices may have less actual SS pins but the register map supports 4. When
248
+ * using gpio chip selects the cs values passed into the macros below can go
249
+ * outside the range 0 - 3. We therefore need to limit the cs value to avoid
250
+ * corrupting bits outside the allocated locations.
251
+ *
252
+ * The simplest way to do this is to just mask the cs bits to 2 bits. This
253
+ * still allows all 4 native chip selects to work as well as gpio chip selects
254
+ * (which can use any of the 4 chip select configurations).
255
+ */
239256 
240257 #define MX51_ECSPI_CTRL		0x08
241258 #define MX51_ECSPI_CTRL_ENABLE		(1 <<  0)
....@@ -245,23 +262,23 @@
245262 #define MX51_ECSPI_CTRL_DRCTL(drctl)	((drctl) << 16)
246263 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET	8
247264 #define MX51_ECSPI_CTRL_PREDIV_OFFSET	12
248
-#define MX51_ECSPI_CTRL_CS(cs)		((cs) << 18)
265
+#define MX51_ECSPI_CTRL_CS(cs)		((cs & 3) << 18)
249266 #define MX51_ECSPI_CTRL_BL_OFFSET	20
250267 #define MX51_ECSPI_CTRL_BL_MASK		(0xfff << 20)
251268 
252269 #define MX51_ECSPI_CONFIG	0x0c
253
-#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
254
-#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
255
-#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
256
-#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
257
-#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs) + 20))
270
+#define MX51_ECSPI_CONFIG_SCLKPHA(cs)	(1 << ((cs & 3) +  0))
271
+#define MX51_ECSPI_CONFIG_SCLKPOL(cs)	(1 << ((cs & 3) +  4))
272
+#define MX51_ECSPI_CONFIG_SBBCTRL(cs)	(1 << ((cs & 3) +  8))
273
+#define MX51_ECSPI_CONFIG_SSBPOL(cs)	(1 << ((cs & 3) + 12))
274
+#define MX51_ECSPI_CONFIG_SCLKCTL(cs)	(1 << ((cs & 3) + 20))
258275 
259276 #define MX51_ECSPI_INT		0x10
260277 #define MX51_ECSPI_INT_TEEN		(1 <<  0)
261278 #define MX51_ECSPI_INT_RREN		(1 <<  3)
262279 #define MX51_ECSPI_INT_RDREN		(1 <<  4)
263280 
264
-#define MX51_ECSPI_DMA      0x14
281
+#define MX51_ECSPI_DMA		0x14
265282 #define MX51_ECSPI_DMA_TX_WML(wml)	((wml) & 0x3f)
266283 #define MX51_ECSPI_DMA_RX_WML(wml)	(((wml) & 0x3f) << 16)
267284 #define MX51_ECSPI_DMA_RXT_WML(wml)	(((wml) & 0x3f) << 24)
....@@ -429,8 +446,7 @@
429446 	unsigned int pre, post;
430447 	unsigned int fin = spi_imx->spi_clk;
431448 
432
-	if (unlikely(fspi > fin))
433
-		return 0;
449
+	fspi = min(fspi, fin);
434450 
435451 	post = fls(fin) - fls(fspi);
436452 	if (fin > fspi << post)
....@@ -482,6 +498,11 @@
482498 	writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
483499 }
484500 
501
+static void mx51_disable_dma(struct spi_imx_data *spi_imx)
502
+{
503
+	writel(0, spi_imx->base + MX51_ECSPI_DMA);
504
+}
505
+
485506 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
486507 {
487508 	u32 ctrl;
....@@ -491,11 +512,14 @@
491512 	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
492513 }
493514 
494
-static int mx51_ecspi_config(struct spi_device *spi)
515
+static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
516
+				      struct spi_message *msg)
495517 {
496
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
518
+	struct spi_device *spi = msg->spi;
519
+	struct spi_transfer *xfer;
497520 	u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
498
-	u32 clk = spi_imx->speed_hz, delay, reg;
521
+	u32 min_speed_hz = ~0U;
522
+	u32 testreg, delay;
499523 	u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
500524 
501525 	/* set Master or Slave mode */
....@@ -510,19 +534,21 @@
510534 	if (spi->mode & SPI_READY)
511535 		ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
512536 
513
-	/* set clock speed */
514
-	ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
515
-	spi_imx->spi_bus_clk = clk;
516
-
517537 	/* set chip select to use */
518538 	ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
519539 
520
-	if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
521
-		ctrl |= (spi_imx->slave_burst * 8 - 1)
522
-			<< MX51_ECSPI_CTRL_BL_OFFSET;
540
+	/*
541
+	 * The ctrl register must be written first, with the EN bit set other
542
+	 * registers must not be written to.
543
+	 */
544
+	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
545
+
546
+	testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
547
+	if (spi->mode & SPI_LOOP)
548
+		testreg |= MX51_ECSPI_TESTREG_LBC;
523549 	else
524
-		ctrl |= (spi_imx->bits_per_word - 1)
525
-			<< MX51_ECSPI_CTRL_BL_OFFSET;
550
+		testreg &= ~MX51_ECSPI_TESTREG_LBC;
551
+	writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
526552 
527553 	/*
528554 	 * eCSPI burst completion by Chip Select signal in Slave mode
....@@ -546,23 +572,11 @@
546572 		cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
547573 		cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
548574 	}
575
+
549576 	if (spi->mode & SPI_CS_HIGH)
550577 		cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
551578 	else
552579 		cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
553
-
554
-	if (spi_imx->usedma)
555
-		ctrl |= MX51_ECSPI_CTRL_SMC;
556
-
557
-	/* CTRL register always go first to bring out controller from reset */
558
-	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
559
-
560
-	reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
561
-	if (spi->mode & SPI_LOOP)
562
-		reg |= MX51_ECSPI_TESTREG_LBC;
563
-	else
564
-		reg &= ~MX51_ECSPI_TESTREG_LBC;
565
-	writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
566580 
567581 	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
568582 
....@@ -576,25 +590,68 @@
576590 	 * be asserted before the SCLK polarity changes, which would disrupt
577591 	 * the SPI communication as the device on the other end would consider
578592 	 * the change of SCLK polarity as a clock tick already.
593
+	 *
594
+	 * Because spi_imx->spi_bus_clk is only set in bitbang prepare_message
595
+	 * callback, iterate over all the transfers in spi_message, find the
596
+	 * one with lowest bus frequency, and use that bus frequency for the
597
+	 * delay calculation. In case all transfers have speed_hz == 0, then
598
+	 * min_speed_hz is ~0 and the resulting delay is zero.
579599 	 */
580
-	delay = (2 * 1000000) / clk;
600
+	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
601
+		if (!xfer->speed_hz)
602
+			continue;
603
+		min_speed_hz = min(xfer->speed_hz, min_speed_hz);
604
+	}
605
+
606
+	delay = (2 * 1000000) / min_speed_hz;
581607 	if (likely(delay < 10))	/* SCLK is faster than 100 kHz */
582608 		udelay(delay);
583609 	else			/* SCLK is _very_ slow */
584610 		usleep_range(delay, delay + 10);
585611 
612
+	return 0;
613
+}
614
+
615
+static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
616
+				       struct spi_device *spi)
617
+{
618
+	u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
619
+	u32 clk;
620
+
621
+	/* Clear BL field and set the right value */
622
+	ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
623
+	if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
624
+		ctrl |= (spi_imx->slave_burst * 8 - 1)
625
+			<< MX51_ECSPI_CTRL_BL_OFFSET;
626
+	else
627
+		ctrl |= (spi_imx->bits_per_word - 1)
628
+			<< MX51_ECSPI_CTRL_BL_OFFSET;
629
+
630
+	/* set clock speed */
631
+	ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
632
+		  0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
633
+	ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
634
+	spi_imx->spi_bus_clk = clk;
635
+
636
+	if (spi_imx->usedma)
637
+		ctrl |= MX51_ECSPI_CTRL_SMC;
638
+
639
+	writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
640
+
641
+	return 0;
642
+}
643
+
644
+static void mx51_setup_wml(struct spi_imx_data *spi_imx)
645
+{
586646 	/*
587647 	 * Configure the DMA register: setup the watermark
588648 	 * and enable DMA request.
589649 	 */
590
-
591
-	writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
650
+	writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
592651 		MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
593652 		MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
594653 		MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
595654 		MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
596
-
597
-	return 0;
598655 }
599656 
600657 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
....@@ -661,13 +718,19 @@
661718 	writel(reg, spi_imx->base + MXC_CSPICTRL);
662719 }
663720 
664
-static int mx31_config(struct spi_device *spi)
721
+static int mx31_prepare_message(struct spi_imx_data *spi_imx,
722
+				struct spi_message *msg)
665723 {
666
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
724
+	return 0;
725
+}
726
+
727
+static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
728
+				 struct spi_device *spi)
729
+{
667730 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
668731 	unsigned int clk;
669732 
670
-	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
733
+	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
671734 		MX31_CSPICTRL_DR_SHIFT;
672735 	spi_imx->spi_bus_clk = clk;
673736 
....@@ -684,7 +747,7 @@
684747 		reg |= MX31_CSPICTRL_POL;
685748 	if (spi->mode & SPI_CS_HIGH)
686749 		reg |= MX31_CSPICTRL_SSPOL;
687
-	if (!gpio_is_valid(spi->cs_gpio))
750
+	if (!spi->cs_gpiod)
688751 		reg |= (spi->chip_select) <<
689752 			(is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
690753 						  MX31_CSPICTRL_CS_SHIFT);
....@@ -702,8 +765,10 @@
702765 	writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
703766 
704767 	if (spi_imx->usedma) {
705
-		/* configure DMA requests when RXFIFO is half full and
706
-		   when TXFIFO is half empty */
768
+		/*
769
+		 * configure DMA requests when RXFIFO is half full and
770
+		 * when TXFIFO is half empty
771
+		 */
707772 		writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
708773 			spi_imx->base + MX31_CSPI_DMAREG);
709774 	}
....@@ -757,14 +822,20 @@
757822 	writel(reg, spi_imx->base + MXC_CSPICTRL);
758823 }
759824 
760
-static int mx21_config(struct spi_device *spi)
825
+static int mx21_prepare_message(struct spi_imx_data *spi_imx,
826
+				struct spi_message *msg)
761827 {
762
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
828
+	return 0;
829
+}
830
+
831
+static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
832
+				 struct spi_device *spi)
833
+{
763834 	unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
764835 	unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
765836 	unsigned int clk;
766837 
767
-	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
838
+	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
768839 		<< MX21_CSPICTRL_DR_SHIFT;
769840 	spi_imx->spi_bus_clk = clk;
770841 
....@@ -776,7 +847,7 @@
776847 		reg |= MX21_CSPICTRL_POL;
777848 	if (spi->mode & SPI_CS_HIGH)
778849 		reg |= MX21_CSPICTRL_SSPOL;
779
-	if (!gpio_is_valid(spi->cs_gpio))
850
+	if (!spi->cs_gpiod)
780851 		reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
781852 
782853 	writel(reg, spi_imx->base + MXC_CSPICTRL);
....@@ -826,13 +897,19 @@
826897 	writel(reg, spi_imx->base + MXC_CSPICTRL);
827898 }
828899 
829
-static int mx1_config(struct spi_device *spi)
900
+static int mx1_prepare_message(struct spi_imx_data *spi_imx,
901
+			       struct spi_message *msg)
830902 {
831
-	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
903
+	return 0;
904
+}
905
+
906
+static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
907
+				struct spi_device *spi)
908
+{
832909 	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
833910 	unsigned int clk;
834911 
835
-	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
912
+	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
836913 		MX1_CSPICTRL_DR_SHIFT;
837914 	spi_imx->spi_bus_clk = clk;
838915 
....@@ -860,7 +937,8 @@
860937 
861938 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
862939 	.intctrl = mx1_intctrl,
863
-	.config = mx1_config,
940
+	.prepare_message = mx1_prepare_message,
941
+	.prepare_transfer = mx1_prepare_transfer,
864942 	.trigger = mx1_trigger,
865943 	.rx_available = mx1_rx_available,
866944 	.reset = mx1_reset,
....@@ -873,7 +951,8 @@
873951 
874952 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
875953 	.intctrl = mx21_intctrl,
876
-	.config = mx21_config,
954
+	.prepare_message = mx21_prepare_message,
955
+	.prepare_transfer = mx21_prepare_transfer,
877956 	.trigger = mx21_trigger,
878957 	.rx_available = mx21_rx_available,
879958 	.reset = mx21_reset,
....@@ -887,7 +966,8 @@
887966 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
888967 	/* i.mx27 cspi shares the functions with i.mx21 one */
889968 	.intctrl = mx21_intctrl,
890
-	.config = mx21_config,
969
+	.prepare_message = mx21_prepare_message,
970
+	.prepare_transfer = mx21_prepare_transfer,
891971 	.trigger = mx21_trigger,
892972 	.rx_available = mx21_rx_available,
893973 	.reset = mx21_reset,
....@@ -900,7 +980,8 @@
900980 
901981 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
902982 	.intctrl = mx31_intctrl,
903
-	.config = mx31_config,
983
+	.prepare_message = mx31_prepare_message,
984
+	.prepare_transfer = mx31_prepare_transfer,
904985 	.trigger = mx31_trigger,
905986 	.rx_available = mx31_rx_available,
906987 	.reset = mx31_reset,
....@@ -914,7 +995,8 @@
914995 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
915996 	/* i.mx35 and later cspi shares the functions with i.mx31 one */
916997 	.intctrl = mx31_intctrl,
917
-	.config = mx31_config,
998
+	.prepare_message = mx31_prepare_message,
999
+	.prepare_transfer = mx31_prepare_transfer,
9181000 	.trigger = mx31_trigger,
9191001 	.rx_available = mx31_rx_available,
9201002 	.reset = mx31_reset,
....@@ -927,10 +1009,13 @@
9271009 
9281010 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
9291011 	.intctrl = mx51_ecspi_intctrl,
930
-	.config = mx51_ecspi_config,
1012
+	.prepare_message = mx51_ecspi_prepare_message,
1013
+	.prepare_transfer = mx51_ecspi_prepare_transfer,
9311014 	.trigger = mx51_ecspi_trigger,
9321015 	.rx_available = mx51_ecspi_rx_available,
9331016 	.reset = mx51_ecspi_reset,
1017
+	.setup_wml = mx51_setup_wml,
1018
+	.disable_dma = mx51_disable_dma,
9341019 	.fifo_size = 64,
9351020 	.has_dmamode = true,
9361021 	.dynamic_burst = true,
....@@ -941,9 +1026,11 @@
9411026 
9421027 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
9431028 	.intctrl = mx51_ecspi_intctrl,
944
-	.config = mx51_ecspi_config,
1029
+	.prepare_message = mx51_ecspi_prepare_message,
1030
+	.prepare_transfer = mx51_ecspi_prepare_transfer,
9451031 	.trigger = mx51_ecspi_trigger,
9461032 	.rx_available = mx51_ecspi_rx_available,
1033
+	.disable_dma = mx51_disable_dma,
9471034 	.reset = mx51_ecspi_reset,
9481035 	.fifo_size = 64,
9491036 	.has_dmamode = true,
....@@ -991,20 +1078,6 @@
9911078 };
9921079 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
9931080 
994
-static void spi_imx_chipselect(struct spi_device *spi, int is_active)
995
-{
996
-	int active = is_active != BITBANG_CS_INACTIVE;
997
-	int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
998
-
999
-	if (spi->mode & SPI_NO_CS)
1000
-		return;
1001
-
1002
-	if (!gpio_is_valid(spi->cs_gpio))
1003
-		return;
1004
-
1005
-	gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1006
-}
1007
-
10081081 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
10091082 {
10101083 	u32 ctrl;
....@@ -1049,7 +1122,7 @@
10491122 		if (!spi_imx->count)
10501123 			break;
10511124 		if (spi_imx->dynamic_burst &&
1052
-		    spi_imx->txfifo >=  DIV_ROUND_UP(spi_imx->remainder,
1125
+		    spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
10531126 						     fifo_words))
10541127 			break;
10551128 		spi_imx->tx(spi_imx);
....@@ -1138,13 +1211,21 @@
11381211 				 struct spi_transfer *t)
11391212 {
11401213 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1141
-	int ret;
11421214 
11431215 	if (!t)
11441216 		return 0;
11451217 
1218
+	if (!t->speed_hz) {
1219
+		if (!spi->max_speed_hz) {
1220
+			dev_err(&spi->dev, "no speed_hz provided!\n");
1221
+			return -EINVAL;
1222
+		}
1223
+		dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1224
+		spi_imx->spi_bus_clk = spi->max_speed_hz;
1225
+	} else
1226
+		spi_imx->spi_bus_clk = t->speed_hz;
1227
+
11461228 	spi_imx->bits_per_word = t->bits_per_word;
1147
-	spi_imx->speed_hz  = t->speed_hz;
11481229 
11491230 	/*
11501231 	 * Initialize the functions for transfer. To transfer non byte-aligned
....@@ -1175,15 +1256,9 @@
11751256 	}
11761257 
11771258 	if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1178
-		spi_imx->usedma = 1;
1259
+		spi_imx->usedma = true;
11791260 	else
1180
-		spi_imx->usedma = 0;
1181
-
1182
-	if (spi_imx->usedma) {
1183
-		ret = spi_imx_dma_configure(spi->master);
1184
-		if (ret)
1185
-			return ret;
1186
-	}
1261
+		spi_imx->usedma = false;
11871262 
11881263 	if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
11891264 		spi_imx->rx = mx53_ecspi_rx_slave;
....@@ -1191,7 +1266,7 @@
11911266 		spi_imx->slave_burst = t->len;
11921267 	}
11931268 
1194
-	spi_imx->devtype_data->config(spi);
1269
+	spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
11951270 
11961271 	return 0;
11971272 }
....@@ -1223,7 +1298,7 @@
12231298 	spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
12241299 
12251300 	/* Prepare for TX DMA: */
1226
-	master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1301
+	master->dma_tx = dma_request_chan(dev, "tx");
12271302 	if (IS_ERR(master->dma_tx)) {
12281303 		ret = PTR_ERR(master->dma_tx);
12291304 		dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
....@@ -1232,7 +1307,7 @@
12321307 	}
12331308 
12341309 	/* Prepare for RX : */
1235
-	master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1310
+	master->dma_rx = dma_request_chan(dev, "rx");
12361311 	if (IS_ERR(master->dma_rx)) {
12371312 		ret = PTR_ERR(master->dma_rx);
12381313 		dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
....@@ -1289,6 +1364,32 @@
12891364 	unsigned long timeout;
12901365 	struct spi_master *master = spi_imx->bitbang.master;
12911366 	struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1367
+	struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1368
+	unsigned int bytes_per_word, i;
1369
+	int ret;
1370
+
1371
+	/* Get the right burst length from the last sg to ensure no tail data */
1372
+	bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1373
+	for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1374
+		if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1375
+			break;
1376
+	}
1377
+	/* Use 1 as wml in case no available burst length got */
1378
+	if (i == 0)
1379
+		i = 1;
1380
+
1381
+	spi_imx->wml =  i;
1382
+
1383
+	ret = spi_imx_dma_configure(master);
1384
+	if (ret)
1385
+		goto dma_failure_no_start;
1386
+
1387
+	if (!spi_imx->devtype_data->setup_wml) {
1388
+		dev_err(spi_imx->dev, "No setup_wml()?\n");
1389
+		ret = -EINVAL;
1390
+		goto dma_failure_no_start;
1391
+	}
1392
+	spi_imx->devtype_data->setup_wml(spi_imx);
12921393 
12931394 	/*
12941395 	 * The TX DMA setup starts the transfer, so make sure RX is configured
....@@ -1297,8 +1398,10 @@
12971398 	desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
12981399 				rx->sgl, rx->nents, DMA_DEV_TO_MEM,
12991400 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1300
-	if (!desc_rx)
1301
-		return -EINVAL;
1401
+	if (!desc_rx) {
1402
+		ret = -EINVAL;
1403
+		goto dma_failure_no_start;
1404
+	}
13021405 
13031406 	desc_rx->callback = spi_imx_dma_rx_callback;
13041407 	desc_rx->callback_param = (void *)spi_imx;
....@@ -1311,6 +1414,7 @@
13111414 				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
13121415 	if (!desc_tx) {
13131416 		dmaengine_terminate_all(master->dma_tx);
1417
+		dmaengine_terminate_all(master->dma_rx);
13141418 		return -EINVAL;
13151419 	}
13161420 
....@@ -1342,6 +1446,10 @@
13421446 	}
13431447 
13441448 	return transfer->len;
1449
+/* fallback to pio */
1450
+dma_failure_no_start:
1451
+	transfer->error |= SPI_TRANS_FAIL_NO_START;
1452
+	return ret;
13451453 }
13461454 
13471455 static int spi_imx_pio_transfer(struct spi_device *spi,
....@@ -1425,6 +1533,8 @@
14251533 {
14261534 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
14271535 
1536
+	transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1537
+
14281538 	/* flush rxfifo before transfer */
14291539 	while (spi_imx->devtype_data->rx_available(spi_imx))
14301540 		readl(spi_imx->base + MXC_CSPIRXDATA);
....@@ -1434,23 +1544,14 @@
14341544 
14351545 	if (spi_imx->usedma)
14361546 		return spi_imx_dma_transfer(spi_imx, transfer);
1437
-	else
1438
-		return spi_imx_pio_transfer(spi, transfer);
1547
+
1548
+	return spi_imx_pio_transfer(spi, transfer);
14391549 }
14401550 
14411551 static int spi_imx_setup(struct spi_device *spi)
14421552 {
14431553 	dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
14441554 		 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1445
-
1446
-	if (spi->mode & SPI_NO_CS)
1447
-		return 0;
1448
-
1449
-	if (gpio_is_valid(spi->cs_gpio))
1450
-		gpio_direction_output(spi->cs_gpio,
1451
-				      spi->mode & SPI_CS_HIGH ? 0 : 1);
1452
-
1453
-	spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
14541555 
14551556 	return 0;
14561557 }
....@@ -1465,17 +1566,19 @@
14651566 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
14661567 	int ret;
14671568 
1468
-	ret = clk_enable(spi_imx->clk_per);
1469
-	if (ret)
1470
-		return ret;
1471
-
1472
-	ret = clk_enable(spi_imx->clk_ipg);
1473
-	if (ret) {
1474
-		clk_disable(spi_imx->clk_per);
1569
+	ret = pm_runtime_resume_and_get(spi_imx->dev);
1570
+	if (ret < 0) {
1571
+		dev_err(spi_imx->dev, "failed to enable clock\n");
14751572 		return ret;
14761573 	}
14771574 
1478
-	return 0;
1575
+	ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1576
+	if (ret) {
1577
+		pm_runtime_mark_last_busy(spi_imx->dev);
1578
+		pm_runtime_put_autosuspend(spi_imx->dev);
1579
+	}
1580
+
1581
+	return ret;
14791582 }
14801583 
14811584 static int
....@@ -1483,8 +1586,8 @@
14831586 {
14841587 	struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
14851588 
1486
-	clk_disable(spi_imx->clk_ipg);
1487
-	clk_disable(spi_imx->clk_per);
1589
+	pm_runtime_mark_last_busy(spi_imx->dev);
1590
+	pm_runtime_put_autosuspend(spi_imx->dev);
14881591 	return 0;
14891592 }
14901593 
....@@ -1503,20 +1606,14 @@
15031606 	struct device_node *np = pdev->dev.of_node;
15041607 	const struct of_device_id *of_id =
15051608 			of_match_device(spi_imx_dt_ids, &pdev->dev);
1506
-	struct spi_imx_master *mxc_platform_info =
1507
-			dev_get_platdata(&pdev->dev);
15081609 	struct spi_master *master;
15091610 	struct spi_imx_data *spi_imx;
15101611 	struct resource *res;
1511
-	int i, ret, irq, spi_drctl;
1612
+	int ret, irq, spi_drctl;
15121613 	const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
15131614 		(struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
15141615 	bool slave_mode;
1515
-
1516
-	if (!np && !mxc_platform_info) {
1517
-		dev_err(&pdev->dev, "can't get the platform data\n");
1518
-		return -EINVAL;
1519
-	}
1616
+	u32 val;
15201617 
15211618 	slave_mode = devtype_data->has_slavemode &&
15221619 			of_property_read_bool(np, "spi-slave");
....@@ -1539,6 +1636,7 @@
15391636 
15401637 	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
15411638 	master->bus_num = np ? -1 : pdev->id;
1639
+	master->use_gpio_descriptors = true;
15421640 
15431641 	spi_imx = spi_master_get_devdata(master);
15441642 	spi_imx->bitbang.master = master;
....@@ -1547,28 +1645,17 @@
15471645 
15481646 	spi_imx->devtype_data = devtype_data;
15491647 
1550
-	/* Get number of chip selects, either platform data or OF */
1551
-	if (mxc_platform_info) {
1552
-		master->num_chipselect = mxc_platform_info->num_chipselect;
1553
-		if (mxc_platform_info->chipselect) {
1554
-			master->cs_gpios = devm_kcalloc(&master->dev,
1555
-				master->num_chipselect, sizeof(int),
1556
-				GFP_KERNEL);
1557
-			if (!master->cs_gpios)
1558
-				return -ENOMEM;
1648
+	/*
1649
+	 * Get number of chip selects from device properties. This can be
1650
+	 * coming from device tree or boardfiles, if it is not defined,
1651
+	 * a default value of 3 chip selects will be used, as all the legacy
1652
+	 * board files have <= 3 chip selects.
1653
+	 */
1654
+	if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1655
+		master->num_chipselect = val;
1656
+	else
1657
+		master->num_chipselect = 3;
15591658 
1560
-			for (i = 0; i < master->num_chipselect; i++)
1561
-				master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1562
-		}
1563
-	} else {
1564
-		u32 num_cs;
1565
-
1566
-		if (!of_property_read_u32(np, "num-cs", &num_cs))
1567
-			master->num_chipselect = num_cs;
1568
-		/* If not preset, default value of 1 is used */
1569
-	}
1570
-
1571
-	spi_imx->bitbang.chipselect = spi_imx_chipselect;
15721659 	spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
15731660 	spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
15741661 	spi_imx->bitbang.master->setup = spi_imx_setup;
....@@ -1627,6 +1714,12 @@
16271714 	if (ret)
16281715 		goto out_put_per;
16291716 
1717
+	pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1718
+	pm_runtime_use_autosuspend(spi_imx->dev);
1719
+	pm_runtime_get_noresume(spi_imx->dev);
1720
+	pm_runtime_set_active(spi_imx->dev);
1721
+	pm_runtime_enable(spi_imx->dev);
1722
+
16301723 	spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
16311724 	/*
16321725 	 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
....@@ -1635,10 +1728,10 @@
16351728 	if (spi_imx->devtype_data->has_dmamode) {
16361729 		ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
16371730 		if (ret == -EPROBE_DEFER)
1638
-			goto out_clk_put;
1731
+			goto out_runtime_pm_put;
16391732 
16401733 		if (ret < 0)
1641
-			dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1734
+			dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
16421735 				ret);
16431736 	}
16441737 
....@@ -1649,36 +1742,23 @@
16491742 	master->dev.of_node = pdev->dev.of_node;
16501743 	ret = spi_bitbang_start(&spi_imx->bitbang);
16511744 	if (ret) {
1652
-		dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1653
-		goto out_clk_put;
1745
+		dev_err_probe(&pdev->dev, ret, "bitbang start failed\n");
1746
+		goto out_bitbang_start;
16541747 	}
16551748 
1656
-	/* Request GPIO CS lines, if any */
1657
-	if (!spi_imx->slave_mode && master->cs_gpios) {
1658
-		for (i = 0; i < master->num_chipselect; i++) {
1659
-			if (!gpio_is_valid(master->cs_gpios[i]))
1660
-				continue;
1749
+	pm_runtime_mark_last_busy(spi_imx->dev);
1750
+	pm_runtime_put_autosuspend(spi_imx->dev);
16611751 
1662
-			ret = devm_gpio_request(&pdev->dev,
1663
-						master->cs_gpios[i],
1664
-						DRIVER_NAME);
1665
-			if (ret) {
1666
-				dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1667
-					master->cs_gpios[i]);
1668
-				goto out_spi_bitbang;
1669
-			}
1670
-		}
1671
-	}
1672
-
1673
-	dev_info(&pdev->dev, "probed\n");
1674
-
1675
-	clk_disable(spi_imx->clk_ipg);
1676
-	clk_disable(spi_imx->clk_per);
16771752 	return ret;
16781753 
1679
-out_spi_bitbang:
1680
-	spi_bitbang_stop(&spi_imx->bitbang);
1681
-out_clk_put:
1754
+out_bitbang_start:
1755
+	if (spi_imx->devtype_data->has_dmamode)
1756
+		spi_imx_sdma_exit(spi_imx);
1757
+out_runtime_pm_put:
1758
+	pm_runtime_dont_use_autosuspend(spi_imx->dev);
1759
+	pm_runtime_set_suspended(&pdev->dev);
1760
+	pm_runtime_disable(spi_imx->dev);
1761
+
16821762 	clk_disable_unprepare(spi_imx->clk_ipg);
16831763 out_put_per:
16841764 	clk_disable_unprepare(spi_imx->clk_per);
....@@ -1696,30 +1776,80 @@
16961776 
16971777 	spi_bitbang_stop(&spi_imx->bitbang);
16981778 
1699
-	ret = clk_enable(spi_imx->clk_per);
1700
-	if (ret)
1701
-		return ret;
1779
+	ret = pm_runtime_get_sync(spi_imx->dev);
1780
+	if (ret >= 0)
1781
+		writel(0, spi_imx->base + MXC_CSPICTRL);
1782
+	else
1783
+		dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
17021784 
1703
-	ret = clk_enable(spi_imx->clk_ipg);
1704
-	if (ret) {
1705
-		clk_disable(spi_imx->clk_per);
1706
-		return ret;
1707
-	}
1785
+	pm_runtime_dont_use_autosuspend(spi_imx->dev);
1786
+	pm_runtime_put_sync(spi_imx->dev);
1787
+	pm_runtime_disable(spi_imx->dev);
17081788 
1709
-	writel(0, spi_imx->base + MXC_CSPICTRL);
1710
-	clk_disable_unprepare(spi_imx->clk_ipg);
1711
-	clk_disable_unprepare(spi_imx->clk_per);
17121789 	spi_imx_sdma_exit(spi_imx);
17131790 	spi_master_put(master);
17141791 
17151792 	return 0;
17161793 }
17171794 
1795
+static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1796
+{
1797
+	struct spi_master *master = dev_get_drvdata(dev);
1798
+	struct spi_imx_data *spi_imx;
1799
+	int ret;
1800
+
1801
+	spi_imx = spi_master_get_devdata(master);
1802
+
1803
+	ret = clk_prepare_enable(spi_imx->clk_per);
1804
+	if (ret)
1805
+		return ret;
1806
+
1807
+	ret = clk_prepare_enable(spi_imx->clk_ipg);
1808
+	if (ret) {
1809
+		clk_disable_unprepare(spi_imx->clk_per);
1810
+		return ret;
1811
+	}
1812
+
1813
+	return 0;
1814
+}
1815
+
1816
+static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1817
+{
1818
+	struct spi_master *master = dev_get_drvdata(dev);
1819
+	struct spi_imx_data *spi_imx;
1820
+
1821
+	spi_imx = spi_master_get_devdata(master);
1822
+
1823
+	clk_disable_unprepare(spi_imx->clk_per);
1824
+	clk_disable_unprepare(spi_imx->clk_ipg);
1825
+
1826
+	return 0;
1827
+}
1828
+
1829
+static int __maybe_unused spi_imx_suspend(struct device *dev)
1830
+{
1831
+	pinctrl_pm_select_sleep_state(dev);
1832
+	return 0;
1833
+}
1834
+
1835
+static int __maybe_unused spi_imx_resume(struct device *dev)
1836
+{
1837
+	pinctrl_pm_select_default_state(dev);
1838
+	return 0;
1839
+}
1840
+
1841
+static const struct dev_pm_ops imx_spi_pm = {
1842
+	SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1843
+				spi_imx_runtime_resume, NULL)
1844
+	SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1845
+};
1846
+
17181847 static struct platform_driver spi_imx_driver = {
17191848 	.driver = {
17201849 		   .name = DRIVER_NAME,
17211850 		   .of_match_table = spi_imx_dt_ids,
1722
-		   },
1851
+		   .pm = &imx_spi_pm,
1852
+	},
17231853 	.id_table = spi_imx_devtype,
17241854 	.probe = spi_imx_probe,
17251855 	.remove = spi_imx_remove,