| .. | .. |
|---|
| 54 | 54 | if (unlikely(!buf->sg[0].data)) |
|---|
| 55 | 55 | goto out; |
|---|
| 56 | 56 | |
|---|
| 57 | | - dma_device = &conn->fdev->mdev->pdev->dev; |
|---|
| 57 | + dma_device = mlx5_core_dma_dev(conn->fdev->mdev); |
|---|
| 58 | 58 | buf->sg[0].dma_addr = dma_map_single(dma_device, buf->sg[0].data, |
|---|
| 59 | 59 | buf->sg[0].size, buf->dma_dir); |
|---|
| 60 | 60 | err = dma_mapping_error(dma_device, buf->sg[0].dma_addr); |
|---|
| .. | .. |
|---|
| 86 | 86 | { |
|---|
| 87 | 87 | struct device *dma_device; |
|---|
| 88 | 88 | |
|---|
| 89 | | - dma_device = &conn->fdev->mdev->pdev->dev; |
|---|
| 89 | + dma_device = mlx5_core_dma_dev(conn->fdev->mdev); |
|---|
| 90 | 90 | if (buf->sg[1].data) |
|---|
| 91 | 91 | dma_unmap_single(dma_device, buf->sg[1].dma_addr, |
|---|
| 92 | 92 | buf->sg[1].size, buf->dma_dir); |
|---|
| .. | .. |
|---|
| 135 | 135 | *conn->qp.wq.sq.db = cpu_to_be32(conn->qp.sq.pc); |
|---|
| 136 | 136 | /* Make sure that doorbell record is visible before ringing */ |
|---|
| 137 | 137 | wmb(); |
|---|
| 138 | | - mlx5_write64(wqe, conn->fdev->conn_res.uar->map + MLX5_BF_OFFSET, NULL); |
|---|
| 138 | + mlx5_write64(wqe, conn->fdev->conn_res.uar->map + MLX5_BF_OFFSET); |
|---|
| 139 | 139 | } |
|---|
| 140 | 140 | |
|---|
| 141 | 141 | static void mlx5_fpga_conn_post_send(struct mlx5_fpga_conn *conn, |
|---|
| .. | .. |
|---|
| 165 | 165 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; |
|---|
| 166 | 166 | ctrl->opmod_idx_opcode = cpu_to_be32(((conn->qp.sq.pc & 0xffff) << 8) | |
|---|
| 167 | 167 | MLX5_OPCODE_SEND); |
|---|
| 168 | | - ctrl->qpn_ds = cpu_to_be32(size | (conn->qp.mqp.qpn << 8)); |
|---|
| 168 | + ctrl->qpn_ds = cpu_to_be32(size | (conn->qp.qpn << 8)); |
|---|
| 169 | 169 | |
|---|
| 170 | 170 | conn->qp.sq.pc++; |
|---|
| 171 | 171 | conn->qp.sq.bufs[ix] = buf; |
|---|
| .. | .. |
|---|
| 334 | 334 | { |
|---|
| 335 | 335 | u8 opcode, status = 0; |
|---|
| 336 | 336 | |
|---|
| 337 | | - opcode = cqe->op_own >> 4; |
|---|
| 337 | + opcode = get_cqe_opcode(cqe); |
|---|
| 338 | 338 | |
|---|
| 339 | 339 | switch (opcode) { |
|---|
| 340 | 340 | case MLX5_CQE_REQ_ERR: |
|---|
| 341 | 341 | status = ((struct mlx5_err_cqe *)cqe)->syndrome; |
|---|
| 342 | | - /* Fall through */ |
|---|
| 342 | + fallthrough; |
|---|
| 343 | 343 | case MLX5_CQE_REQ: |
|---|
| 344 | 344 | mlx5_fpga_conn_sq_cqe(conn, cqe, status); |
|---|
| 345 | 345 | break; |
|---|
| 346 | 346 | |
|---|
| 347 | 347 | case MLX5_CQE_RESP_ERR: |
|---|
| 348 | 348 | status = ((struct mlx5_err_cqe *)cqe)->syndrome; |
|---|
| 349 | | - /* Fall through */ |
|---|
| 349 | + fallthrough; |
|---|
| 350 | 350 | case MLX5_CQE_RESP_SEND: |
|---|
| 351 | 351 | mlx5_fpga_conn_rq_cqe(conn, cqe, status); |
|---|
| 352 | 352 | break; |
|---|
| .. | .. |
|---|
| 360 | 360 | { |
|---|
| 361 | 361 | mlx5_cq_arm(&conn->cq.mcq, MLX5_CQ_DB_REQ_NOT, |
|---|
| 362 | 362 | conn->fdev->conn_res.uar->map, conn->cq.wq.cc); |
|---|
| 363 | | -} |
|---|
| 364 | | - |
|---|
| 365 | | -static void mlx5_fpga_conn_cq_event(struct mlx5_core_cq *mcq, |
|---|
| 366 | | - enum mlx5_event event) |
|---|
| 367 | | -{ |
|---|
| 368 | | - struct mlx5_fpga_conn *conn; |
|---|
| 369 | | - |
|---|
| 370 | | - conn = container_of(mcq, struct mlx5_fpga_conn, cq.mcq); |
|---|
| 371 | | - mlx5_fpga_warn(conn->fdev, "CQ event %u on CQ #%u\n", event, mcq->cqn); |
|---|
| 372 | | -} |
|---|
| 373 | | - |
|---|
| 374 | | -static void mlx5_fpga_conn_event(struct mlx5_core_qp *mqp, int event) |
|---|
| 375 | | -{ |
|---|
| 376 | | - struct mlx5_fpga_conn *conn; |
|---|
| 377 | | - |
|---|
| 378 | | - conn = container_of(mqp, struct mlx5_fpga_conn, qp.mqp); |
|---|
| 379 | | - mlx5_fpga_warn(conn->fdev, "QP event %u on QP #%u\n", event, mqp->qpn); |
|---|
| 380 | 363 | } |
|---|
| 381 | 364 | |
|---|
| 382 | 365 | static inline void mlx5_fpga_conn_cqes(struct mlx5_fpga_conn *conn, |
|---|
| .. | .. |
|---|
| 405 | 388 | mlx5_fpga_conn_arm_cq(conn); |
|---|
| 406 | 389 | } |
|---|
| 407 | 390 | |
|---|
| 408 | | -static void mlx5_fpga_conn_cq_tasklet(unsigned long data) |
|---|
| 391 | +static void mlx5_fpga_conn_cq_tasklet(struct tasklet_struct *t) |
|---|
| 409 | 392 | { |
|---|
| 410 | | - struct mlx5_fpga_conn *conn = (void *)data; |
|---|
| 393 | + struct mlx5_fpga_conn *conn = from_tasklet(conn, t, cq.tasklet); |
|---|
| 411 | 394 | |
|---|
| 412 | 395 | if (unlikely(!conn->qp.active)) |
|---|
| 413 | 396 | return; |
|---|
| 414 | 397 | mlx5_fpga_conn_cqes(conn, MLX5_FPGA_CQ_BUDGET); |
|---|
| 415 | 398 | } |
|---|
| 416 | 399 | |
|---|
| 417 | | -static void mlx5_fpga_conn_cq_complete(struct mlx5_core_cq *mcq) |
|---|
| 400 | +static void mlx5_fpga_conn_cq_complete(struct mlx5_core_cq *mcq, |
|---|
| 401 | + struct mlx5_eqe *eqe) |
|---|
| 418 | 402 | { |
|---|
| 419 | 403 | struct mlx5_fpga_conn *conn; |
|---|
| 420 | 404 | |
|---|
| .. | .. |
|---|
| 429 | 413 | struct mlx5_fpga_device *fdev = conn->fdev; |
|---|
| 430 | 414 | struct mlx5_core_dev *mdev = fdev->mdev; |
|---|
| 431 | 415 | u32 temp_cqc[MLX5_ST_SZ_DW(cqc)] = {0}; |
|---|
| 416 | + u32 out[MLX5_ST_SZ_DW(create_cq_out)]; |
|---|
| 432 | 417 | struct mlx5_wq_param wqp; |
|---|
| 433 | 418 | struct mlx5_cqe64 *cqe; |
|---|
| 434 | 419 | int inlen, err, eqn; |
|---|
| 435 | | - unsigned int irqn; |
|---|
| 436 | 420 | void *cqc, *in; |
|---|
| 437 | 421 | __be64 *pas; |
|---|
| 438 | 422 | u32 i; |
|---|
| .. | .. |
|---|
| 461 | 445 | goto err_cqwq; |
|---|
| 462 | 446 | } |
|---|
| 463 | 447 | |
|---|
| 464 | | - err = mlx5_vector2eqn(mdev, smp_processor_id(), &eqn, &irqn); |
|---|
| 448 | + err = mlx5_vector2eqn(mdev, smp_processor_id(), &eqn); |
|---|
| 465 | 449 | if (err) { |
|---|
| 466 | 450 | kvfree(in); |
|---|
| 467 | 451 | goto err_cqwq; |
|---|
| .. | .. |
|---|
| 478 | 462 | pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas); |
|---|
| 479 | 463 | mlx5_fill_page_frag_array(&conn->cq.wq_ctrl.buf, pas); |
|---|
| 480 | 464 | |
|---|
| 481 | | - err = mlx5_core_create_cq(mdev, &conn->cq.mcq, in, inlen); |
|---|
| 465 | + err = mlx5_core_create_cq(mdev, &conn->cq.mcq, in, inlen, out, sizeof(out)); |
|---|
| 482 | 466 | kvfree(in); |
|---|
| 483 | 467 | |
|---|
| 484 | 468 | if (err) |
|---|
| .. | .. |
|---|
| 491 | 475 | *conn->cq.mcq.arm_db = 0; |
|---|
| 492 | 476 | conn->cq.mcq.vector = 0; |
|---|
| 493 | 477 | conn->cq.mcq.comp = mlx5_fpga_conn_cq_complete; |
|---|
| 494 | | - conn->cq.mcq.event = mlx5_fpga_conn_cq_event; |
|---|
| 495 | | - conn->cq.mcq.irqn = irqn; |
|---|
| 496 | 478 | conn->cq.mcq.uar = fdev->conn_res.uar; |
|---|
| 497 | | - tasklet_init(&conn->cq.tasklet, mlx5_fpga_conn_cq_tasklet, |
|---|
| 498 | | - (unsigned long)conn); |
|---|
| 479 | + tasklet_setup(&conn->cq.tasklet, mlx5_fpga_conn_cq_tasklet); |
|---|
| 499 | 480 | |
|---|
| 500 | 481 | mlx5_fpga_dbg(fdev, "Created CQ #0x%x\n", conn->cq.mcq.cqn); |
|---|
| 501 | 482 | |
|---|
| .. | .. |
|---|
| 532 | 513 | unsigned int tx_size, unsigned int rx_size) |
|---|
| 533 | 514 | { |
|---|
| 534 | 515 | struct mlx5_fpga_device *fdev = conn->fdev; |
|---|
| 516 | + u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; |
|---|
| 535 | 517 | struct mlx5_core_dev *mdev = fdev->mdev; |
|---|
| 536 | | - u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {0}; |
|---|
| 518 | + u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {}; |
|---|
| 537 | 519 | void *in = NULL, *qpc; |
|---|
| 538 | 520 | int err, inlen; |
|---|
| 539 | 521 | |
|---|
| .. | .. |
|---|
| 598 | 580 | mlx5_fill_page_frag_array(&conn->qp.wq_ctrl.buf, |
|---|
| 599 | 581 | (__be64 *)MLX5_ADDR_OF(create_qp_in, in, pas)); |
|---|
| 600 | 582 | |
|---|
| 601 | | - err = mlx5_core_create_qp(mdev, &conn->qp.mqp, in, inlen); |
|---|
| 583 | + MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP); |
|---|
| 584 | + err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); |
|---|
| 602 | 585 | if (err) |
|---|
| 603 | 586 | goto err_sq_bufs; |
|---|
| 604 | 587 | |
|---|
| 605 | | - conn->qp.mqp.event = mlx5_fpga_conn_event; |
|---|
| 606 | | - mlx5_fpga_dbg(fdev, "Created QP #0x%x\n", conn->qp.mqp.qpn); |
|---|
| 588 | + conn->qp.qpn = MLX5_GET(create_qp_out, out, qpn); |
|---|
| 589 | + mlx5_fpga_dbg(fdev, "Created QP #0x%x\n", conn->qp.qpn); |
|---|
| 607 | 590 | |
|---|
| 608 | 591 | goto out; |
|---|
| 609 | 592 | |
|---|
| .. | .. |
|---|
| 656 | 639 | |
|---|
| 657 | 640 | static void mlx5_fpga_conn_destroy_qp(struct mlx5_fpga_conn *conn) |
|---|
| 658 | 641 | { |
|---|
| 659 | | - mlx5_core_destroy_qp(conn->fdev->mdev, &conn->qp.mqp); |
|---|
| 642 | + struct mlx5_core_dev *dev = conn->fdev->mdev; |
|---|
| 643 | + u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; |
|---|
| 644 | + |
|---|
| 645 | + MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP); |
|---|
| 646 | + MLX5_SET(destroy_qp_in, in, qpn, conn->qp.qpn); |
|---|
| 647 | + mlx5_cmd_exec_in(dev, destroy_qp, in); |
|---|
| 648 | + |
|---|
| 660 | 649 | mlx5_fpga_conn_free_recv_bufs(conn); |
|---|
| 661 | 650 | mlx5_fpga_conn_flush_send_bufs(conn); |
|---|
| 662 | 651 | kvfree(conn->qp.sq.bufs); |
|---|
| .. | .. |
|---|
| 664 | 653 | mlx5_wq_destroy(&conn->qp.wq_ctrl); |
|---|
| 665 | 654 | } |
|---|
| 666 | 655 | |
|---|
| 667 | | -static inline int mlx5_fpga_conn_reset_qp(struct mlx5_fpga_conn *conn) |
|---|
| 656 | +static int mlx5_fpga_conn_reset_qp(struct mlx5_fpga_conn *conn) |
|---|
| 668 | 657 | { |
|---|
| 669 | 658 | struct mlx5_core_dev *mdev = conn->fdev->mdev; |
|---|
| 659 | + u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {}; |
|---|
| 670 | 660 | |
|---|
| 671 | | - mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to RST\n", conn->qp.mqp.qpn); |
|---|
| 661 | + mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to RST\n", conn->qp.qpn); |
|---|
| 672 | 662 | |
|---|
| 673 | | - return mlx5_core_qp_modify(mdev, MLX5_CMD_OP_2RST_QP, 0, NULL, |
|---|
| 674 | | - &conn->qp.mqp); |
|---|
| 663 | + MLX5_SET(qp_2rst_in, in, opcode, MLX5_CMD_OP_2RST_QP); |
|---|
| 664 | + MLX5_SET(qp_2rst_in, in, qpn, conn->qp.qpn); |
|---|
| 665 | + |
|---|
| 666 | + return mlx5_cmd_exec_in(mdev, qp_2rst, in); |
|---|
| 675 | 667 | } |
|---|
| 676 | 668 | |
|---|
| 677 | | -static inline int mlx5_fpga_conn_init_qp(struct mlx5_fpga_conn *conn) |
|---|
| 669 | +static int mlx5_fpga_conn_init_qp(struct mlx5_fpga_conn *conn) |
|---|
| 678 | 670 | { |
|---|
| 671 | + u32 in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {}; |
|---|
| 679 | 672 | struct mlx5_fpga_device *fdev = conn->fdev; |
|---|
| 680 | 673 | struct mlx5_core_dev *mdev = fdev->mdev; |
|---|
| 681 | | - u32 *qpc = NULL; |
|---|
| 682 | | - int err; |
|---|
| 674 | + u32 *qpc; |
|---|
| 683 | 675 | |
|---|
| 684 | | - mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to INIT\n", conn->qp.mqp.qpn); |
|---|
| 676 | + mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to INIT\n", conn->qp.qpn); |
|---|
| 685 | 677 | |
|---|
| 686 | | - qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); |
|---|
| 687 | | - if (!qpc) { |
|---|
| 688 | | - err = -ENOMEM; |
|---|
| 689 | | - goto out; |
|---|
| 690 | | - } |
|---|
| 678 | + qpc = MLX5_ADDR_OF(rst2init_qp_in, in, qpc); |
|---|
| 691 | 679 | |
|---|
| 692 | 680 | MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC); |
|---|
| 693 | 681 | MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED); |
|---|
| .. | .. |
|---|
| 698 | 686 | MLX5_SET(qpc, qpc, cqn_rcv, conn->cq.mcq.cqn); |
|---|
| 699 | 687 | MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma); |
|---|
| 700 | 688 | |
|---|
| 701 | | - err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_RST2INIT_QP, 0, qpc, |
|---|
| 702 | | - &conn->qp.mqp); |
|---|
| 703 | | - if (err) { |
|---|
| 704 | | - mlx5_fpga_warn(fdev, "qp_modify RST2INIT failed: %d\n", err); |
|---|
| 705 | | - goto out; |
|---|
| 706 | | - } |
|---|
| 689 | + MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP); |
|---|
| 690 | + MLX5_SET(rst2init_qp_in, in, qpn, conn->qp.qpn); |
|---|
| 707 | 691 | |
|---|
| 708 | | -out: |
|---|
| 709 | | - kfree(qpc); |
|---|
| 710 | | - return err; |
|---|
| 692 | + return mlx5_cmd_exec_in(mdev, rst2init_qp, in); |
|---|
| 711 | 693 | } |
|---|
| 712 | 694 | |
|---|
| 713 | | -static inline int mlx5_fpga_conn_rtr_qp(struct mlx5_fpga_conn *conn) |
|---|
| 695 | +static int mlx5_fpga_conn_rtr_qp(struct mlx5_fpga_conn *conn) |
|---|
| 714 | 696 | { |
|---|
| 697 | + u32 in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {}; |
|---|
| 715 | 698 | struct mlx5_fpga_device *fdev = conn->fdev; |
|---|
| 716 | 699 | struct mlx5_core_dev *mdev = fdev->mdev; |
|---|
| 717 | | - u32 *qpc = NULL; |
|---|
| 718 | | - int err; |
|---|
| 700 | + u32 *qpc; |
|---|
| 719 | 701 | |
|---|
| 720 | 702 | mlx5_fpga_dbg(conn->fdev, "QP RTR\n"); |
|---|
| 721 | 703 | |
|---|
| 722 | | - qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); |
|---|
| 723 | | - if (!qpc) { |
|---|
| 724 | | - err = -ENOMEM; |
|---|
| 725 | | - goto out; |
|---|
| 726 | | - } |
|---|
| 704 | + qpc = MLX5_ADDR_OF(init2rtr_qp_in, in, qpc); |
|---|
| 727 | 705 | |
|---|
| 728 | 706 | MLX5_SET(qpc, qpc, mtu, MLX5_QPC_MTU_1K_BYTES); |
|---|
| 729 | 707 | MLX5_SET(qpc, qpc, log_msg_max, (u8)MLX5_CAP_GEN(mdev, log_max_msg)); |
|---|
| .. | .. |
|---|
| 743 | 721 | MLX5_ADDR_OF(fpga_qpc, conn->fpga_qpc, fpga_ip), |
|---|
| 744 | 722 | MLX5_FLD_SZ_BYTES(qpc, primary_address_path.rgid_rip)); |
|---|
| 745 | 723 | |
|---|
| 746 | | - err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_INIT2RTR_QP, 0, qpc, |
|---|
| 747 | | - &conn->qp.mqp); |
|---|
| 748 | | - if (err) { |
|---|
| 749 | | - mlx5_fpga_warn(fdev, "qp_modify RST2INIT failed: %d\n", err); |
|---|
| 750 | | - goto out; |
|---|
| 751 | | - } |
|---|
| 724 | + MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP); |
|---|
| 725 | + MLX5_SET(init2rtr_qp_in, in, qpn, conn->qp.qpn); |
|---|
| 752 | 726 | |
|---|
| 753 | | -out: |
|---|
| 754 | | - kfree(qpc); |
|---|
| 755 | | - return err; |
|---|
| 727 | + return mlx5_cmd_exec_in(mdev, init2rtr_qp, in); |
|---|
| 756 | 728 | } |
|---|
| 757 | 729 | |
|---|
| 758 | | -static inline int mlx5_fpga_conn_rts_qp(struct mlx5_fpga_conn *conn) |
|---|
| 730 | +static int mlx5_fpga_conn_rts_qp(struct mlx5_fpga_conn *conn) |
|---|
| 759 | 731 | { |
|---|
| 760 | 732 | struct mlx5_fpga_device *fdev = conn->fdev; |
|---|
| 733 | + u32 in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {}; |
|---|
| 761 | 734 | struct mlx5_core_dev *mdev = fdev->mdev; |
|---|
| 762 | | - u32 *qpc = NULL; |
|---|
| 763 | | - u32 opt_mask; |
|---|
| 764 | | - int err; |
|---|
| 735 | + u32 *qpc; |
|---|
| 765 | 736 | |
|---|
| 766 | 737 | mlx5_fpga_dbg(conn->fdev, "QP RTS\n"); |
|---|
| 767 | 738 | |
|---|
| 768 | | - qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL); |
|---|
| 769 | | - if (!qpc) { |
|---|
| 770 | | - err = -ENOMEM; |
|---|
| 771 | | - goto out; |
|---|
| 772 | | - } |
|---|
| 739 | + qpc = MLX5_ADDR_OF(rtr2rts_qp_in, in, qpc); |
|---|
| 773 | 740 | |
|---|
| 774 | 741 | MLX5_SET(qpc, qpc, log_ack_req_freq, 8); |
|---|
| 775 | 742 | MLX5_SET(qpc, qpc, min_rnr_nak, 0x12); |
|---|
| .. | .. |
|---|
| 779 | 746 | MLX5_SET(qpc, qpc, retry_count, 7); |
|---|
| 780 | 747 | MLX5_SET(qpc, qpc, rnr_retry, 7); /* Infinite retry if RNR NACK */ |
|---|
| 781 | 748 | |
|---|
| 782 | | - opt_mask = MLX5_QP_OPTPAR_RNR_TIMEOUT; |
|---|
| 783 | | - err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_RTR2RTS_QP, opt_mask, qpc, |
|---|
| 784 | | - &conn->qp.mqp); |
|---|
| 785 | | - if (err) { |
|---|
| 786 | | - mlx5_fpga_warn(fdev, "qp_modify RST2INIT failed: %d\n", err); |
|---|
| 787 | | - goto out; |
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| 788 | | - } |
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| 749 | + MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP); |
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| 750 | + MLX5_SET(rtr2rts_qp_in, in, qpn, conn->qp.qpn); |
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| 751 | + MLX5_SET(rtr2rts_qp_in, in, opt_param_mask, MLX5_QP_OPTPAR_RNR_TIMEOUT); |
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| 789 | 752 | |
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| 790 | | -out: |
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| 791 | | - kfree(qpc); |
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| 792 | | - return err; |
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| 753 | + return mlx5_cmd_exec_in(mdev, rtr2rts_qp, in); |
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| 793 | 754 | } |
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| 794 | 755 | |
|---|
| 795 | 756 | static int mlx5_fpga_conn_connect(struct mlx5_fpga_conn *conn) |
|---|
| .. | .. |
|---|
| 869 | 830 | conn->cb_arg = attr->cb_arg; |
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| 870 | 831 | |
|---|
| 871 | 832 | remote_mac = MLX5_ADDR_OF(fpga_qpc, conn->fpga_qpc, remote_mac_47_32); |
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| 872 | | - err = mlx5_query_nic_vport_mac_address(fdev->mdev, 0, remote_mac); |
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| 833 | + err = mlx5_query_mac_address(fdev->mdev, remote_mac); |
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| 873 | 834 | if (err) { |
|---|
| 874 | 835 | mlx5_fpga_err(fdev, "Failed to query local MAC: %d\n", err); |
|---|
| 875 | 836 | ret = ERR_PTR(err); |
|---|
| .. | .. |
|---|
| 929 | 890 | MLX5_SET(fpga_qpc, conn->fpga_qpc, next_rcv_psn, 1); |
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| 930 | 891 | MLX5_SET(fpga_qpc, conn->fpga_qpc, next_send_psn, 0); |
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| 931 | 892 | MLX5_SET(fpga_qpc, conn->fpga_qpc, pkey, MLX5_FPGA_PKEY); |
|---|
| 932 | | - MLX5_SET(fpga_qpc, conn->fpga_qpc, remote_qpn, conn->qp.mqp.qpn); |
|---|
| 893 | + MLX5_SET(fpga_qpc, conn->fpga_qpc, remote_qpn, conn->qp.qpn); |
|---|
| 933 | 894 | MLX5_SET(fpga_qpc, conn->fpga_qpc, rnr_retry, 7); |
|---|
| 934 | 895 | MLX5_SET(fpga_qpc, conn->fpga_qpc, retry_count, 7); |
|---|
| 935 | 896 | |
|---|
| .. | .. |
|---|
| 970 | 931 | |
|---|
| 971 | 932 | void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn) |
|---|
| 972 | 933 | { |
|---|
| 973 | | - struct mlx5_fpga_device *fdev = conn->fdev; |
|---|
| 974 | | - struct mlx5_core_dev *mdev = fdev->mdev; |
|---|
| 975 | | - int err = 0; |
|---|
| 976 | | - |
|---|
| 977 | 934 | conn->qp.active = false; |
|---|
| 978 | 935 | tasklet_disable(&conn->cq.tasklet); |
|---|
| 979 | 936 | synchronize_irq(conn->cq.mcq.irqn); |
|---|
| 980 | 937 | |
|---|
| 981 | 938 | mlx5_fpga_destroy_qp(conn->fdev->mdev, conn->fpga_qpn); |
|---|
| 982 | | - err = mlx5_core_qp_modify(mdev, MLX5_CMD_OP_2ERR_QP, 0, NULL, |
|---|
| 983 | | - &conn->qp.mqp); |
|---|
| 984 | | - if (err) |
|---|
| 985 | | - mlx5_fpga_warn(fdev, "qp_modify 2ERR failed: %d\n", err); |
|---|
| 986 | 939 | mlx5_fpga_conn_destroy_qp(conn); |
|---|
| 987 | 940 | mlx5_fpga_conn_destroy_cq(conn); |
|---|
| 988 | 941 | |
|---|