AX88772C_eeprom and ax8872c build together

hc

2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb

 kernel/drivers/memory/tegra/tegra124.c
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@@ -1,9 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/of.h>
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@@ -12,48 +9,6 @@
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 #include <dt-bindings/memory/tegra124-mc.h>
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 #include "mc.h"
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-
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-#define MC_EMEM_ARB_CFG				0x90
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-#define MC_EMEM_ARB_OUTSTANDING_REQ		0x94
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-#define MC_EMEM_ARB_TIMING_RCD			0x98
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-#define MC_EMEM_ARB_TIMING_RP			0x9c
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-#define MC_EMEM_ARB_TIMING_RC			0xa0
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-#define MC_EMEM_ARB_TIMING_RAS			0xa4
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-#define MC_EMEM_ARB_TIMING_FAW			0xa8
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-#define MC_EMEM_ARB_TIMING_RRD			0xac
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-#define MC_EMEM_ARB_TIMING_RAP2PRE		0xb0
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-#define MC_EMEM_ARB_TIMING_WAP2PRE		0xb4
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-#define MC_EMEM_ARB_TIMING_R2R			0xb8
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-#define MC_EMEM_ARB_TIMING_W2W			0xbc
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-#define MC_EMEM_ARB_TIMING_R2W			0xc0
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-#define MC_EMEM_ARB_TIMING_W2R			0xc4
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-#define MC_EMEM_ARB_DA_TURNS			0xd0
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-#define MC_EMEM_ARB_DA_COVERS			0xd4
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-#define MC_EMEM_ARB_MISC0			0xd8
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-#define MC_EMEM_ARB_MISC1			0xdc
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-#define MC_EMEM_ARB_RING1_THROTTLE		0xe0
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-
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-static const unsigned long tegra124_mc_emem_regs[] = {
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-	MC_EMEM_ARB_CFG,
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-	MC_EMEM_ARB_OUTSTANDING_REQ,
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-	MC_EMEM_ARB_TIMING_RCD,
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-	MC_EMEM_ARB_TIMING_RP,
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-	MC_EMEM_ARB_TIMING_RC,
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-	MC_EMEM_ARB_TIMING_RAS,
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-	MC_EMEM_ARB_TIMING_FAW,
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-	MC_EMEM_ARB_TIMING_RRD,
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-	MC_EMEM_ARB_TIMING_RAP2PRE,
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-	MC_EMEM_ARB_TIMING_WAP2PRE,
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-	MC_EMEM_ARB_TIMING_R2R,
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-	MC_EMEM_ARB_TIMING_W2W,
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-	MC_EMEM_ARB_TIMING_R2W,
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-	MC_EMEM_ARB_TIMING_W2R,
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-	MC_EMEM_ARB_DA_TURNS,
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-	MC_EMEM_ARB_DA_COVERS,
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-	MC_EMEM_ARB_MISC0,
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-	MC_EMEM_ARB_MISC1,
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-	MC_EMEM_ARB_RING1_THROTTLE
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-};
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 static const struct tegra_mc_client tegra124_mc_clients[] = {
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 	{
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@@ -999,16 +954,17 @@
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 	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
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 };
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-static const unsigned int tegra124_group_display[] = {
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+static const unsigned int tegra124_group_drm[] = {
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 	TEGRA_SWGROUP_DC,
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 	TEGRA_SWGROUP_DCB,
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+	TEGRA_SWGROUP_VIC,
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 };
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 static const struct tegra_smmu_group_soc tegra124_groups[] = {
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 	{
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-		.name = "display",
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-		.swgroups = tegra124_group_display,
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-		.num_swgroups = ARRAY_SIZE(tegra124_group_display),
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+		.name = "drm",
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+		.swgroups = tegra124_group_drm,
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+		.num_swgroups = ARRAY_SIZE(tegra124_group_drm),
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 	},
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 };
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@@ -1049,6 +1005,28 @@
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 };
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 #ifdef CONFIG_ARCH_TEGRA_124_SOC
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+static const unsigned long tegra124_mc_emem_regs[] = {
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+	MC_EMEM_ARB_CFG,
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+	MC_EMEM_ARB_OUTSTANDING_REQ,
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+	MC_EMEM_ARB_TIMING_RCD,
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+	MC_EMEM_ARB_TIMING_RP,
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+	MC_EMEM_ARB_TIMING_RC,
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+	MC_EMEM_ARB_TIMING_RAS,
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+	MC_EMEM_ARB_TIMING_FAW,
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+	MC_EMEM_ARB_TIMING_RRD,
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+	MC_EMEM_ARB_TIMING_RAP2PRE,
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+	MC_EMEM_ARB_TIMING_WAP2PRE,
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+	MC_EMEM_ARB_TIMING_R2R,
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+	MC_EMEM_ARB_TIMING_W2W,
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+	MC_EMEM_ARB_TIMING_R2W,
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+	MC_EMEM_ARB_TIMING_W2R,
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+	MC_EMEM_ARB_DA_TURNS,
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+	MC_EMEM_ARB_DA_COVERS,
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+	MC_EMEM_ARB_MISC0,
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+	MC_EMEM_ARB_MISC1,
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+	MC_EMEM_ARB_RING1_THROTTLE
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+};
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+
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 static const struct tegra_smmu_soc tegra124_smmu_soc = {
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 	.clients = tegra124_mc_clients,
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 	.num_clients = ARRAY_SIZE(tegra124_mc_clients),
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@@ -1074,7 +1052,7 @@
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 	.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
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 		   MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
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 		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
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-	.reset_ops = &terga_mc_reset_ops_common,
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+	.reset_ops = &tegra_mc_reset_ops_common,
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 	.resets = tegra124_mc_resets,
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 	.num_resets = ARRAY_SIZE(tegra124_mc_resets),
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 };
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@@ -1104,7 +1082,7 @@
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 	.intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
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 		   MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
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 		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
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-	.reset_ops = &terga_mc_reset_ops_common,
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+	.reset_ops = &tegra_mc_reset_ops_common,
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 	.resets = tegra124_mc_resets,
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 	.num_resets = ARRAY_SIZE(tegra124_mc_resets),
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 };