AX88772C_eeprom and ax8872c build together

hc

2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb

 kernel/drivers/gpio/gpio-merrifield.c
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@@ -1,18 +1,14 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * Intel Merrifield SoC GPIO driver
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  *
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  * Copyright (c) 2016 Intel Corporation.
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  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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8
 
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 #include <linux/acpi.h>
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 #include <linux/bitops.h>
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 #include <linux/gpio/driver.h>
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-#include <linux/init.h>
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 #include <linux/interrupt.h>
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 #include <linux/io.h>
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14
 #include <linux/module.h>
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@@ -166,7 +162,10 @@
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 {
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 	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
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-	return !(readl(gpdr) & BIT(offset % 32));
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+	if (readl(gpdr) & BIT(offset % 32))
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+		return GPIO_LINE_DIRECTION_OUT;
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+
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+	return GPIO_LINE_DIRECTION_IN;
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 }
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170
 
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 static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
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@@ -366,8 +365,9 @@
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 	chained_irq_exit(irqchip, desc);
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 }
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367
 
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-static void mrfld_irq_init_hw(struct mrfld_gpio *priv)
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+static int mrfld_irq_init_hw(struct gpio_chip *chip)
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 {
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+	struct mrfld_gpio *priv = gpiochip_get_data(chip);
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 	void __iomem *reg;
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 	unsigned int base;
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373
 
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@@ -379,22 +379,56 @@
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 		reg = gpio_reg(&priv->chip, base, GFER);
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 		writel(0, reg);
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 	}
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+
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+	return 0;
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 }
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-static const char *mrfld_gpio_get_pinctrl_dev_name(void)
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+static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv)
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 {
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-	const char *dev_name = acpi_dev_get_first_match_name("INTC1002", NULL, -1);
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-	return dev_name ? dev_name : "pinctrl-merrifield";
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+	struct acpi_device *adev;
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+	const char *name;
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+
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+	adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1);
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+	if (adev) {
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+		name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL);
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+		acpi_dev_put(adev);
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+	} else {
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+		name = "pinctrl-merrifield";
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+	}
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+
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+	return name;
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+}
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+
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+static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip)
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+{
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+	struct mrfld_gpio *priv = gpiochip_get_data(chip);
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+	const struct mrfld_gpio_pinrange *range;
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+	const char *pinctrl_dev_name;
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+	unsigned int i;
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+	int retval;
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+
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+	pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv);
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+	for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
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+		range = &mrfld_gpio_ranges[i];
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+		retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name,
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+						range->gpio_base,
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+						range->pin_base,
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+						range->npins);
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+		if (retval) {
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+			dev_err(priv->dev, "failed to add GPIO pin range\n");
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+			return retval;
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+		}
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+	}
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+
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+	return 0;
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 }
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 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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 {
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-	const struct mrfld_gpio_pinrange *range;
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-	const char *pinctrl_dev_name;
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+	struct gpio_irq_chip *girq;
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 	struct mrfld_gpio *priv;
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 	u32 gpio_base, irq_base;
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 	void __iomem *base;
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-	unsigned int i;
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 	int retval;
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433
 
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 	retval = pcim_enable_device(pdev);
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@@ -409,8 +443,8 @@
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443
 
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 	base = pcim_iomap_table(pdev)[1];
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-	irq_base = readl(base);
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-	gpio_base = readl(sizeof(u32) + base);
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+	irq_base = readl(base + 0 * sizeof(u32));
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+	gpio_base = readl(base + 1 * sizeof(u32));
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448
 
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 	/* Release the IO mapping, since we already get the info from BAR1 */
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 	pcim_iounmap_regions(pdev, BIT(1));
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@@ -435,42 +469,35 @@
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 	priv->chip.base = gpio_base;
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 	priv->chip.ngpio = MRFLD_NGPIO;
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 	priv->chip.can_sleep = false;
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+	priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges;
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473
 
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 	raw_spin_lock_init(&priv->lock);
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-	pci_set_drvdata(pdev, priv);
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+	retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
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+	if (retval < 0)
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+		return retval;
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+
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+	girq = &priv->chip.irq;
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+	girq->chip = &mrfld_irqchip;
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+	girq->init_hw = mrfld_irq_init_hw;
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+	girq->parent_handler = mrfld_irq_handler;
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+	girq->num_parents = 1;
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+	girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
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+				     sizeof(*girq->parents), GFP_KERNEL);
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+	if (!girq->parents)
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+		return -ENOMEM;
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+	girq->parents[0] = pci_irq_vector(pdev, 0);
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+	girq->first = irq_base;
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+	girq->default_type = IRQ_TYPE_NONE;
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+	girq->handler = handle_bad_irq;
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+
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 	retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
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 	if (retval) {
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 		dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
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 		return retval;
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 	}
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-	pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name();
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-	for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) {
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-		range = &mrfld_gpio_ranges[i];
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-		retval = gpiochip_add_pin_range(&priv->chip,
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-						pinctrl_dev_name,
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-						range->gpio_base,
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-						range->pin_base,
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-						range->npins);
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-		if (retval) {
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-			dev_err(&pdev->dev, "failed to add GPIO pin range\n");
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-			return retval;
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-		}
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-	}
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-
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-	retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base,
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-				      handle_bad_irq, IRQ_TYPE_NONE);
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-	if (retval) {
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-		dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n");
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-		return retval;
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-	}
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-
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-	mrfld_irq_init_hw(priv);
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-
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-	gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq,
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-				     mrfld_irq_handler);
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-
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+	pci_set_drvdata(pdev, priv);
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 	return 0;
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 }
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