AX88772C_eeprom and ax8872c build together

hc

2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb

 kernel/arch/mips/kernel/branch.c
..
..
@@ -20,6 +20,8 @@
20
20
 #include <asm/ptrace.h>
21
21
 #include <linux/uaccess.h>
22
22
 
23
+#include "probes-common.h"
24
+
23
25
 /*
24
26
  * Calculate and return exception PC in case of branch delay slot
25
27
  * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
..
..
@@ -32,7 +34,7 @@
32
34
 	/* Calculate exception PC in branch delay slot. */
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35
 	if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
34
36
 		/* This should never happen because delay slot was checked. */
35
-		force_sig(SIGSEGV, current);
37
+		force_sig(SIGSEGV);
36
38
 		return epc;
37
39
 	}
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40
 	if (cpu_has_mips16) {
..
..
@@ -58,9 +60,7 @@
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60
 		       unsigned long *contpc)
59
61
 {
60
62
 	union mips_instruction insn = (union mips_instruction)dec_insn.insn;
61
-	int bc_false = 0;
62
-	unsigned int fcr31;
63
-	unsigned int bit;
63
+	int __maybe_unused bc_false = 0;
64
64
 
65
65
 	if (!cpu_has_mmips)
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66
 		return 0;
..
..
@@ -92,7 +92,7 @@
92
92
 			regs->regs[31] = regs->cp0_epc +
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93
 				dec_insn.pc_inc +
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94
 				dec_insn.next_pc_inc;
95
-			/* Fall through */
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+			fallthrough;
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96
 		case mm_bltz_op:
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97
 			if ((long)regs->regs[insn.mm_i_format.rs] < 0)
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98
 				*contpc = regs->cp0_epc +
..
..
@@ -108,7 +108,7 @@
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108
 			regs->regs[31] = regs->cp0_epc +
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 					dec_insn.pc_inc +
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110
 					dec_insn.next_pc_inc;
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-			/* Fall through */
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+			fallthrough;
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112
 		case mm_bgez_op:
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113
 			if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
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114
 				*contpc = regs->cp0_epc +
..
..
@@ -139,10 +139,14 @@
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 					dec_insn.pc_inc +
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 					dec_insn.next_pc_inc;
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 			return 1;
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+#ifdef CONFIG_MIPS_FP_SUPPORT
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 		case mm_bc2f_op:
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-		case mm_bc1f_op:
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+		case mm_bc1f_op: {
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+			unsigned int fcr31;
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+			unsigned int bit;
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+
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 			bc_false = 1;
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-			/* Fall through */
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+			fallthrough;
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 		case mm_bc2t_op:
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151
 		case mm_bc1t_op:
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 			preempt_disable();
..
..
@@ -167,6 +171,8 @@
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 					dec_insn.pc_inc + dec_insn.next_pc_inc;
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 			return 1;
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173
 		}
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+#endif /* CONFIG_MIPS_FP_SUPPORT */
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+		}
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176
 		break;
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177
 	case mm_pool16c_op:
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178
 		switch (insn.mm_i_format.rt) {
..
..
@@ -174,7 +180,7 @@
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180
 		case mm_jalrs16_op:
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181
 			regs->regs[31] = regs->cp0_epc +
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182
 				dec_insn.pc_inc + dec_insn.next_pc_inc;
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-			/* Fall through */
183
+			fallthrough;
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184
 		case mm_jr16_op:
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185
 			*contpc = regs->regs[insn.mm_i_format.rs];
180
186
 			return 1;
..
..
@@ -235,7 +241,7 @@
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241
 	case mm_jal32_op:
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 		regs->regs[31] = regs->cp0_epc +
237
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 			dec_insn.pc_inc + dec_insn.next_pc_inc;
238
-		/* Fall through */
244
+		fallthrough;
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245
 	case mm_j32_op:
240
246
 		*contpc = regs->cp0_epc + dec_insn.pc_inc;
241
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 		*contpc >>= 27;
..
..
@@ -301,7 +307,7 @@
301
307
 	return 0;
302
308
 
303
309
 sigsegv:
304
-	force_sig(SIGSEGV, current);
310
+	force_sig(SIGSEGV);
305
311
 	return -EFAULT;
306
312
 }
307
313
 
..
..
@@ -324,7 +330,7 @@
324
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 	/* Read the instruction. */
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331
 	addr = (u16 __user *)msk_isa16_mode(epc);
326
332
 	if (__get_user(inst.full, addr)) {
327
-		force_sig(SIGSEGV, current);
333
+		force_sig(SIGSEGV);
328
334
 		return -EFAULT;
329
335
 	}
330
336
 
..
..
@@ -339,7 +345,7 @@
339
345
 	case MIPS16e_jal_op:
340
346
 		addr += 1;
341
347
 		if (__get_user(inst2, addr)) {
342
-			force_sig(SIGSEGV, current);
348
+			force_sig(SIGSEGV);
343
349
 			return -EFAULT;
344
350
 		}
345
351
 		fullinst = ((unsigned)inst.full << 16) | inst2;
..
..
@@ -416,8 +422,8 @@
416
422
 int __compute_return_epc_for_insn(struct pt_regs *regs,
417
423
 				   union mips_instruction insn)
418
424
 {
419
-	unsigned int bit, fcr31, dspcontrol, reg;
420
425
 	long epc = regs->cp0_epc;
426
+	unsigned int dspcontrol;
421
427
 	int ret = 0;
422
428
 
423
429
 	switch (insn.i_format.opcode) {
..
..
@@ -428,7 +434,7 @@
428
434
 		switch (insn.r_format.func) {
429
435
 		case jalr_op:
430
436
 			regs->regs[insn.r_format.rd] = epc + 8;
431
-			/* Fall through */
437
+			fallthrough;
432
438
 		case jr_op:
433
439
 			if (NO_R6EMU && insn.r_format.func == jr_op)
434
440
 				goto sigill_r2r6;
..
..
@@ -447,6 +453,7 @@
447
453
 		case bltzl_op:
448
454
 			if (NO_R6EMU)
449
455
 				goto sigill_r2r6;
456
+			fallthrough;
450
457
 		case bltz_op:
451
458
 			if ((long)regs->regs[insn.i_format.rs] < 0) {
452
459
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
..
..
@@ -460,6 +467,7 @@
460
467
 		case bgezl_op:
461
468
 			if (NO_R6EMU)
462
469
 				goto sigill_r2r6;
470
+			fallthrough;
463
471
 		case bgez_op:
464
472
 			if ((long)regs->regs[insn.i_format.rs] >= 0) {
465
473
 				epc = epc + 4 + (insn.i_format.simmediate << 2);
..
..
@@ -555,6 +563,7 @@
555
563
 	case jalx_op:
556
564
 	case jal_op:
557
565
 		regs->regs[31] = regs->cp0_epc + 8;
566
+		fallthrough;
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567
 	case j_op:
559
568
 		epc += 4;
560
569
 		epc >>= 28;
..
..
@@ -571,6 +580,7 @@
571
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 	case beql_op:
572
581
 		if (NO_R6EMU)
573
582
 			goto sigill_r2r6;
583
+		fallthrough;
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584
 	case beq_op:
575
585
 		if (regs->regs[insn.i_format.rs] ==
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586
 		    regs->regs[insn.i_format.rt]) {
..
..
@@ -585,6 +595,7 @@
585
595
 	case bnel_op:
586
596
 		if (NO_R6EMU)
587
597
 			goto sigill_r2r6;
598
+		fallthrough;
588
599
 	case bne_op:
589
600
 		if (regs->regs[insn.i_format.rs] !=
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601
 		    regs->regs[insn.i_format.rt]) {
..
..
@@ -599,6 +610,7 @@
599
610
 	case blezl_op: /* not really i_format */
600
611
 		if (!insn.i_format.rt && NO_R6EMU)
601
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 			goto sigill_r2r6;
613
+		fallthrough;
602
614
 	case blez_op:
603
615
 		/*
604
616
 		 * Compact branches for R6 for the
..
..
@@ -634,6 +646,7 @@
634
646
 	case bgtzl_op:
635
647
 		if (!insn.i_format.rt && NO_R6EMU)
636
648
 			goto sigill_r2r6;
649
+		fallthrough;
637
650
 	case bgtz_op:
638
651
 		/*
639
652
 		 * Compact branches for R6 for the
..
..
@@ -667,23 +680,18 @@
667
680
 		regs->cp0_epc = epc;
668
681
 		break;
669
682
 
683
+#ifdef CONFIG_MIPS_FP_SUPPORT
670
684
 	/*
671
685
 	 * And now the FPA/cp1 branch instructions.
672
686
 	 */
673
-	case cop1_op:
687
+	case cop1_op: {
688
+		unsigned int bit, fcr31, reg;
689
+
674
690
 		if (cpu_has_mips_r6 &&
675
691
 		    ((insn.i_format.rs == bc1eqz_op) ||
676
692
 		     (insn.i_format.rs == bc1nez_op))) {
677
-			if (!used_math()) { /* First time FPU user */
678
-				ret = init_fpu();
679
-				if (ret && NO_R6EMU) {
680
-					ret = -ret;
681
-					break;
682
-				}
683
-				ret = 0;
684
-				set_used_math();
685
-			}
686
-			lose_fpu(1);    /* Save FPU state for the emulator. */
693
+			if (!init_fp_ctx(current))
694
+				lose_fpu(1);
687
695
 			reg = insn.i_format.rt;
688
696
 			bit = get_fpr32(&current->thread.fpu.fpr[reg], 0) & 0x1;
689
697
 			if (insn.i_format.rs == bc1eqz_op)
..
..
@@ -736,6 +744,9 @@
736
744
 			}
737
745
 			break;
738
746
 		}
747
+	}
748
+#endif /* CONFIG_MIPS_FP_SUPPORT */
749
+
739
750
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
740
751
 	case lwc2_op: /* This is bbit0 on Octeon */
741
752
 		if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
..
..
@@ -820,17 +831,17 @@
820
831
 sigill_dsp:
821
832
 	pr_debug("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
822
833
 		 current->comm);
823
-	force_sig(SIGILL, current);
834
+	force_sig(SIGILL);
824
835
 	return -EFAULT;
825
836
 sigill_r2r6:
826
837
 	pr_debug("%s: R2 branch but r2-to-r6 emulator is not present - sending SIGILL.\n",
827
838
 		 current->comm);
828
-	force_sig(SIGILL, current);
839
+	force_sig(SIGILL);
829
840
 	return -EFAULT;
830
841
 sigill_r6:
831
842
 	pr_debug("%s: R6 branch but no MIPSr6 ISA support - sending SIGILL.\n",
832
843
 		 current->comm);
833
-	force_sig(SIGILL, current);
844
+	force_sig(SIGILL);
834
845
 	return -EFAULT;
835
846
 }
836
847
 EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
..
..
@@ -850,7 +861,7 @@
850
861
 	 */
851
862
 	addr = (unsigned int __user *) epc;
852
863
 	if (__get_user(insn.word, addr)) {
853
-		force_sig(SIGSEGV, current);
864
+		force_sig(SIGSEGV);
854
865
 		return -EFAULT;
855
866
 	}
856
867
 
..
..
@@ -858,7 +869,7 @@
858
869
 
859
870
 unaligned:
860
871
 	printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
861
-	force_sig(SIGBUS, current);
872
+	force_sig(SIGBUS);
862
873
 	return -EFAULT;
863
874
 }
864
875