AX88772C_eeprom and ax8872c build together

hc

2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb

 kernel/arch/mips/include/asm/pgtable-bits.h
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@@ -52,6 +52,12 @@
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 	_PAGE_WRITE_SHIFT,
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 	_PAGE_ACCESSED_SHIFT,
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 	_PAGE_MODIFIED_SHIFT,
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+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
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+	_PAGE_SPECIAL_SHIFT,
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+#endif
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+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
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+	_PAGE_SOFT_DIRTY_SHIFT,
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+#endif
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 };
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 /*
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@@ -78,9 +84,15 @@
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 	_PAGE_WRITE_SHIFT,
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 	_PAGE_ACCESSED_SHIFT,
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 	_PAGE_MODIFIED_SHIFT,
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+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
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+	_PAGE_SPECIAL_SHIFT,
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+#endif
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+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
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+	_PAGE_SOFT_DIRTY_SHIFT,
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+#endif
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 };
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-#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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+#elif defined(CONFIG_CPU_R3K_TLB)
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 /* Page table bits used for r3k systems */
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 enum pgtable_bits {
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@@ -90,6 +102,12 @@
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 	_PAGE_WRITE_SHIFT,
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 	_PAGE_ACCESSED_SHIFT,
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 	_PAGE_MODIFIED_SHIFT,
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+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
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+	_PAGE_SPECIAL_SHIFT,
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+#endif
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+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
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+	_PAGE_SOFT_DIRTY_SHIFT,
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+#endif
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 	/* Used by TLB hardware (placed in EntryLo) */
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 	_PAGE_GLOBAL_SHIFT = 8,
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@@ -110,10 +128,15 @@
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 	_PAGE_WRITE_SHIFT,
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 	_PAGE_ACCESSED_SHIFT,
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 	_PAGE_MODIFIED_SHIFT,
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-#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
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+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
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 	_PAGE_HUGE_SHIFT,
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 #endif
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-
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+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
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+	_PAGE_SPECIAL_SHIFT,
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+#endif
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+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
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+	_PAGE_SOFT_DIRTY_SHIFT,
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+#endif
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 	/* Used by TLB hardware (placed in EntryLo*) */
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 #if defined(CONFIG_CPU_HAS_RIXI)
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 	_PAGE_NO_EXEC_SHIFT,
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@@ -132,8 +155,18 @@
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 #define _PAGE_WRITE		(1 << _PAGE_WRITE_SHIFT)
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 #define _PAGE_ACCESSED		(1 << _PAGE_ACCESSED_SHIFT)
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 #define _PAGE_MODIFIED		(1 << _PAGE_MODIFIED_SHIFT)
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-#if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
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+#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
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 # define _PAGE_HUGE		(1 << _PAGE_HUGE_SHIFT)
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+#endif
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+#if defined(CONFIG_ARCH_HAS_PTE_SPECIAL)
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+# define _PAGE_SPECIAL		(1 << _PAGE_SPECIAL_SHIFT)
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+#else
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+# define _PAGE_SPECIAL		0
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+#endif
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+#if defined(CONFIG_HAVE_ARCH_SOFT_DIRTY)
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+# define _PAGE_SOFT_DIRTY	(1 << _PAGE_SOFT_DIRTY_SHIFT)
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+#else
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+# define _PAGE_SOFT_DIRTY	0
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 #endif
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 /* Used by TLB hardware (placed in EntryLo*) */
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@@ -146,7 +179,7 @@
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 #define _PAGE_GLOBAL		(1 << _PAGE_GLOBAL_SHIFT)
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 #define _PAGE_VALID		(1 << _PAGE_VALID_SHIFT)
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 #define _PAGE_DIRTY		(1 << _PAGE_DIRTY_SHIFT)
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-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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+#if defined(CONFIG_CPU_R3K_TLB)
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 # define _CACHE_UNCACHED	(1 << _CACHE_UNCACHED_SHIFT)
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 # define _CACHE_MASK		_CACHE_UNCACHED
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 # define _PFN_SHIFT		PAGE_SHIFT
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@@ -204,7 +237,7 @@
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 /*
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  * Cache attributes
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  */
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-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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+#if defined(CONFIG_CPU_R3K_TLB)
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 #define _CACHE_CACHABLE_NONCOHERENT 0
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 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
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@@ -215,18 +248,6 @@
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    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
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 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
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-
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-#elif defined(CONFIG_CPU_LOONGSON3)
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-
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-/* Using COHERENT flag for NONCOHERENT doesn't hurt. */
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-
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-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* LOONGSON       */
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-#define _CACHE_CACHABLE_COHERENT    (3<<_CACHE_SHIFT)  /* LOONGSON-3     */
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-
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-#elif defined(CONFIG_MACH_INGENIC)
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-
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-/* Ingenic uses the WA bit to achieve write-combine memory writes */
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-#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
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 #endif
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@@ -259,6 +280,6 @@
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 #define __WRITEABLE	(_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
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 #define _PAGE_CHG_MASK	(_PAGE_ACCESSED | _PAGE_MODIFIED |	\
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-			 _PFN_MASK | _CACHE_MASK)
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+			 _PAGE_SOFT_DIRTY | _PFN_MASK | _CACHE_MASK)
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 #endif /* _ASM_PGTABLE_BITS_H */