AX88772C_eeprom and ax8872c build together

hc

2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb

 kernel/arch/arm64/include/asm/pgtable-prot.h
..
..
@@ -1,17 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
1
2
 /*
2
3
  * Copyright (C) 2016 ARM Ltd.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15
4
  */
16
5
 #ifndef __ASM_PGTABLE_PROT_H
17
6
 #define __ASM_PGTABLE_PROT_H
..
..
@@ -24,21 +13,41 @@
24
13
 /*
25
14
  * Software defined PTE bits definition.
26
15
  */
27
-#define PTE_VALID		(_AT(pteval_t, 1) << 0)
28
16
 #define PTE_WRITE		(PTE_DBM)		 /* same as DBM (51) */
29
17
 #define PTE_DIRTY		(_AT(pteval_t, 1) << 55)
30
18
 #define PTE_SPECIAL		(_AT(pteval_t, 1) << 56)
19
+#define PTE_DEVMAP		(_AT(pteval_t, 1) << 57)
31
20
 #define PTE_PROT_NONE		(_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
21
+
22
+/*
23
+ * This bit indicates that the entry is present i.e. pmd_page()
24
+ * still points to a valid huge page in memory even if the pmd
25
+ * has been invalidated.
26
+ */
27
+#define PMD_PRESENT_INVALID	(_AT(pteval_t, 1) << 59) /* only when !PMD_SECT_VALID */
32
28
 
33
29
 #ifndef __ASSEMBLY__
34
30
 
31
+#include <asm/cpufeature.h>
35
32
 #include <asm/pgtable-types.h>
33
+
34
+extern bool arm64_use_ng_mappings;
36
35
 
37
36
 #define _PROT_DEFAULT		(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
38
37
 #define _PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
39
38
 
40
-#define PTE_MAYBE_NG		(arm64_kernel_unmapped_at_el0() ? PTE_NG : 0)
41
-#define PMD_MAYBE_NG		(arm64_kernel_unmapped_at_el0() ? PMD_SECT_NG : 0)
39
+#define PTE_MAYBE_NG		(arm64_use_ng_mappings ? PTE_NG : 0)
40
+#define PMD_MAYBE_NG		(arm64_use_ng_mappings ? PMD_SECT_NG : 0)
41
+
42
+/*
43
+ * If we have userspace only BTI we don't want to mark kernel pages
44
+ * guarded even if the system does support BTI.
45
+ */
46
+#ifdef CONFIG_ARM64_BTI_KERNEL
47
+#define PTE_MAYBE_GP		(system_supports_bti() ? PTE_GP : 0)
48
+#else
49
+#define PTE_MAYBE_GP		0
50
+#endif
42
51
 
43
52
 #define PROT_DEFAULT		(_PROT_DEFAULT | PTE_MAYBE_NG)
44
53
 #define PROT_SECT_DEFAULT	(_PROT_SECT_DEFAULT | PMD_MAYBE_NG)
..
..
@@ -48,13 +57,13 @@
48
57
 #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
49
58
 #define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
50
59
 #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
60
+#define PROT_NORMAL_TAGGED	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_TAGGED))
51
61
 
52
62
 #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
53
63
 #define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
54
64
 #define PROT_SECT_NORMAL_EXEC	(PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
55
65
 
56
66
 #define _PAGE_DEFAULT		(_PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
57
-#define _HYP_PAGE_DEFAULT	_PAGE_DEFAULT
58
67
 
59
68
 #define PAGE_KERNEL		__pgprot(PROT_NORMAL)
60
69
 #define PAGE_KERNEL_RO		__pgprot((PROT_NORMAL & ~PTE_WRITE) | PTE_RDONLY)
..
..
@@ -62,33 +71,15 @@
62
71
 #define PAGE_KERNEL_EXEC	__pgprot(PROT_NORMAL & ~PTE_PXN)
63
72
 #define PAGE_KERNEL_EXEC_CONT	__pgprot((PROT_NORMAL & ~PTE_PXN) | PTE_CONT)
64
73
 
65
-#define PAGE_HYP		__pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_HYP_XN)
66
-#define PAGE_HYP_EXEC		__pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY)
67
-#define PAGE_HYP_RO		__pgprot(_HYP_PAGE_DEFAULT | PTE_HYP | PTE_RDONLY | PTE_HYP_XN)
68
-#define PAGE_HYP_DEVICE		__pgprot(_PROT_DEFAULT | PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_HYP | PTE_HYP_XN)
69
-
70
-#define PAGE_S2_MEMATTR(attr)						\
74
+#define PAGE_S2_MEMATTR(attr, has_fwb)					\
71
75
 	({								\
72
76
 		u64 __val;						\
73
-		if (cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))		\
77
+		if (has_fwb)						\
74
78
 			__val = PTE_S2_MEMATTR(MT_S2_FWB_ ## attr);	\
75
79
 		else							\
76
80
 			__val = PTE_S2_MEMATTR(MT_S2_ ## attr);		\
77
81
 		__val;							\
78
82
 	 })
79
-
80
-#define PAGE_S2_XN							\
81
-	({								\
82
-		u64 __val;						\
83
-		if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))		\
84
-			__val = 0;					\
85
-		else							\
86
-			__val = PTE_S2_XN;				\
87
-		__val;							\
88
-	})
89
-
90
-#define PAGE_S2			__pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)
91
-#define PAGE_S2_DEVICE		__pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PAGE_S2_XN)
92
83
 
93
84
 #define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
94
85
 /* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */