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2024-05-16 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb 
 kernel/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
....@@ -1,13 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
34  *
45  * Copyright (C) 2009-2011 Nokia Corporation
56  * Copyright (C) 2012 Texas Instruments, Inc.
67  * Paul Walmsley
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
118  *
129  * The data in this file should be completely autogeneratable from
1310  * the TI hardware database or other technical documentation.
....@@ -19,7 +16,6 @@
1916 #include <linux/power/smartreflex.h>
2017 #include <linux/platform_data/hsmmc-omap.h>
2118 
22
-#include <linux/omap-dma.h>
2319 #include "l3_3xxx.h"
2420 #include "l4_3xxx.h"
2521 
....@@ -151,36 +147,6 @@
151147 	.sysc = &omap3xxx_timer_sysc,
152148 };
153149 
154
-/* timer1 */
155
-static struct omap_hwmod omap3xxx_timer1_hwmod = {
156
-	.name		= "timer1",
157
-	.main_clk	= "gpt1_fck",
158
-	.prcm		= {
159
-		.omap2 = {
160
-			.module_offs = WKUP_MOD,
161
-			.idlest_reg_id = 1,
162
-			.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
163
-		},
164
-	},
165
-	.class		= &omap3xxx_timer_hwmod_class,
166
-	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
167
-};
168
-
169
-/* timer2 */
170
-static struct omap_hwmod omap3xxx_timer2_hwmod = {
171
-	.name		= "timer2",
172
-	.main_clk	= "gpt2_fck",
173
-	.prcm		= {
174
-		.omap2 = {
175
-			.module_offs = OMAP3430_PER_MOD,
176
-			.idlest_reg_id = 1,
177
-			.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
178
-		},
179
-	},
180
-	.class		= &omap3xxx_timer_hwmod_class,
181
-	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
182
-};
183
-
184150 /* timer3 */
185151 static struct omap_hwmod omap3xxx_timer3_hwmod = {
186152 	.name		= "timer3",
....@@ -310,21 +276,6 @@
310276 			.module_offs = CORE_MOD,
311277 			.idlest_reg_id = 1,
312278 			.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
313
-		},
314
-	},
315
-	.class		= &omap3xxx_timer_hwmod_class,
316
-	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
317
-};
318
-
319
-/* timer12 */
320
-static struct omap_hwmod omap3xxx_timer12_hwmod = {
321
-	.name		= "timer12",
322
-	.main_clk	= "gpt12_fck",
323
-	.prcm		= {
324
-		.omap2 = {
325
-			.module_offs = WKUP_MOD,
326
-			.idlest_reg_id = 1,
327
-			.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
328279 		},
329280 	},
330281 	.class		= &omap3xxx_timer_hwmod_class,
....@@ -484,7 +435,6 @@
484435 static struct omap_hwmod_class i2c_class = {
485436 	.name	= "i2c",
486437 	.sysc	= &i2c_sysc,
487
-	.rev	= OMAP_I2C_IP_VERSION_1,
488438 	.reset	= &omap_i2c_reset,
489439 };
490440 
....@@ -707,7 +657,6 @@
707657 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
708658 	.name = "gpio",
709659 	.sysc = &omap3xxx_gpio_sysc,
710
-	.rev = 1,
711660 };
712661 
713662 /* gpio1 */
....@@ -836,47 +785,6 @@
836785 		},
837786 	},
838787 	.class		= &omap3xxx_gpio_hwmod_class,
839
-};
840
-
841
-/* dma attributes */
842
-static struct omap_dma_dev_attr dma_dev_attr = {
843
-	.dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
844
-				IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
845
-	.lch_count = 32,
846
-};
847
-
848
-static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
849
-	.rev_offs	= 0x0000,
850
-	.sysc_offs	= 0x002c,
851
-	.syss_offs	= 0x0028,
852
-	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
853
-			   SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
854
-			   SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
855
-			   SYSS_HAS_RESET_STATUS),
856
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
857
-			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
858
-	.sysc_fields	= &omap_hwmod_sysc_type1,
859
-};
860
-
861
-static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
862
-	.name = "dma",
863
-	.sysc = &omap3xxx_dma_sysc,
864
-};
865
-
866
-/* dma_system */
867
-static struct omap_hwmod omap3xxx_dma_system_hwmod = {
868
-	.name		= "dma",
869
-	.class		= &omap3xxx_dma_hwmod_class,
870
-	.main_clk	= "core_l3_ick",
871
-	.prcm = {
872
-		.omap2 = {
873
-			.module_offs		= CORE_MOD,
874
-			.idlest_reg_id		= 1,
875
-			.idlest_idle_bit	= OMAP3430_ST_SDMA_SHIFT,
876
-		},
877
-	},
878
-	.dev_attr	= &dma_dev_attr,
879
-	.flags		= HWMOD_NO_IDLEST,
880788 };
881789 
882790 /*
....@@ -1029,7 +937,6 @@
1029937 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1030938 	.name = "smartreflex",
1031939 	.sysc = &omap34xx_sr_sysc,
1032
-	.rev  = 1,
1033940 };
1034941 
1035942 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
....@@ -1044,7 +951,6 @@
1044951 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1045952 	.name = "smartreflex",
1046953 	.sysc = &omap36xx_sr_sysc,
1047
-	.rev  = 2,
1048954 };
1049955 
1050956 /* SR1 */
....@@ -1574,38 +1480,6 @@
15741480 };
15751481 
15761482 /*
1577
- * '32K sync counter' class
1578
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1579
- */
1580
-static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1581
-	.rev_offs	= 0x0000,
1582
-	.sysc_offs	= 0x0004,
1583
-	.sysc_flags	= SYSC_HAS_SIDLEMODE,
1584
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
1585
-	.sysc_fields	= &omap_hwmod_sysc_type1,
1586
-};
1587
-
1588
-static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1589
-	.name	= "counter",
1590
-	.sysc	= &omap3xxx_counter_sysc,
1591
-};
1592
-
1593
-static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1594
-	.name		= "counter_32k",
1595
-	.class		= &omap3xxx_counter_hwmod_class,
1596
-	.clkdm_name	= "wkup_clkdm",
1597
-	.flags		= HWMOD_SWSUP_SIDLE,
1598
-	.main_clk	= "wkup_32k_fck",
1599
-	.prcm		= {
1600
-		.omap2	= {
1601
-			.module_offs = WKUP_MOD,
1602
-			.idlest_reg_id = 1,
1603
-			.idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1604
-		},
1605
-	},
1606
-};
1607
-
1608
-/*
16091483  * 'gpmc' class
16101484  * general purpose memory controller
16111485  */
....@@ -1917,25 +1791,6 @@
19171791 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
19181792 };
19191793 
1920
-
1921
-/* l4_wkup -> timer1 */
1922
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
1923
-	.master		= &omap3xxx_l4_wkup_hwmod,
1924
-	.slave		= &omap3xxx_timer1_hwmod,
1925
-	.clk		= "gpt1_ick",
1926
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1927
-};
1928
-
1929
-
1930
-/* l4_per -> timer2 */
1931
-static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
1932
-	.master		= &omap3xxx_l4_per_hwmod,
1933
-	.slave		= &omap3xxx_timer2_hwmod,
1934
-	.clk		= "gpt2_ick",
1935
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1936
-};
1937
-
1938
-
19391794 /* l4_per -> timer3 */
19401795 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
19411796 	.master		= &omap3xxx_l4_per_hwmod,
....@@ -2011,15 +1866,6 @@
20111866 	.master		= &omap3xxx_l4_core_hwmod,
20121867 	.slave		= &omap3xxx_timer11_hwmod,
20131868 	.clk		= "gpt11_ick",
2014
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2015
-};
2016
-
2017
-
2018
-/* l4_core -> timer12 */
2019
-static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2020
-	.master		= &omap3xxx_l4_sec_hwmod,
2021
-	.slave		= &omap3xxx_timer12_hwmod,
2022
-	.clk		= "gpt12_ick",
20231869 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
20241870 };
20251871 
....@@ -2240,23 +2086,6 @@
22402086 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
22412087 };
22422088 
2243
-/* dma_system -> L3 */
2244
-static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2245
-	.master		= &omap3xxx_dma_system_hwmod,
2246
-	.slave		= &omap3xxx_l3_main_hwmod,
2247
-	.clk		= "core_l3_ick",
2248
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2249
-};
2250
-
2251
-/* l4_cfg -> dma_system */
2252
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2253
-	.master		= &omap3xxx_l4_core_hwmod,
2254
-	.slave		= &omap3xxx_dma_system_hwmod,
2255
-	.clk		= "core_l4_ick",
2256
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2257
-};
2258
-
2259
-
22602089 /* l4_core -> mcbsp1 */
22612090 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
22622091 	.master		= &omap3xxx_l4_core_hwmod,
....@@ -2391,16 +2220,6 @@
23912220 	.flags		= OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
23922221 };
23932222 
2394
-/* l4_wkup -> 32ksync_counter */
2395
-
2396
-
2397
-static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2398
-	.master		= &omap3xxx_l4_wkup_hwmod,
2399
-	.slave		= &omap3xxx_counter_32k_hwmod,
2400
-	.clk		= "omap_32ksync_ick",
2401
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2402
-};
2403
-
24042223 /* am35xx has Davinci MDIO & EMAC */
24052224 static struct omap_hwmod_class am35xx_mdio_class = {
24062225 	.name = "davinci_mdio",
....@@ -2523,44 +2342,6 @@
25232342 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
25242343 };
25252344 
2526
-/* l4_core -> AES */
2527
-static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2528
-	.rev_offs	= 0x44,
2529
-	.sysc_offs	= 0x48,
2530
-	.syss_offs	= 0x4c,
2531
-	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2532
-			   SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2533
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2534
-	.sysc_fields	= &omap3xxx_aes_sysc_fields,
2535
-};
2536
-
2537
-static struct omap_hwmod_class omap3xxx_aes_class = {
2538
-	.name	= "aes",
2539
-	.sysc	= &omap3_aes_sysc,
2540
-};
2541
-
2542
-
2543
-static struct omap_hwmod omap3xxx_aes_hwmod = {
2544
-	.name		= "aes",
2545
-	.main_clk	= "aes2_ick",
2546
-	.prcm		= {
2547
-		.omap2 = {
2548
-			.module_offs = CORE_MOD,
2549
-			.idlest_reg_id = 1,
2550
-			.idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2551
-		},
2552
-	},
2553
-	.class		= &omap3xxx_aes_class,
2554
-};
2555
-
2556
-
2557
-static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2558
-	.master		= &omap3xxx_l4_core_hwmod,
2559
-	.slave		= &omap3xxx_aes_hwmod,
2560
-	.clk		= "aes2_ick",
2561
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2562
-};
2563
-
25642345 /*
25652346  * 'ssi' class
25662347  * synchronous serial interface (multichannel and full-duplex serial if)
....@@ -2617,8 +2398,6 @@
26172398 	&omap3_l4_core__i2c2,
26182399 	&omap3_l4_core__i2c3,
26192400 	&omap3xxx_l4_wkup__l4_sec,
2620
-	&omap3xxx_l4_wkup__timer1,
2621
-	&omap3xxx_l4_per__timer2,
26222401 	&omap3xxx_l4_per__timer3,
26232402 	&omap3xxx_l4_per__timer4,
26242403 	&omap3xxx_l4_per__timer5,
....@@ -2635,8 +2414,6 @@
26352414 	&omap3xxx_l4_per__gpio4,
26362415 	&omap3xxx_l4_per__gpio5,
26372416 	&omap3xxx_l4_per__gpio6,
2638
-	&omap3xxx_dma_system__l3,
2639
-	&omap3xxx_l4_core__dma_system,
26402417 	&omap3xxx_l4_core__mcbsp1,
26412418 	&omap3xxx_l4_per__mcbsp2,
26422419 	&omap3xxx_l4_per__mcbsp3,
....@@ -2648,24 +2425,7 @@
26482425 	&omap34xx_l4_core__mcspi2,
26492426 	&omap34xx_l4_core__mcspi3,
26502427 	&omap34xx_l4_core__mcspi4,
2651
-	&omap3xxx_l4_wkup__counter_32k,
26522428 	&omap3xxx_l3_main__gpmc,
2653
-	NULL,
2654
-};
2655
-
2656
-/* GP-only hwmod links */
2657
-static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2658
-	&omap3xxx_l4_sec__timer12,
2659
-	NULL,
2660
-};
2661
-
2662
-static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2663
-	&omap3xxx_l4_sec__timer12,
2664
-	NULL,
2665
-};
2666
-
2667
-static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2668
-	&omap3xxx_l4_sec__timer12,
26692429 	NULL,
26702430 };
26712431 
....@@ -2675,20 +2435,11 @@
26752435 	NULL,
26762436 };
26772437 
2678
-static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2679
-	&omap3xxx_l4_core__aes,
2680
-	NULL,
2681
-};
2682
-
26832438 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
26842439 	&omap3xxx_l4_core__sham,
26852440 	NULL
26862441 };
26872442 
2688
-static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2689
-	&omap3xxx_l4_core__aes,
2690
-	NULL
2691
-};
26922443 
26932444 /*
26942445  * Apparently the SHA/MD5 and AES accelerator IP blocks are
....@@ -2701,11 +2452,6 @@
27012452 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
27022453 	/* &omap3xxx_l4_core__sham, */
27032454 	NULL
2704
-};
2705
-
2706
-static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2707
-	/* &omap3xxx_l4_core__aes, */
2708
-	NULL,
27092455 };
27102456 
27112457 /* 3430ES1-only hwmod links */
....@@ -2842,8 +2588,7 @@
28422588 int __init omap3xxx_hwmod_init(void)
28432589 {
28442590 	int r;
2845
-	struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
2846
-	struct omap_hwmod_ocp_if **h_aes = NULL;
2591
+	struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
28472592 	struct device_node *bus;
28482593 	unsigned int rev;
28492594 
....@@ -2865,20 +2610,14 @@
28652610 	    rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
28662611 	    rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
28672612 		h = omap34xx_hwmod_ocp_ifs;
2868
-		h_gp = omap34xx_gp_hwmod_ocp_ifs;
28692613 		h_sham = omap34xx_sham_hwmod_ocp_ifs;
2870
-		h_aes = omap34xx_aes_hwmod_ocp_ifs;
28712614 	} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
28722615 		h = am35xx_hwmod_ocp_ifs;
2873
-		h_gp = am35xx_gp_hwmod_ocp_ifs;
28742616 		h_sham = am35xx_sham_hwmod_ocp_ifs;
2875
-		h_aes = am35xx_aes_hwmod_ocp_ifs;
28762617 	} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
28772618 		   rev == OMAP3630_REV_ES1_2) {
28782619 		h = omap36xx_hwmod_ocp_ifs;
2879
-		h_gp = omap36xx_gp_hwmod_ocp_ifs;
28802620 		h_sham = omap36xx_sham_hwmod_ocp_ifs;
2881
-		h_aes = omap36xx_aes_hwmod_ocp_ifs;
28822621 	} else {
28832622 		WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
28842623 		return -EINVAL;
....@@ -2887,13 +2626,6 @@
28872626 	r = omap_hwmod_register_links(h);
28882627 	if (r < 0)
28892628 		return r;
2890
-
2891
-	/* Register GP-only hwmod links. */
2892
-	if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
2893
-		r = omap_hwmod_register_links(h_gp);
2894
-		if (r < 0)
2895
-			return r;
2896
-	}
28972629 
28982630 	/*
28992631 	 * Register crypto hwmod links only if they are not disabled in DT.
....@@ -2908,11 +2640,6 @@
29082640 			goto put_node;
29092641 	}
29102642 
2911
-	if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
2912
-		r = omap_hwmod_register_links(h_aes);
2913
-		if (r < 0)
2914
-			goto put_node;
2915
-	}
29162643 	of_node_put(bus);
29172644 
29182645 	/*