~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,6 +1,6 @@
	1	+/* SPDX-License-Identifier: GPL-2.0-only */
1	2	/*
2	3	* Copyright 2014, Michael Ellerman, IBM Corp.
3		- * Licensed under GPLv2.
4	4	*/
5	5
6	6	#ifndef _SELFTESTS_POWERPC_REG_H
..	..	@@ -17,6 +17,7 @@
17	17	: "memory")
18	18
19	19	#define mb() asm volatile("sync" : : : "memory");
	20	+#define barrier() asm volatile("" : : : "memory");
20	21
21	22	#define SPRN_MMCR2 769
22	23	#define SPRN_MMCRA 770
..	..	@@ -56,6 +57,12 @@
56	57	#define SPRN_PPR 896 /* Program Priority Register */
57	58	#define SPRN_AMR 13 /* Authority Mask Register - problem state */
58	59
	60	+#define set_amr(v) asm volatile("isync;" \
	61	+ "mtspr " __stringify(SPRN_AMR) ",%0;" \
	62	+ "isync" : \
	63	+ : "r" ((unsigned long)(v)) \
	64	+ : "memory")
	65	+
59	66	/* TEXASR register bits */
60	67	#define TEXASR_FC 0xFE00000000000000
61	68	#define TEXASR_FP 0x0100000000000000
..	..	@@ -76,6 +83,16 @@
76	83	#define TEXASR_TE 0x0000000004000000
77	84	#define TEXASR_ROT 0x0000000002000000
78	85
	86	+/* MSR register bits */
	87	+#define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */
	88	+#define MSR_TS_T_LG 34 /* Trans Mem state: Active */
	89	+
	90	+#define __MASK(X) (1UL<<(X))
	91	+
	92	+/* macro to check TM MSR bits */
	93	+#define MSR_TS_S __MASK(MSR_TS_S_LG) /* Transaction Suspended */
	94	+#define MSR_TS_T __MASK(MSR_TS_T_LG) /* Transaction Transactional */
	95	+
79	96	/* Vector Instructions */
80	97	#define VSX_XX1(xs, ra, rb) (((xs) & 0x1f) << 21 \| ((ra) << 16) \| \
81	98	((rb) << 11) \| (((xs) >> 5)))